#include <pmon.h>
#define _LITTLE_ENDIAN 
#define MDC_MDIO_OPERATION 
#define MDC_MDIO_GPIO
/*
 * Data Type Declaration
 */
typedef enum rt_error_code_e
{
    RT_ERR_FAILED = -1,                             /* General Error                                                                    */

    /* 0x0000xxxx for common error code */
    RT_ERR_OK = 0,                                  /* 0x00000000, OK                                                                   */
    RT_ERR_INPUT,                                   /* 0x00000001, invalid input parameter                                              */
    RT_ERR_UNIT_ID,                                 /* 0x00000002, invalid unit id                                                      */
    RT_ERR_PORT_ID,                                 /* 0x00000003, invalid port id                                                      */
    RT_ERR_PORT_MASK,                               /* 0x00000004, invalid port mask                                                    */
    RT_ERR_PORT_LINKDOWN,                           /* 0x00000005, link down port status                                                */
    RT_ERR_ENTRY_INDEX,                             /* 0x00000006, invalid entry index                                                  */
    RT_ERR_NULL_POINTER,                            /* 0x00000007, input parameter is null pointer                                      */
    RT_ERR_QUEUE_ID,                                /* 0x00000008, invalid queue id                                                     */
    RT_ERR_QUEUE_NUM,                               /* 0x00000009, invalid queue number                                                 */
    RT_ERR_BUSYWAIT_TIMEOUT,                        /* 0x0000000a, busy watting time out                                                */
    RT_ERR_MAC,                                     /* 0x0000000b, invalid mac address                                                  */
    RT_ERR_OUT_OF_RANGE,                            /* 0x0000000c, input parameter out of range                                         */
    RT_ERR_CHIP_NOT_SUPPORTED,                      /* 0x0000000d, functions not supported by this chip model                           */
    RT_ERR_SMI,                                     /* 0x0000000e, SMI error                                                            */
    RT_ERR_NOT_INIT,                                /* 0x0000000f, The module is not initial                                            */
    RT_ERR_CHIP_NOT_FOUND,                          /* 0x00000010, The chip can not found                                               */
    RT_ERR_NOT_ALLOWED,                             /* 0x00000011, actions not allowed by the function                                  */
    RT_ERR_DRIVER_NOT_FOUND,                        /* 0x00000012, The driver can not found                                             */
    RT_ERR_SEM_LOCK_FAILED,                         /* 0x00000013, Failed to lock semaphore                                             */
    RT_ERR_SEM_UNLOCK_FAILED,                       /* 0x00000014, Failed to unlock semaphore                                           */
    RT_ERR_ENABLE,                                  /* 0x00000015, invalid enable parameter                                             */
    RT_ERR_TBL_FULL,                                /* 0x00000016, input table full                                                     */

   
    RT_ERR_END                                       /* The symbol is the latest symbol                                                  */
} rt_error_code_t;

#ifndef _RTL8370_REG_H_
#define _RTL8370_REG_H_

/************************************************************
auto-generated register address and field data
*************************************************************/

/* (16'h0000) port_reg */

#define    RTL8370_REG_PKTGEN_PORT0_CTRL    0x0001
#define    RTL8370_PKTGEN_PORT0_CTRL_STATUS_OFFSET    15
#define    RTL8370_PKTGEN_PORT0_CTRL_STATUS_MASK    0x8000
#define    RTL8370_PKTGEN_PORT0_CTRL_ENABLED_OFFSET    9
#define    RTL8370_PKTGEN_PORT0_CTRL_ENABLED_MASK    0x200
#define    RTL8370_PKTGEN_PORT0_CTRL_INC_BC_OFFSET    8
#define    RTL8370_PKTGEN_PORT0_CTRL_INC_BC_MASK    0x100
#define    RTL8370_PKTGEN_PORT0_CTRL_INC_SA_OFFSET    7
#define    RTL8370_PKTGEN_PORT0_CTRL_INC_SA_MASK    0x80
#define    RTL8370_PKTGEN_PORT0_CTRL_INC_DA_OFFSET    6
#define    RTL8370_PKTGEN_PORT0_CTRL_INC_DA_MASK    0x40
#define    RTL8370_PKTGEN_PORT0_CTRL_RANDOM_OFFSET    5
#define    RTL8370_PKTGEN_PORT0_CTRL_RANDOM_MASK    0x20
#define    RTL8370_PKTGEN_PORT0_CTRL_CRC_NO_ERROR_OFFSET    4
#define    RTL8370_PKTGEN_PORT0_CTRL_CRC_NO_ERROR_MASK    0x10
#define    RTL8370_PKTGEN_PORT0_CTRL_CMD_CLEAR_OFFSET    3
#define    RTL8370_PKTGEN_PORT0_CTRL_CMD_CLEAR_MASK    0x8
#define    RTL8370_PKTGEN_PORT0_CTRL_CMD_CONTINUE_OFFSET    2
#define    RTL8370_PKTGEN_PORT0_CTRL_CMD_CONTINUE_MASK    0x4
#define    RTL8370_PKTGEN_PORT0_CTRL_CMD_PAUSE_OFFSET    1
#define    RTL8370_PKTGEN_PORT0_CTRL_CMD_PAUSE_MASK    0x2
#define    RTL8370_PKTGEN_PORT0_CTRL_CMD_START_OFFSET    0
#define    RTL8370_PKTGEN_PORT0_CTRL_CMD_START_MASK    0x1

#define    RTL8370_REG_P0_DUMMY5    0x0002

#define    RTL8370_REG_PKTGEN_PORT0_DA0    0x0003

#define    RTL8370_REG_PKTGEN_PORT0_DA1    0x0004

#define    RTL8370_REG_PKTGEN_PORT0_DA2    0x0005

#define    RTL8370_REG_PKTGEN_PORT0_SA0    0x0006

#define    RTL8370_REG_PKTGEN_PORT0_SA1    0x0007

#define    RTL8370_REG_PKTGEN_PORT0_SA2    0x0008

#define    RTL8370_REG_PKTGEN_PORT0_COUNTER0    0x0009

#define    RTL8370_REG_PKTGEN_PORT0_COUNTER1    0x000a
#define    RTL8370_PKTGEN_PORT0_COUNTER1_OFFSET    0
#define    RTL8370_PKTGEN_PORT0_COUNTER1_MASK    0xFF

#define    RTL8370_REG_PKTGEN_PORT0_TX_LENGTH    0x000b
#define    RTL8370_PKTGEN_PORT0_TX_LENGTH_OFFSET    0
#define    RTL8370_PKTGEN_PORT0_TX_LENGTH_MASK    0x3FFF

#define    RTL8370_REG_PKTGEN_PORT0_MAX_LENGTH    0x000c
#define    RTL8370_PKTGEN_PORT0_MAX_LENGTH_OFFSET    0
#define    RTL8370_PKTGEN_PORT0_MAX_LENGTH_MASK    0x3FFF

#define    RTL8370_REG_P0_DUMMY6    0x000d

#define    RTL8370_REG_PORT0_MISC_CFG    0x000e
#define    RTL8370_PORT0_MISC_CFG_TIMER_OFFSET    12
#define    RTL8370_PORT0_MISC_CFG_TIMER_MASK    0xF000
#define    RTL8370_INGRESSBW_PORT0_FLOWCRTL_OFFSET    11
#define    RTL8370_INGRESSBW_PORT0_FLOWCRTL_MASK    0x800
#define    RTL8370_INGRESSBW_PORT0_IFG_OFFSET    10
#define    RTL8370_INGRESSBW_PORT0_IFG_MASK    0x400
#define    RTL8370_PORT0_MISC_CFG_RX_SPC_OFFSET    9
#define    RTL8370_PORT0_MISC_CFG_RX_SPC_MASK    0x200
#define    RTL8370_PORT0_MISC_CFG_CRC_SKIP_OFFSET    8
#define    RTL8370_PORT0_MISC_CFG_CRC_SKIP_MASK    0x100
#define    RTL8370_PORT0_MISC_CFG_MAC_LOOPBACK_OFFSET    6
#define    RTL8370_PORT0_MISC_CFG_MAC_LOOPBACK_MASK    0x40
#define    RTL8370_VLAN_PORT0_EGRESS_MODE_OFFSET    4
#define    RTL8370_VLAN_PORT0_EGRESS_MODE_MASK    0x30
#define    RTL8370_CONGESTION_PORT0_SUSTAIN_TIME_OFFSET    0
#define    RTL8370_CONGESTION_PORT0_SUSTAIN_TIME_MASK    0xF

#define    RTL8370_REG_INGRESSBW_PORT0_RATE_CRTL0    0x000f

#define    RTL8370_REG_INGRESSBW_PORT0_RATE_CRTL1    0x0010
#define    RTL8370_INGRESSBW_PORT0_RATE_CRTL1_DUMMY_OFFSET    1
#define    RTL8370_INGRESSBW_PORT0_RATE_CRTL1_DUMMY_MASK    0xFFFE
#define    RTL8370_INGRESSBW_PORT0_RATE16_OFFSET    0
#define    RTL8370_INGRESSBW_PORT0_RATE16_MASK    0x1

#define    RTL8370_REG_PORT0_FORCE_RATE0    0x0011

#define    RTL8370_REG_PORT0_FORCE_RATE1    0x0012

#define    RTL8370_REG_PORT0_CURENT_RATE0    0x0013

#define    RTL8370_REG_PORT0_CURENT_RATE1    0x0014

#define    RTL8370_REG_PORT0_PAGE_COUNTER    0x0015
#define    RTL8370_PORT0_PAGE_COUNTER_OFFSET    0
#define    RTL8370_PORT0_PAGE_COUNTER_MASK    0x7F

#define    RTL8370_REG_PAGEMETER_PORT0_CTRL0    0x0016

#define    RTL8370_REG_PAGEMETER_PORT0_CTRL1    0x0017
#define    RTL8370_PAGEMETER_PORT0_CTRL1_OFFSET    0
#define    RTL8370_PAGEMETER_PORT0_CTRL1_MASK    0x3F

#define    RTL8370_REG_PORT0_EEECFG    0x0018
#define    RTL8370_PORT0_EEECFG_EEEP_ENABLE_TX_OFFSET    14
#define    RTL8370_PORT0_EEECFG_EEEP_ENABLE_TX_MASK    0x4000
#define    RTL8370_PORT0_EEECFG_EEEP_ENABLE_RX_OFFSET    13
#define    RTL8370_PORT0_EEECFG_EEEP_ENABLE_RX_MASK    0x2000
#define    RTL8370_PORT0_EEECFG_EEE_FORCE_OFFSET    12
#define    RTL8370_PORT0_EEECFG_EEE_FORCE_MASK    0x1000
#define    RTL8370_PORT0_EEECFG_EEE_100M_OFFSET    11
#define    RTL8370_PORT0_EEECFG_EEE_100M_MASK    0x800
#define    RTL8370_PORT0_EEECFG_EEE_GIGA_OFFSET    10
#define    RTL8370_PORT0_EEECFG_EEE_GIGA_MASK    0x400
#define    RTL8370_PORT0_EEECFG_EEE_TX_OFFSET    9
#define    RTL8370_PORT0_EEECFG_EEE_TX_MASK    0x200
#define    RTL8370_PORT0_EEECFG_EEE_RX_OFFSET    8
#define    RTL8370_PORT0_EEECFG_EEE_RX_MASK    0x100
#define    RTL8370_PORT0_EEECFG_EEE_LPI_OFFSET    5
#define    RTL8370_PORT0_EEECFG_EEE_LPI_MASK    0x20
#define    RTL8370_PORT0_EEECFG_EEE_TX_LPI_OFFSET    4
#define    RTL8370_PORT0_EEECFG_EEE_TX_LPI_MASK    0x10
#define    RTL8370_PORT0_EEECFG_EEE_RX_LPI_OFFSET    3
#define    RTL8370_PORT0_EEECFG_EEE_RX_LPI_MASK    0x8
#define    RTL8370_PORT0_EEECFG_EEE_PAUSE_INDICATOR_OFFSET    2
#define    RTL8370_PORT0_EEECFG_EEE_PAUSE_INDICATOR_MASK    0x4
#define    RTL8370_PORT0_EEECFG_EEE_WAKE_REQ_OFFSET    1
#define    RTL8370_PORT0_EEECFG_EEE_WAKE_REQ_MASK    0x2
#define    RTL8370_PORT0_EEECFG_EEE_SLEEP_REQ_OFFSET    0
#define    RTL8370_PORT0_EEECFG_EEE_SLEEP_REQ_MASK    0x1

#define    RTL8370_REG_P0EEETXMTR    0x0019

#define    RTL8370_REG_P0EEERXMTR    0x001a

#define    RTL8370_REG_P0EEEPTXMTR    0x001b

#define    RTL8370_REG_P0EEEPRXMTR    0x001c

#define    RTL8370_REG_P0_DUMMY2    0x001d

#define    RTL8370_REG_P0_DUMMY3    0x001e

#define    RTL8370_REG_P0_DUMMY4    0x001f

#define    RTL8370_REG_PKTGEN_PORT1_CTRL    0x0021
#define    RTL8370_PKTGEN_PORT1_CTRL_STATUS_OFFSET    15
#define    RTL8370_PKTGEN_PORT1_CTRL_STATUS_MASK    0x8000
#define    RTL8370_PKTGEN_PORT1_CTRL_ENABLED_OFFSET    9
#define    RTL8370_PKTGEN_PORT1_CTRL_ENABLED_MASK    0x200
#define    RTL8370_PKTGEN_PORT1_CTRL_INC_BC_OFFSET    8
#define    RTL8370_PKTGEN_PORT1_CTRL_INC_BC_MASK    0x100
#define    RTL8370_PKTGEN_PORT1_CTRL_INC_SA_OFFSET    7
#define    RTL8370_PKTGEN_PORT1_CTRL_INC_SA_MASK    0x80
#define    RTL8370_PKTGEN_PORT1_CTRL_INC_DA_OFFSET    6
#define    RTL8370_PKTGEN_PORT1_CTRL_INC_DA_MASK    0x40
#define    RTL8370_PKTGEN_PORT1_CTRL_RANDOM_OFFSET    5
#define    RTL8370_PKTGEN_PORT1_CTRL_RANDOM_MASK    0x20
#define    RTL8370_PKTGEN_PORT1_CTRL_CRC_NO_ERROR_OFFSET    4
#define    RTL8370_PKTGEN_PORT1_CTRL_CRC_NO_ERROR_MASK    0x10
#define    RTL8370_PKTGEN_PORT1_CTRL_CMD_CLEAR_OFFSET    3
#define    RTL8370_PKTGEN_PORT1_CTRL_CMD_CLEAR_MASK    0x8
#define    RTL8370_PKTGEN_PORT1_CTRL_CMD_CONTINUE_OFFSET    2
#define    RTL8370_PKTGEN_PORT1_CTRL_CMD_CONTINUE_MASK    0x4
#define    RTL8370_PKTGEN_PORT1_CTRL_CMD_PAUSE_OFFSET    1
#define    RTL8370_PKTGEN_PORT1_CTRL_CMD_PAUSE_MASK    0x2
#define    RTL8370_PKTGEN_PORT1_CTRL_CMD_START_OFFSET    0
#define    RTL8370_PKTGEN_PORT1_CTRL_CMD_START_MASK    0x1

#define    RTL8370_REG_P1_DUMMY5    0x0022

#define    RTL8370_REG_PKTGEN_PORT1_DA0    0x0023

#define    RTL8370_REG_PKTGEN_PORT1_DA1    0x0024

#define    RTL8370_REG_PKTGEN_PORT1_DA2    0x0025

#define    RTL8370_REG_PKTGEN_PORT1_SA0    0x0026

#define    RTL8370_REG_PKTGEN_PORT1_SA1    0x0027

#define    RTL8370_REG_PKTGEN_PORT1_SA2    0x0028

#define    RTL8370_REG_PKTGEN_PORT1_COUNTER0    0x0029

#define    RTL8370_REG_PKTGEN_PORT1_COUNTER1    0x002a
#define    RTL8370_PKTGEN_PORT1_COUNTER1_OFFSET    0
#define    RTL8370_PKTGEN_PORT1_COUNTER1_MASK    0xFF

#define    RTL8370_REG_PKTGEN_PORT1_TX_LENGTH    0x002b
#define    RTL8370_PKTGEN_PORT1_TX_LENGTH_OFFSET    0
#define    RTL8370_PKTGEN_PORT1_TX_LENGTH_MASK    0x3FFF

#define    RTL8370_REG_PKTGEN_PORT1_MAX_LENGTH    0x002c
#define    RTL8370_PKTGEN_PORT1_MAX_LENGTH_OFFSET    0
#define    RTL8370_PKTGEN_PORT1_MAX_LENGTH_MASK    0x3FFF

#define    RTL8370_REG_P1_DUMMY6    0x002d

#define    RTL8370_REG_PORT1_MISC_CFG    0x002e
#define    RTL8370_PORT1_MISC_CFG_TIMER_OFFSET    12
#define    RTL8370_PORT1_MISC_CFG_TIMER_MASK    0xF000
#define    RTL8370_INGRESSBW_PORT1_FLOWCRTL_OFFSET    11
#define    RTL8370_INGRESSBW_PORT1_FLOWCRTL_MASK    0x800
#define    RTL8370_INGRESSBW_PORT1_IFG_OFFSET    10
#define    RTL8370_INGRESSBW_PORT1_IFG_MASK    0x400
#define    RTL8370_PORT1_MISC_CFG_RX_SPC_OFFSET    9
#define    RTL8370_PORT1_MISC_CFG_RX_SPC_MASK    0x200
#define    RTL8370_PORT1_MISC_CFG_CRC_SKIP_OFFSET    8
#define    RTL8370_PORT1_MISC_CFG_CRC_SKIP_MASK    0x100
#define    RTL8370_PORT1_MISC_CFG_MAC_LOOPBACK_OFFSET    6
#define    RTL8370_PORT1_MISC_CFG_MAC_LOOPBACK_MASK    0x40
#define    RTL8370_VLAN_PORT1_EGRESS_MODE_OFFSET    4
#define    RTL8370_VLAN_PORT1_EGRESS_MODE_MASK    0x30
#define    RTL8370_CONGESTION_PORT1_SUSTAIN_TIME_OFFSET    0
#define    RTL8370_CONGESTION_PORT1_SUSTAIN_TIME_MASK    0xF

#define    RTL8370_REG_INGRESSBW_PORT1_RATE_CRTL0    0x002f

#define    RTL8370_REG_INGRESSBW_PORT1_RATE_CRTL1    0x0030
#define    RTL8370_INGRESSBW_PORT1_RATE_CRTL1_DUMMY_OFFSET    1
#define    RTL8370_INGRESSBW_PORT1_RATE_CRTL1_DUMMY_MASK    0xFFFE
#define    RTL8370_INGRESSBW_PORT1_RATE16_OFFSET    0
#define    RTL8370_INGRESSBW_PORT1_RATE16_MASK    0x1

#define    RTL8370_REG_PORT1_FORCE_RATE0    0x0031

#define    RTL8370_REG_PORT1_FORCE_RATE1    0x0032

#define    RTL8370_REG_PORT1_CURENT_RATE0    0x0033

#define    RTL8370_REG_PORT1_CURENT_RATE1    0x0034

#define    RTL8370_REG_PORT1_PAGE_COUNTER    0x0035
#define    RTL8370_PORT1_PAGE_COUNTER_OFFSET    0
#define    RTL8370_PORT1_PAGE_COUNTER_MASK    0x7F

#define    RTL8370_REG_PAGEMETER_PORT1_CTRL0    0x0036

#define    RTL8370_REG_PAGEMETER_PORT1_CTRL1    0x0037
#define    RTL8370_PAGEMETER_PORT1_CTRL1_OFFSET    0
#define    RTL8370_PAGEMETER_PORT1_CTRL1_MASK    0x3F

#define    RTL8370_REG_PORT1_EEECFG    0x0038
#define    RTL8370_PORT1_EEECFG_EEEP_ENABLE_TX_OFFSET    14
#define    RTL8370_PORT1_EEECFG_EEEP_ENABLE_TX_MASK    0x4000
#define    RTL8370_PORT1_EEECFG_EEEP_ENABLE_RX_OFFSET    13
#define    RTL8370_PORT1_EEECFG_EEEP_ENABLE_RX_MASK    0x2000
#define    RTL8370_PORT1_EEECFG_EEE_FORCE_OFFSET    12
#define    RTL8370_PORT1_EEECFG_EEE_FORCE_MASK    0x1000
#define    RTL8370_PORT1_EEECFG_EEE_100M_OFFSET    11
#define    RTL8370_PORT1_EEECFG_EEE_100M_MASK    0x800
#define    RTL8370_PORT1_EEECFG_EEE_GIGA_OFFSET    10
#define    RTL8370_PORT1_EEECFG_EEE_GIGA_MASK    0x400
#define    RTL8370_PORT1_EEECFG_EEE_TX_OFFSET    9
#define    RTL8370_PORT1_EEECFG_EEE_TX_MASK    0x200
#define    RTL8370_PORT1_EEECFG_EEE_RX_OFFSET    8
#define    RTL8370_PORT1_EEECFG_EEE_RX_MASK    0x100
#define    RTL8370_PORT1_EEECFG_EEE_LPI_OFFSET    5
#define    RTL8370_PORT1_EEECFG_EEE_LPI_MASK    0x20
#define    RTL8370_PORT1_EEECFG_EEE_TX_LPI_OFFSET    4
#define    RTL8370_PORT1_EEECFG_EEE_TX_LPI_MASK    0x10
#define    RTL8370_PORT1_EEECFG_EEE_RX_LPI_OFFSET    3
#define    RTL8370_PORT1_EEECFG_EEE_RX_LPI_MASK    0x8
#define    RTL8370_PORT1_EEECFG_EEE_PAUSE_INDICATOR_OFFSET    2
#define    RTL8370_PORT1_EEECFG_EEE_PAUSE_INDICATOR_MASK    0x4
#define    RTL8370_PORT1_EEECFG_EEE_WAKE_REQ_OFFSET    1
#define    RTL8370_PORT1_EEECFG_EEE_WAKE_REQ_MASK    0x2
#define    RTL8370_PORT1_EEECFG_EEE_SLEEP_REQ_OFFSET    0
#define    RTL8370_PORT1_EEECFG_EEE_SLEEP_REQ_MASK    0x1

#define    RTL8370_REG_P1EEETXMTR    0x0039

#define    RTL8370_REG_P1EEERXMTR    0x003a

#define    RTL8370_REG_P1EEEPTXMTR    0x003b

#define    RTL8370_REG_P1EEEPRXMTR    0x003c

#define    RTL8370_REG_P1_DUMMY2    0x003d

#define    RTL8370_REG_P1_DUMMY3    0x003e

#define    RTL8370_REG_P1_DUMMY4    0x003f

#define    RTL8370_REG_PKTGEN_PORT2_CTRL    0x0041
#define    RTL8370_PKTGEN_PORT2_CTRL_STATUS_OFFSET    15
#define    RTL8370_PKTGEN_PORT2_CTRL_STATUS_MASK    0x8000
#define    RTL8370_PKTGEN_PORT2_CTRL_ENABLED_OFFSET    9
#define    RTL8370_PKTGEN_PORT2_CTRL_ENABLED_MASK    0x200
#define    RTL8370_PKTGEN_PORT2_CTRL_INC_BC_OFFSET    8
#define    RTL8370_PKTGEN_PORT2_CTRL_INC_BC_MASK    0x100
#define    RTL8370_PKTGEN_PORT2_CTRL_INC_SA_OFFSET    7
#define    RTL8370_PKTGEN_PORT2_CTRL_INC_SA_MASK    0x80
#define    RTL8370_PKTGEN_PORT2_CTRL_INC_DA_OFFSET    6
#define    RTL8370_PKTGEN_PORT2_CTRL_INC_DA_MASK    0x40
#define    RTL8370_PKTGEN_PORT2_CTRL_RANDOM_OFFSET    5
#define    RTL8370_PKTGEN_PORT2_CTRL_RANDOM_MASK    0x20
#define    RTL8370_PKTGEN_PORT2_CTRL_CRC_NO_ERROR_OFFSET    4
#define    RTL8370_PKTGEN_PORT2_CTRL_CRC_NO_ERROR_MASK    0x10
#define    RTL8370_PKTGEN_PORT2_CTRL_CMD_CLEAR_OFFSET    3
#define    RTL8370_PKTGEN_PORT2_CTRL_CMD_CLEAR_MASK    0x8
#define    RTL8370_PKTGEN_PORT2_CTRL_CMD_CONTINUE_OFFSET    2
#define    RTL8370_PKTGEN_PORT2_CTRL_CMD_CONTINUE_MASK    0x4
#define    RTL8370_PKTGEN_PORT2_CTRL_CMD_PAUSE_OFFSET    1
#define    RTL8370_PKTGEN_PORT2_CTRL_CMD_PAUSE_MASK    0x2
#define    RTL8370_PKTGEN_PORT2_CTRL_CMD_START_OFFSET    0
#define    RTL8370_PKTGEN_PORT2_CTRL_CMD_START_MASK    0x1

#define    RTL8370_REG_P2_DUMMY5    0x0042

#define    RTL8370_REG_PKTGEN_PORT2_DA0    0x0043

#define    RTL8370_REG_PKTGEN_PORT2_DA1    0x0044

#define    RTL8370_REG_PKTGEN_PORT2_DA2    0x0045

#define    RTL8370_REG_PKTGEN_PORT2_SA0    0x0046

#define    RTL8370_REG_PKTGEN_PORT2_SA1    0x0047

#define    RTL8370_REG_PKTGEN_PORT2_SA2    0x0048

#define    RTL8370_REG_PKTGEN_PORT2_COUNTER0    0x0049

#define    RTL8370_REG_PKTGEN_PORT2_COUNTER1    0x004a
#define    RTL8370_PKTGEN_PORT2_COUNTER1_OFFSET    0
#define    RTL8370_PKTGEN_PORT2_COUNTER1_MASK    0xFF

#define    RTL8370_REG_PKTGEN_PORT2_TX_LENGTH    0x004b
#define    RTL8370_PKTGEN_PORT2_TX_LENGTH_OFFSET    0
#define    RTL8370_PKTGEN_PORT2_TX_LENGTH_MASK    0x3FFF

#define    RTL8370_REG_PKTGEN_PORT2_MAX_LENGTH    0x004c
#define    RTL8370_PKTGEN_PORT2_MAX_LENGTH_OFFSET    0
#define    RTL8370_PKTGEN_PORT2_MAX_LENGTH_MASK    0x3FFF

#define    RTL8370_REG_P2_DUMMY6    0x004d

#define    RTL8370_REG_PORT2_MISC_CFG    0x004e
#define    RTL8370_PORT2_MISC_CFG_TIMER_OFFSET    12
#define    RTL8370_PORT2_MISC_CFG_TIMER_MASK    0xF000
#define    RTL8370_INGRESSBW_PORT2_FLOWCRTL_OFFSET    11
#define    RTL8370_INGRESSBW_PORT2_FLOWCRTL_MASK    0x800
#define    RTL8370_INGRESSBW_PORT2_IFG_OFFSET    10
#define    RTL8370_INGRESSBW_PORT2_IFG_MASK    0x400
#define    RTL8370_PORT2_MISC_CFG_RX_SPC_OFFSET    9
#define    RTL8370_PORT2_MISC_CFG_RX_SPC_MASK    0x200
#define    RTL8370_PORT2_MISC_CFG_CRC_SKIP_OFFSET    8
#define    RTL8370_PORT2_MISC_CFG_CRC_SKIP_MASK    0x100
#define    RTL8370_PORT2_MISC_CFG_MAC_LOOPBACK_OFFSET    6
#define    RTL8370_PORT2_MISC_CFG_MAC_LOOPBACK_MASK    0x40
#define    RTL8370_VLAN_PORT2_EGRESS_MODE_OFFSET    4
#define    RTL8370_VLAN_PORT2_EGRESS_MODE_MASK    0x30
#define    RTL8370_CONGESTION_PORT2_SUSTAIN_TIME_OFFSET    0
#define    RTL8370_CONGESTION_PORT2_SUSTAIN_TIME_MASK    0xF

#define    RTL8370_REG_INGRESSBW_PORT2_RATE_CRTL0    0x004f

#define    RTL8370_REG_INGRESSBW_PORT2_RATE_CRTL1    0x0050
#define    RTL8370_INGRESSBW_PORT2_RATE_CRTL1_DUMMY_OFFSET    1
#define    RTL8370_INGRESSBW_PORT2_RATE_CRTL1_DUMMY_MASK    0xFFFE
#define    RTL8370_INGRESSBW_PORT2_RATE16_OFFSET    0
#define    RTL8370_INGRESSBW_PORT2_RATE16_MASK    0x1

#define    RTL8370_REG_PORT2_FORCE_RATE0    0x0051

#define    RTL8370_REG_PORT2_FORCE_RATE1    0x0052

#define    RTL8370_REG_PORT2_CURENT_RATE0    0x0053

#define    RTL8370_REG_PORT2_CURENT_RATE1    0x0054

#define    RTL8370_REG_PORT2_PAGE_COUNTER    0x0055
#define    RTL8370_PORT2_PAGE_COUNTER_OFFSET    0
#define    RTL8370_PORT2_PAGE_COUNTER_MASK    0x7F

#define    RTL8370_REG_PAGEMETER_PORT2_CTRL0    0x0056

#define    RTL8370_REG_PAGEMETER_PORT2_CTRL1    0x0057
#define    RTL8370_PAGEMETER_PORT2_CTRL1_OFFSET    0
#define    RTL8370_PAGEMETER_PORT2_CTRL1_MASK    0x3F

#define    RTL8370_REG_PORT2_EEECFG    0x0058
#define    RTL8370_PORT2_EEECFG_EEEP_ENABLE_TX_OFFSET    14
#define    RTL8370_PORT2_EEECFG_EEEP_ENABLE_TX_MASK    0x4000
#define    RTL8370_PORT2_EEECFG_EEEP_ENABLE_RX_OFFSET    13
#define    RTL8370_PORT2_EEECFG_EEEP_ENABLE_RX_MASK    0x2000
#define    RTL8370_PORT2_EEECFG_EEE_FORCE_OFFSET    12
#define    RTL8370_PORT2_EEECFG_EEE_FORCE_MASK    0x1000
#define    RTL8370_PORT2_EEECFG_EEE_100M_OFFSET    11
#define    RTL8370_PORT2_EEECFG_EEE_100M_MASK    0x800
#define    RTL8370_PORT2_EEECFG_EEE_GIGA_OFFSET    10
#define    RTL8370_PORT2_EEECFG_EEE_GIGA_MASK    0x400
#define    RTL8370_PORT2_EEECFG_EEE_TX_OFFSET    9
#define    RTL8370_PORT2_EEECFG_EEE_TX_MASK    0x200
#define    RTL8370_PORT2_EEECFG_EEE_RX_OFFSET    8
#define    RTL8370_PORT2_EEECFG_EEE_RX_MASK    0x100
#define    RTL8370_PORT2_EEECFG_EEE_LPI_OFFSET    5
#define    RTL8370_PORT2_EEECFG_EEE_LPI_MASK    0x20
#define    RTL8370_PORT2_EEECFG_EEE_TX_LPI_OFFSET    4
#define    RTL8370_PORT2_EEECFG_EEE_TX_LPI_MASK    0x10
#define    RTL8370_PORT2_EEECFG_EEE_RX_LPI_OFFSET    3
#define    RTL8370_PORT2_EEECFG_EEE_RX_LPI_MASK    0x8
#define    RTL8370_PORT2_EEECFG_EEE_PAUSE_INDICATOR_OFFSET    2
#define    RTL8370_PORT2_EEECFG_EEE_PAUSE_INDICATOR_MASK    0x4
#define    RTL8370_PORT2_EEECFG_EEE_WAKE_REQ_OFFSET    1
#define    RTL8370_PORT2_EEECFG_EEE_WAKE_REQ_MASK    0x2
#define    RTL8370_PORT2_EEECFG_EEE_SLEEP_REQ_OFFSET    0
#define    RTL8370_PORT2_EEECFG_EEE_SLEEP_REQ_MASK    0x1

#define    RTL8370_REG_P2EEETXMTR    0x0059

#define    RTL8370_REG_P2EEERXMTR    0x005a

#define    RTL8370_REG_P2EEEPTXMTR    0x005b

#define    RTL8370_REG_P2EEEPRXMTR    0x005c

#define    RTL8370_REG_P2_DUMMY2    0x005d

#define    RTL8370_REG_P2_DUMMY3    0x005e

#define    RTL8370_REG_P2_DUMMY4    0x005f

#define    RTL8370_REG_PKTGEN_PORT3_CTRL    0x0061
#define    RTL8370_PKTGEN_PORT3_CTRL_STATUS_OFFSET    15
#define    RTL8370_PKTGEN_PORT3_CTRL_STATUS_MASK    0x8000
#define    RTL8370_PKTGEN_PORT3_CTRL_ENABLED_OFFSET    9
#define    RTL8370_PKTGEN_PORT3_CTRL_ENABLED_MASK    0x200
#define    RTL8370_PKTGEN_PORT3_CTRL_INC_BC_OFFSET    8
#define    RTL8370_PKTGEN_PORT3_CTRL_INC_BC_MASK    0x100
#define    RTL8370_PKTGEN_PORT3_CTRL_INC_SA_OFFSET    7
#define    RTL8370_PKTGEN_PORT3_CTRL_INC_SA_MASK    0x80
#define    RTL8370_PKTGEN_PORT3_CTRL_INC_DA_OFFSET    6
#define    RTL8370_PKTGEN_PORT3_CTRL_INC_DA_MASK    0x40
#define    RTL8370_PKTGEN_PORT3_CTRL_RANDOM_OFFSET    5
#define    RTL8370_PKTGEN_PORT3_CTRL_RANDOM_MASK    0x20
#define    RTL8370_PKTGEN_PORT3_CTRL_CRC_NO_ERROR_OFFSET    4
#define    RTL8370_PKTGEN_PORT3_CTRL_CRC_NO_ERROR_MASK    0x10
#define    RTL8370_PKTGEN_PORT3_CTRL_CMD_CLEAR_OFFSET    3
#define    RTL8370_PKTGEN_PORT3_CTRL_CMD_CLEAR_MASK    0x8
#define    RTL8370_PKTGEN_PORT3_CTRL_CMD_CONTINUE_OFFSET    2
#define    RTL8370_PKTGEN_PORT3_CTRL_CMD_CONTINUE_MASK    0x4
#define    RTL8370_PKTGEN_PORT3_CTRL_CMD_PAUSE_OFFSET    1
#define    RTL8370_PKTGEN_PORT3_CTRL_CMD_PAUSE_MASK    0x2
#define    RTL8370_PKTGEN_PORT3_CTRL_CMD_START_OFFSET    0
#define    RTL8370_PKTGEN_PORT3_CTRL_CMD_START_MASK    0x1

#define    RTL8370_REG_P3_DUMMY5    0x0062

#define    RTL8370_REG_PKTGEN_PORT3_DA0    0x0063

#define    RTL8370_REG_PKTGEN_PORT3_DA1    0x0064

#define    RTL8370_REG_PKTGEN_PORT3_DA2    0x0065

#define    RTL8370_REG_PKTGEN_PORT3_SA0    0x0066

#define    RTL8370_REG_PKTGEN_PORT3_SA1    0x0067

#define    RTL8370_REG_PKTGEN_PORT3_SA2    0x0068

#define    RTL8370_REG_PKTGEN_PORT3_COUNTER0    0x0069

#define    RTL8370_REG_PKTGEN_PORT3_COUNTER1    0x006a
#define    RTL8370_PKTGEN_PORT3_COUNTER1_OFFSET    0
#define    RTL8370_PKTGEN_PORT3_COUNTER1_MASK    0xFF

#define    RTL8370_REG_PKTGEN_PORT3_TX_LENGTH    0x006b
#define    RTL8370_PKTGEN_PORT3_TX_LENGTH_OFFSET    0
#define    RTL8370_PKTGEN_PORT3_TX_LENGTH_MASK    0x3FFF

#define    RTL8370_REG_PKTGEN_PORT3_MAX_LENGTH    0x006c
#define    RTL8370_PKTGEN_PORT3_MAX_LENGTH_OFFSET    0
#define    RTL8370_PKTGEN_PORT3_MAX_LENGTH_MASK    0x3FFF

#define    RTL8370_REG_P3_DUMMY6    0x006d

#define    RTL8370_REG_PORT3_MISC_CFG    0x006e
#define    RTL8370_PORT3_MISC_CFG_TIMER_OFFSET    12
#define    RTL8370_PORT3_MISC_CFG_TIMER_MASK    0xF000
#define    RTL8370_INGRESSBW_PORT3_FLOWCRTL_OFFSET    11
#define    RTL8370_INGRESSBW_PORT3_FLOWCRTL_MASK    0x800
#define    RTL8370_INGRESSBW_PORT3_IFG_OFFSET    10
#define    RTL8370_INGRESSBW_PORT3_IFG_MASK    0x400
#define    RTL8370_PORT3_MISC_CFG_RX_SPC_OFFSET    9
#define    RTL8370_PORT3_MISC_CFG_RX_SPC_MASK    0x200
#define    RTL8370_PORT3_MISC_CFG_CRC_SKIP_OFFSET    8
#define    RTL8370_PORT3_MISC_CFG_CRC_SKIP_MASK    0x100
#define    RTL8370_PORT3_MISC_CFG_MAC_LOOPBACK_OFFSET    6
#define    RTL8370_PORT3_MISC_CFG_MAC_LOOPBACK_MASK    0x40
#define    RTL8370_VLAN_PORT3_EGRESS_MODE_OFFSET    4
#define    RTL8370_VLAN_PORT3_EGRESS_MODE_MASK    0x30
#define    RTL8370_CONGESTION_PORT3_SUSTAIN_TIME_OFFSET    0
#define    RTL8370_CONGESTION_PORT3_SUSTAIN_TIME_MASK    0xF

#define    RTL8370_REG_INGRESSBW_PORT3_RATE_CRTL0    0x006f

#define    RTL8370_REG_INGRESSBW_PORT3_RATE_CRTL1    0x0070
#define    RTL8370_INGRESSBW_PORT3_RATE_CRTL1_DUMMY_OFFSET    1
#define    RTL8370_INGRESSBW_PORT3_RATE_CRTL1_DUMMY_MASK    0xFFFE
#define    RTL8370_INGRESSBW_PORT3_RATE16_OFFSET    0
#define    RTL8370_INGRESSBW_PORT3_RATE16_MASK    0x1

#define    RTL8370_REG_PORT3_FORCE_RATE0    0x0071

#define    RTL8370_REG_PORT3_FORCE_RATE1    0x0072

#define    RTL8370_REG_PORT3_CURENT_RATE0    0x0073

#define    RTL8370_REG_PORT3_CURENT_RATE1    0x0074

#define    RTL8370_REG_PORT3_PAGE_COUNTER    0x0075
#define    RTL8370_PORT3_PAGE_COUNTER_OFFSET    0
#define    RTL8370_PORT3_PAGE_COUNTER_MASK    0x7F

#define    RTL8370_REG_PAGEMETER_PORT3_CTRL0    0x0076

#define    RTL8370_REG_PAGEMETER_PORT3_CTRL1    0x0077
#define    RTL8370_PAGEMETER_PORT3_CTRL1_OFFSET    0
#define    RTL8370_PAGEMETER_PORT3_CTRL1_MASK    0x3F

#define    RTL8370_REG_PORT3_EEECFG    0x0078
#define    RTL8370_PORT3_EEECFG_EEEP_ENABLE_TX_OFFSET    14
#define    RTL8370_PORT3_EEECFG_EEEP_ENABLE_TX_MASK    0x4000
#define    RTL8370_PORT3_EEECFG_EEEP_ENABLE_RX_OFFSET    13
#define    RTL8370_PORT3_EEECFG_EEEP_ENABLE_RX_MASK    0x2000
#define    RTL8370_PORT3_EEECFG_EEE_FORCE_OFFSET    12
#define    RTL8370_PORT3_EEECFG_EEE_FORCE_MASK    0x1000
#define    RTL8370_PORT3_EEECFG_EEE_100M_OFFSET    11
#define    RTL8370_PORT3_EEECFG_EEE_100M_MASK    0x800
#define    RTL8370_PORT3_EEECFG_EEE_GIGA_OFFSET    10
#define    RTL8370_PORT3_EEECFG_EEE_GIGA_MASK    0x400
#define    RTL8370_PORT3_EEECFG_EEE_TX_OFFSET    9
#define    RTL8370_PORT3_EEECFG_EEE_TX_MASK    0x200
#define    RTL8370_PORT3_EEECFG_EEE_RX_OFFSET    8
#define    RTL8370_PORT3_EEECFG_EEE_RX_MASK    0x100
#define    RTL8370_PORT3_EEECFG_EEE_LPI_OFFSET    5
#define    RTL8370_PORT3_EEECFG_EEE_LPI_MASK    0x20
#define    RTL8370_PORT3_EEECFG_EEE_TX_LPI_OFFSET    4
#define    RTL8370_PORT3_EEECFG_EEE_TX_LPI_MASK    0x10
#define    RTL8370_PORT3_EEECFG_EEE_RX_LPI_OFFSET    3
#define    RTL8370_PORT3_EEECFG_EEE_RX_LPI_MASK    0x8
#define    RTL8370_PORT3_EEECFG_EEE_PAUSE_INDICATOR_OFFSET    2
#define    RTL8370_PORT3_EEECFG_EEE_PAUSE_INDICATOR_MASK    0x4
#define    RTL8370_PORT3_EEECFG_EEE_WAKE_REQ_OFFSET    1
#define    RTL8370_PORT3_EEECFG_EEE_WAKE_REQ_MASK    0x2
#define    RTL8370_PORT3_EEECFG_EEE_SLEEP_REQ_OFFSET    0
#define    RTL8370_PORT3_EEECFG_EEE_SLEEP_REQ_MASK    0x1

#define    RTL8370_REG_P3EEETXMTR    0x0079

#define    RTL8370_REG_P3EEERXMTR    0x007a

#define    RTL8370_REG_P3EEEPTXMTR    0x007b

#define    RTL8370_REG_P3EEEPRXMTR    0x007c

#define    RTL8370_REG_P3_DUMMY2    0x007d

#define    RTL8370_REG_P3_DUMMY3    0x007e

#define    RTL8370_REG_P3_DUMMY4    0x007f

#define    RTL8370_REG_PKTGEN_PORT4_CTRL    0x0081
#define    RTL8370_PKTGEN_PORT4_CTRL_STATUS_OFFSET    15
#define    RTL8370_PKTGEN_PORT4_CTRL_STATUS_MASK    0x8000
#define    RTL8370_PKTGEN_PORT4_CTRL_ENABLED_OFFSET    9
#define    RTL8370_PKTGEN_PORT4_CTRL_ENABLED_MASK    0x200
#define    RTL8370_PKTGEN_PORT4_CTRL_INC_BC_OFFSET    8
#define    RTL8370_PKTGEN_PORT4_CTRL_INC_BC_MASK    0x100
#define    RTL8370_PKTGEN_PORT4_CTRL_INC_SA_OFFSET    7
#define    RTL8370_PKTGEN_PORT4_CTRL_INC_SA_MASK    0x80
#define    RTL8370_PKTGEN_PORT4_CTRL_INC_DA_OFFSET    6
#define    RTL8370_PKTGEN_PORT4_CTRL_INC_DA_MASK    0x40
#define    RTL8370_PKTGEN_PORT4_CTRL_RANDOM_OFFSET    5
#define    RTL8370_PKTGEN_PORT4_CTRL_RANDOM_MASK    0x20
#define    RTL8370_PKTGEN_PORT4_CTRL_CRC_NO_ERROR_OFFSET    4
#define    RTL8370_PKTGEN_PORT4_CTRL_CRC_NO_ERROR_MASK    0x10
#define    RTL8370_PKTGEN_PORT4_CTRL_CMD_CLEAR_OFFSET    3
#define    RTL8370_PKTGEN_PORT4_CTRL_CMD_CLEAR_MASK    0x8
#define    RTL8370_PKTGEN_PORT4_CTRL_CMD_CONTINUE_OFFSET    2
#define    RTL8370_PKTGEN_PORT4_CTRL_CMD_CONTINUE_MASK    0x4
#define    RTL8370_PKTGEN_PORT4_CTRL_CMD_PAUSE_OFFSET    1
#define    RTL8370_PKTGEN_PORT4_CTRL_CMD_PAUSE_MASK    0x2
#define    RTL8370_PKTGEN_PORT4_CTRL_CMD_START_OFFSET    0
#define    RTL8370_PKTGEN_PORT4_CTRL_CMD_START_MASK    0x1

#define    RTL8370_REG_P4_DUMMY5    0x0082

#define    RTL8370_REG_PKTGEN_PORT4_DA0    0x0083

#define    RTL8370_REG_PKTGEN_PORT4_DA1    0x0084

#define    RTL8370_REG_PKTGEN_PORT4_DA2    0x0085

#define    RTL8370_REG_PKTGEN_PORT4_SA0    0x0086

#define    RTL8370_REG_PKTGEN_PORT4_SA1    0x0087

#define    RTL8370_REG_PKTGEN_PORT4_SA2    0x0088

#define    RTL8370_REG_PKTGEN_PORT4_COUNTER0    0x0089

#define    RTL8370_REG_PKTGEN_PORT4_COUNTER1    0x008a
#define    RTL8370_PKTGEN_PORT4_COUNTER1_OFFSET    0
#define    RTL8370_PKTGEN_PORT4_COUNTER1_MASK    0xFF

#define    RTL8370_REG_PKTGEN_PORT4_TX_LENGTH    0x008b
#define    RTL8370_PKTGEN_PORT4_TX_LENGTH_OFFSET    0
#define    RTL8370_PKTGEN_PORT4_TX_LENGTH_MASK    0x3FFF

#define    RTL8370_REG_PKTGEN_PORT4_MAX_LENGTH    0x008c
#define    RTL8370_PKTGEN_PORT4_MAX_LENGTH_OFFSET    0
#define    RTL8370_PKTGEN_PORT4_MAX_LENGTH_MASK    0x3FFF

#define    RTL8370_REG_P4_DUMMY6    0x008d

#define    RTL8370_REG_PORT4_MISC_CFG    0x008e
#define    RTL8370_PORT4_MISC_CFG_TIMER_OFFSET    12
#define    RTL8370_PORT4_MISC_CFG_TIMER_MASK    0xF000
#define    RTL8370_INGRESSBW_PORT4_FLOWCRTL_OFFSET    11
#define    RTL8370_INGRESSBW_PORT4_FLOWCRTL_MASK    0x800
#define    RTL8370_INGRESSBW_PORT4_IFG_OFFSET    10
#define    RTL8370_INGRESSBW_PORT4_IFG_MASK    0x400
#define    RTL8370_PORT4_MISC_CFG_RX_SPC_OFFSET    9
#define    RTL8370_PORT4_MISC_CFG_RX_SPC_MASK    0x200
#define    RTL8370_PORT4_MISC_CFG_CRC_SKIP_OFFSET    8
#define    RTL8370_PORT4_MISC_CFG_CRC_SKIP_MASK    0x100
#define    RTL8370_PORT4_MISC_CFG_MAC_LOOPBACK_OFFSET    6
#define    RTL8370_PORT4_MISC_CFG_MAC_LOOPBACK_MASK    0x40
#define    RTL8370_VLAN_PORT4_EGRESS_MODE_OFFSET    4
#define    RTL8370_VLAN_PORT4_EGRESS_MODE_MASK    0x30
#define    RTL8370_CONGESTION_PORT4_SUSTAIN_TIME_OFFSET    0
#define    RTL8370_CONGESTION_PORT4_SUSTAIN_TIME_MASK    0xF

#define    RTL8370_REG_INGRESSBW_PORT4_RATE_CRTL0    0x008f

#define    RTL8370_REG_INGRESSBW_PORT4_RATE_CRTL1    0x0090
#define    RTL8370_INGRESSBW_PORT4_RATE_CRTL1_DUMMY_OFFSET    1
#define    RTL8370_INGRESSBW_PORT4_RATE_CRTL1_DUMMY_MASK    0xFFFE
#define    RTL8370_INGRESSBW_PORT4_RATE16_OFFSET    0
#define    RTL8370_INGRESSBW_PORT4_RATE16_MASK    0x1

#define    RTL8370_REG_PORT4_FORCE_RATE0    0x0091

#define    RTL8370_REG_PORT4_FORCE_RATE1    0x0092

#define    RTL8370_REG_PORT4_CURENT_RATE0    0x0093

#define    RTL8370_REG_PORT4_CURENT_RATE1    0x0094

#define    RTL8370_REG_PORT4_PAGE_COUNTER    0x0095
#define    RTL8370_PORT4_PAGE_COUNTER_OFFSET    0
#define    RTL8370_PORT4_PAGE_COUNTER_MASK    0x7F

#define    RTL8370_REG_PAGEMETER_PORT4_CTRL0    0x0096

#define    RTL8370_REG_PAGEMETER_PORT4_CTRL1    0x0097
#define    RTL8370_PAGEMETER_PORT4_CTRL1_OFFSET    0
#define    RTL8370_PAGEMETER_PORT4_CTRL1_MASK    0x3F

#define    RTL8370_REG_PORT4_EEECFG    0x0098
#define    RTL8370_PORT4_EEECFG_EEEP_ENABLE_TX_OFFSET    14
#define    RTL8370_PORT4_EEECFG_EEEP_ENABLE_TX_MASK    0x4000
#define    RTL8370_PORT4_EEECFG_EEEP_ENABLE_RX_OFFSET    13
#define    RTL8370_PORT4_EEECFG_EEEP_ENABLE_RX_MASK    0x2000
#define    RTL8370_PORT4_EEECFG_EEE_FORCE_OFFSET    12
#define    RTL8370_PORT4_EEECFG_EEE_FORCE_MASK    0x1000
#define    RTL8370_PORT4_EEECFG_EEE_100M_OFFSET    11
#define    RTL8370_PORT4_EEECFG_EEE_100M_MASK    0x800
#define    RTL8370_PORT4_EEECFG_EEE_GIGA_OFFSET    10
#define    RTL8370_PORT4_EEECFG_EEE_GIGA_MASK    0x400
#define    RTL8370_PORT4_EEECFG_EEE_TX_OFFSET    9
#define    RTL8370_PORT4_EEECFG_EEE_TX_MASK    0x200
#define    RTL8370_PORT4_EEECFG_EEE_RX_OFFSET    8
#define    RTL8370_PORT4_EEECFG_EEE_RX_MASK    0x100
#define    RTL8370_PORT4_EEECFG_EEE_LPI_OFFSET    5
#define    RTL8370_PORT4_EEECFG_EEE_LPI_MASK    0x20
#define    RTL8370_PORT4_EEECFG_EEE_TX_LPI_OFFSET    4
#define    RTL8370_PORT4_EEECFG_EEE_TX_LPI_MASK    0x10
#define    RTL8370_PORT4_EEECFG_EEE_RX_LPI_OFFSET    3
#define    RTL8370_PORT4_EEECFG_EEE_RX_LPI_MASK    0x8
#define    RTL8370_PORT4_EEECFG_EEE_PAUSE_INDICATOR_OFFSET    2
#define    RTL8370_PORT4_EEECFG_EEE_PAUSE_INDICATOR_MASK    0x4
#define    RTL8370_PORT4_EEECFG_EEE_WAKE_REQ_OFFSET    1
#define    RTL8370_PORT4_EEECFG_EEE_WAKE_REQ_MASK    0x2
#define    RTL8370_PORT4_EEECFG_EEE_SLEEP_REQ_OFFSET    0
#define    RTL8370_PORT4_EEECFG_EEE_SLEEP_REQ_MASK    0x1

#define    RTL8370_REG_P4EEETXMTR    0x0099

#define    RTL8370_REG_P4EEERXMTR    0x009a

#define    RTL8370_REG_P4EEEPTXMTR    0x009b

#define    RTL8370_REG_P4EEEPRXMTR    0x009c

#define    RTL8370_REG_P4_DUMMY2    0x009d

#define    RTL8370_REG_P4_DUMMY3    0x009e

#define    RTL8370_REG_P4_DUMMY4    0x009f

#define    RTL8370_REG_PKTGEN_PORT5_CTRL    0x00a1
#define    RTL8370_PKTGEN_PORT5_CTRL_STATUS_OFFSET    15
#define    RTL8370_PKTGEN_PORT5_CTRL_STATUS_MASK    0x8000
#define    RTL8370_PKTGEN_PORT5_CTRL_ENABLED_OFFSET    9
#define    RTL8370_PKTGEN_PORT5_CTRL_ENABLED_MASK    0x200
#define    RTL8370_PKTGEN_PORT5_CTRL_INC_BC_OFFSET    8
#define    RTL8370_PKTGEN_PORT5_CTRL_INC_BC_MASK    0x100
#define    RTL8370_PKTGEN_PORT5_CTRL_INC_SA_OFFSET    7
#define    RTL8370_PKTGEN_PORT5_CTRL_INC_SA_MASK    0x80
#define    RTL8370_PKTGEN_PORT5_CTRL_INC_DA_OFFSET    6
#define    RTL8370_PKTGEN_PORT5_CTRL_INC_DA_MASK    0x40
#define    RTL8370_PKTGEN_PORT5_CTRL_RANDOM_OFFSET    5
#define    RTL8370_PKTGEN_PORT5_CTRL_RANDOM_MASK    0x20
#define    RTL8370_PKTGEN_PORT5_CTRL_CRC_NO_ERROR_OFFSET    4
#define    RTL8370_PKTGEN_PORT5_CTRL_CRC_NO_ERROR_MASK    0x10
#define    RTL8370_PKTGEN_PORT5_CTRL_CMD_CLEAR_OFFSET    3
#define    RTL8370_PKTGEN_PORT5_CTRL_CMD_CLEAR_MASK    0x8
#define    RTL8370_PKTGEN_PORT5_CTRL_CMD_CONTINUE_OFFSET    2
#define    RTL8370_PKTGEN_PORT5_CTRL_CMD_CONTINUE_MASK    0x4
#define    RTL8370_PKTGEN_PORT5_CTRL_CMD_PAUSE_OFFSET    1
#define    RTL8370_PKTGEN_PORT5_CTRL_CMD_PAUSE_MASK    0x2
#define    RTL8370_PKTGEN_PORT5_CTRL_CMD_START_OFFSET    0
#define    RTL8370_PKTGEN_PORT5_CTRL_CMD_START_MASK    0x1

#define    RTL8370_REG_P5_DUMMY5    0x00a2

#define    RTL8370_REG_PKTGEN_PORT5_DA0    0x00a3

#define    RTL8370_REG_PKTGEN_PORT5_DA1    0x00a4

#define    RTL8370_REG_PKTGEN_PORT5_DA2    0x00a5

#define    RTL8370_REG_PKTGEN_PORT5_SA0    0x00a6

#define    RTL8370_REG_PKTGEN_PORT5_SA1    0x00a7

#define    RTL8370_REG_PKTGEN_PORT5_SA2    0x00a8

#define    RTL8370_REG_PKTGEN_PORT5_COUNTER0    0x00a9

#define    RTL8370_REG_PKTGEN_PORT5_COUNTER1    0x00aa
#define    RTL8370_PKTGEN_PORT5_COUNTER1_OFFSET    0
#define    RTL8370_PKTGEN_PORT5_COUNTER1_MASK    0xFF

#define    RTL8370_REG_PKTGEN_PORT5_TX_LENGTH    0x00ab
#define    RTL8370_PKTGEN_PORT5_TX_LENGTH_OFFSET    0
#define    RTL8370_PKTGEN_PORT5_TX_LENGTH_MASK    0x3FFF

#define    RTL8370_REG_PKTGEN_PORT5_MAX_LENGTH    0x00ac
#define    RTL8370_PKTGEN_PORT5_MAX_LENGTH_OFFSET    0
#define    RTL8370_PKTGEN_PORT5_MAX_LENGTH_MASK    0x3FFF

#define    RTL8370_REG_P5_DUMMY6    0x00ad

#define    RTL8370_REG_PORT5_MISC_CFG    0x00ae
#define    RTL8370_PORT5_MISC_CFG_TIMER_OFFSET    12
#define    RTL8370_PORT5_MISC_CFG_TIMER_MASK    0xF000
#define    RTL8370_INGRESSBW_PORT5_FLOWCRTL_OFFSET    11
#define    RTL8370_INGRESSBW_PORT5_FLOWCRTL_MASK    0x800
#define    RTL8370_INGRESSBW_PORT5_IFG_OFFSET    10
#define    RTL8370_INGRESSBW_PORT5_IFG_MASK    0x400
#define    RTL8370_PORT5_MISC_CFG_RX_SPC_OFFSET    9
#define    RTL8370_PORT5_MISC_CFG_RX_SPC_MASK    0x200
#define    RTL8370_PORT5_MISC_CFG_CRC_SKIP_OFFSET    8
#define    RTL8370_PORT5_MISC_CFG_CRC_SKIP_MASK    0x100
#define    RTL8370_PORT5_MISC_CFG_MAC_LOOPBACK_OFFSET    6
#define    RTL8370_PORT5_MISC_CFG_MAC_LOOPBACK_MASK    0x40
#define    RTL8370_VLAN_PORT5_EGRESS_MODE_OFFSET    4
#define    RTL8370_VLAN_PORT5_EGRESS_MODE_MASK    0x30
#define    RTL8370_CONGESTION_PORT5_SUSTAIN_TIME_OFFSET    0
#define    RTL8370_CONGESTION_PORT5_SUSTAIN_TIME_MASK    0xF

#define    RTL8370_REG_INGRESSBW_PORT5_RATE_CRTL0    0x00af

#define    RTL8370_REG_INGRESSBW_PORT5_RATE_CRTL1    0x00b0
#define    RTL8370_INGRESSBW_PORT5_RATE_CRTL1_DUMMY_OFFSET    1
#define    RTL8370_INGRESSBW_PORT5_RATE_CRTL1_DUMMY_MASK    0xFFFE
#define    RTL8370_INGRESSBW_PORT5_RATE16_OFFSET    0
#define    RTL8370_INGRESSBW_PORT5_RATE16_MASK    0x1

#define    RTL8370_REG_PORT5_FORCE_RATE0    0x00b1

#define    RTL8370_REG_PORT5_FORCE_RATE1    0x00b2

#define    RTL8370_REG_PORT5_CURENT_RATE0    0x00b3

#define    RTL8370_REG_PORT5_CURENT_RATE1    0x00b4

#define    RTL8370_REG_PORT5_PAGE_COUNTER    0x00b5
#define    RTL8370_PORT5_PAGE_COUNTER_OFFSET    0
#define    RTL8370_PORT5_PAGE_COUNTER_MASK    0x7F

#define    RTL8370_REG_PAGEMETER_PORT5_CTRL0    0x00b6

#define    RTL8370_REG_PAGEMETER_PORT5_CTRL1    0x00b7
#define    RTL8370_PAGEMETER_PORT5_CTRL1_OFFSET    0
#define    RTL8370_PAGEMETER_PORT5_CTRL1_MASK    0x3F

#define    RTL8370_REG_PORT5_EEECFG    0x00b8
#define    RTL8370_PORT5_EEECFG_EEEP_ENABLE_TX_OFFSET    14
#define    RTL8370_PORT5_EEECFG_EEEP_ENABLE_TX_MASK    0x4000
#define    RTL8370_PORT5_EEECFG_EEEP_ENABLE_RX_OFFSET    13
#define    RTL8370_PORT5_EEECFG_EEEP_ENABLE_RX_MASK    0x2000
#define    RTL8370_PORT5_EEECFG_EEE_FORCE_OFFSET    12
#define    RTL8370_PORT5_EEECFG_EEE_FORCE_MASK    0x1000
#define    RTL8370_PORT5_EEECFG_EEE_100M_OFFSET    11
#define    RTL8370_PORT5_EEECFG_EEE_100M_MASK    0x800
#define    RTL8370_PORT5_EEECFG_EEE_GIGA_OFFSET    10
#define    RTL8370_PORT5_EEECFG_EEE_GIGA_MASK    0x400
#define    RTL8370_PORT5_EEECFG_EEE_TX_OFFSET    9
#define    RTL8370_PORT5_EEECFG_EEE_TX_MASK    0x200
#define    RTL8370_PORT5_EEECFG_EEE_RX_OFFSET    8
#define    RTL8370_PORT5_EEECFG_EEE_RX_MASK    0x100
#define    RTL8370_PORT5_EEECFG_EEE_LPI_OFFSET    5
#define    RTL8370_PORT5_EEECFG_EEE_LPI_MASK    0x20
#define    RTL8370_PORT5_EEECFG_EEE_TX_LPI_OFFSET    4
#define    RTL8370_PORT5_EEECFG_EEE_TX_LPI_MASK    0x10
#define    RTL8370_PORT5_EEECFG_EEE_RX_LPI_OFFSET    3
#define    RTL8370_PORT5_EEECFG_EEE_RX_LPI_MASK    0x8
#define    RTL8370_PORT5_EEECFG_EEE_PAUSE_INDICATOR_OFFSET    2
#define    RTL8370_PORT5_EEECFG_EEE_PAUSE_INDICATOR_MASK    0x4
#define    RTL8370_PORT5_EEECFG_EEE_WAKE_REQ_OFFSET    1
#define    RTL8370_PORT5_EEECFG_EEE_WAKE_REQ_MASK    0x2
#define    RTL8370_PORT5_EEECFG_EEE_SLEEP_REQ_OFFSET    0
#define    RTL8370_PORT5_EEECFG_EEE_SLEEP_REQ_MASK    0x1

#define    RTL8370_REG_P5EEETXMTR    0x00b9

#define    RTL8370_REG_P5EEERXMTR    0x00ba

#define    RTL8370_REG_P5EEEPTXMTR    0x00bb

#define    RTL8370_REG_P5EEEPRXMTR    0x00bc

#define    RTL8370_REG_P5_DUMMY2    0x00bd

#define    RTL8370_REG_P5_DUMMY3    0x00be

#define    RTL8370_REG_P5_DUMMY4    0x00bf

#define    RTL8370_REG_PKTGEN_PORT6_CTRL    0x00c1
#define    RTL8370_PKTGEN_PORT6_CTRL_STATUS_OFFSET    15
#define    RTL8370_PKTGEN_PORT6_CTRL_STATUS_MASK    0x8000
#define    RTL8370_PKTGEN_PORT6_CTRL_ENABLED_OFFSET    9
#define    RTL8370_PKTGEN_PORT6_CTRL_ENABLED_MASK    0x200
#define    RTL8370_PKTGEN_PORT6_CTRL_INC_BC_OFFSET    8
#define    RTL8370_PKTGEN_PORT6_CTRL_INC_BC_MASK    0x100
#define    RTL8370_PKTGEN_PORT6_CTRL_INC_SA_OFFSET    7
#define    RTL8370_PKTGEN_PORT6_CTRL_INC_SA_MASK    0x80
#define    RTL8370_PKTGEN_PORT6_CTRL_INC_DA_OFFSET    6
#define    RTL8370_PKTGEN_PORT6_CTRL_INC_DA_MASK    0x40
#define    RTL8370_PKTGEN_PORT6_CTRL_RANDOM_OFFSET    5
#define    RTL8370_PKTGEN_PORT6_CTRL_RANDOM_MASK    0x20
#define    RTL8370_PKTGEN_PORT6_CTRL_CRC_NO_ERROR_OFFSET    4
#define    RTL8370_PKTGEN_PORT6_CTRL_CRC_NO_ERROR_MASK    0x10
#define    RTL8370_PKTGEN_PORT6_CTRL_CMD_CLEAR_OFFSET    3
#define    RTL8370_PKTGEN_PORT6_CTRL_CMD_CLEAR_MASK    0x8
#define    RTL8370_PKTGEN_PORT6_CTRL_CMD_CONTINUE_OFFSET    2
#define    RTL8370_PKTGEN_PORT6_CTRL_CMD_CONTINUE_MASK    0x4
#define    RTL8370_PKTGEN_PORT6_CTRL_CMD_PAUSE_OFFSET    1
#define    RTL8370_PKTGEN_PORT6_CTRL_CMD_PAUSE_MASK    0x2
#define    RTL8370_PKTGEN_PORT6_CTRL_CMD_START_OFFSET    0
#define    RTL8370_PKTGEN_PORT6_CTRL_CMD_START_MASK    0x1

#define    RTL8370_REG_P6_DUMMY5    0x00c2

#define    RTL8370_REG_PKTGEN_PORT6_DA0    0x00c3

#define    RTL8370_REG_PKTGEN_PORT6_DA1    0x00c4

#define    RTL8370_REG_PKTGEN_PORT6_DA2    0x00c5

#define    RTL8370_REG_PKTGEN_PORT6_SA0    0x00c6

#define    RTL8370_REG_PKTGEN_PORT6_SA1    0x00c7

#define    RTL8370_REG_PKTGEN_PORT6_SA2    0x00c8

#define    RTL8370_REG_PKTGEN_PORT6_COUNTER0    0x00c9

#define    RTL8370_REG_PKTGEN_PORT6_COUNTER1    0x00ca
#define    RTL8370_PKTGEN_PORT6_COUNTER1_OFFSET    0
#define    RTL8370_PKTGEN_PORT6_COUNTER1_MASK    0xFF

#define    RTL8370_REG_PKTGEN_PORT6_TX_LENGTH    0x00cb
#define    RTL8370_PKTGEN_PORT6_TX_LENGTH_OFFSET    0
#define    RTL8370_PKTGEN_PORT6_TX_LENGTH_MASK    0x3FFF

#define    RTL8370_REG_PKTGEN_PORT6_MAX_LENGTH    0x00cc
#define    RTL8370_PKTGEN_PORT6_MAX_LENGTH_OFFSET    0
#define    RTL8370_PKTGEN_PORT6_MAX_LENGTH_MASK    0x3FFF

#define    RTL8370_REG_P6_DUMMY6    0x00cd

#define    RTL8370_REG_PORT6_MISC_CFG    0x00ce
#define    RTL8370_PORT6_MISC_CFG_TIMER_OFFSET    12
#define    RTL8370_PORT6_MISC_CFG_TIMER_MASK    0xF000
#define    RTL8370_INGRESSBW_PORT6_FLOWCRTL_OFFSET    11
#define    RTL8370_INGRESSBW_PORT6_FLOWCRTL_MASK    0x800
#define    RTL8370_INGRESSBW_PORT6_IFG_OFFSET    10
#define    RTL8370_INGRESSBW_PORT6_IFG_MASK    0x400
#define    RTL8370_PORT6_MISC_CFG_RX_SPC_OFFSET    9
#define    RTL8370_PORT6_MISC_CFG_RX_SPC_MASK    0x200
#define    RTL8370_PORT6_MISC_CFG_CRC_SKIP_OFFSET    8
#define    RTL8370_PORT6_MISC_CFG_CRC_SKIP_MASK    0x100
#define    RTL8370_PORT6_MISC_CFG_MAC_LOOPBACK_OFFSET    6
#define    RTL8370_PORT6_MISC_CFG_MAC_LOOPBACK_MASK    0x40
#define    RTL8370_VLAN_PORT6_EGRESS_MODE_OFFSET    4
#define    RTL8370_VLAN_PORT6_EGRESS_MODE_MASK    0x30
#define    RTL8370_CONGESTION_PORT6_SUSTAIN_TIME_OFFSET    0
#define    RTL8370_CONGESTION_PORT6_SUSTAIN_TIME_MASK    0xF

#define    RTL8370_REG_INGRESSBW_PORT6_RATE_CRTL0    0x00cf

#define    RTL8370_REG_INGRESSBW_PORT6_RATE_CRTL1    0x00d0
#define    RTL8370_INGRESSBW_PORT6_RATE_CRTL1_DUMMY_OFFSET    1
#define    RTL8370_INGRESSBW_PORT6_RATE_CRTL1_DUMMY_MASK    0xFFFE
#define    RTL8370_INGRESSBW_PORT6_RATE16_OFFSET    0
#define    RTL8370_INGRESSBW_PORT6_RATE16_MASK    0x1

#define    RTL8370_REG_PORT6_FORCE_RATE0    0x00d1

#define    RTL8370_REG_PORT6_FORCE_RATE1    0x00d2

#define    RTL8370_REG_PORT6_CURENT_RATE0    0x00d3

#define    RTL8370_REG_PORT6_CURENT_RATE1    0x00d4

#define    RTL8370_REG_PORT6_PAGE_COUNTER    0x00d5
#define    RTL8370_PORT6_PAGE_COUNTER_OFFSET    0
#define    RTL8370_PORT6_PAGE_COUNTER_MASK    0x7F

#define    RTL8370_REG_PAGEMETER_PORT6_CTRL0    0x00d6

#define    RTL8370_REG_PAGEMETER_PORT6_CTRL1    0x00d7
#define    RTL8370_PAGEMETER_PORT6_CTRL1_OFFSET    0
#define    RTL8370_PAGEMETER_PORT6_CTRL1_MASK    0x3F

#define    RTL8370_REG_PORT6_EEECFG    0x00d8
#define    RTL8370_PORT6_EEECFG_EEEP_ENABLE_TX_OFFSET    14
#define    RTL8370_PORT6_EEECFG_EEEP_ENABLE_TX_MASK    0x4000
#define    RTL8370_PORT6_EEECFG_EEEP_ENABLE_RX_OFFSET    13
#define    RTL8370_PORT6_EEECFG_EEEP_ENABLE_RX_MASK    0x2000
#define    RTL8370_PORT6_EEECFG_EEE_FORCE_OFFSET    12
#define    RTL8370_PORT6_EEECFG_EEE_FORCE_MASK    0x1000
#define    RTL8370_PORT6_EEECFG_EEE_100M_OFFSET    11
#define    RTL8370_PORT6_EEECFG_EEE_100M_MASK    0x800
#define    RTL8370_PORT6_EEECFG_EEE_GIGA_OFFSET    10
#define    RTL8370_PORT6_EEECFG_EEE_GIGA_MASK    0x400
#define    RTL8370_PORT6_EEECFG_EEE_TX_OFFSET    9
#define    RTL8370_PORT6_EEECFG_EEE_TX_MASK    0x200
#define    RTL8370_PORT6_EEECFG_EEE_RX_OFFSET    8
#define    RTL8370_PORT6_EEECFG_EEE_RX_MASK    0x100
#define    RTL8370_PORT6_EEECFG_EEE_LPI_OFFSET    5
#define    RTL8370_PORT6_EEECFG_EEE_LPI_MASK    0x20
#define    RTL8370_PORT6_EEECFG_EEE_TX_LPI_OFFSET    4
#define    RTL8370_PORT6_EEECFG_EEE_TX_LPI_MASK    0x10
#define    RTL8370_PORT6_EEECFG_EEE_RX_LPI_OFFSET    3
#define    RTL8370_PORT6_EEECFG_EEE_RX_LPI_MASK    0x8
#define    RTL8370_PORT6_EEECFG_EEE_PAUSE_INDICATOR_OFFSET    2
#define    RTL8370_PORT6_EEECFG_EEE_PAUSE_INDICATOR_MASK    0x4
#define    RTL8370_PORT6_EEECFG_EEE_WAKE_REQ_OFFSET    1
#define    RTL8370_PORT6_EEECFG_EEE_WAKE_REQ_MASK    0x2
#define    RTL8370_PORT6_EEECFG_EEE_SLEEP_REQ_OFFSET    0
#define    RTL8370_PORT6_EEECFG_EEE_SLEEP_REQ_MASK    0x1

#define    RTL8370_REG_P6EEETXMTR    0x00d9

#define    RTL8370_REG_P6EEERXMTR    0x00da

#define    RTL8370_REG_P6EEEPTXMTR    0x00db

#define    RTL8370_REG_P6EEEPRXMTR    0x00dc

#define    RTL8370_REG_P6_DUMMY2    0x00dd

#define    RTL8370_REG_P6_DUMMY3    0x00de

#define    RTL8370_REG_P6_DUMMY4    0x00df

#define    RTL8370_REG_PKTGEN_PORT7_CTRL    0x00e1
#define    RTL8370_PKTGEN_PORT7_CTRL_STATUS_OFFSET    15
#define    RTL8370_PKTGEN_PORT7_CTRL_STATUS_MASK    0x8000
#define    RTL8370_PKTGEN_PORT7_CTRL_ENABLED_OFFSET    9
#define    RTL8370_PKTGEN_PORT7_CTRL_ENABLED_MASK    0x200
#define    RTL8370_PKTGEN_PORT7_CTRL_INC_BC_OFFSET    8
#define    RTL8370_PKTGEN_PORT7_CTRL_INC_BC_MASK    0x100
#define    RTL8370_PKTGEN_PORT7_CTRL_INC_SA_OFFSET    7
#define    RTL8370_PKTGEN_PORT7_CTRL_INC_SA_MASK    0x80
#define    RTL8370_PKTGEN_PORT7_CTRL_INC_DA_OFFSET    6
#define    RTL8370_PKTGEN_PORT7_CTRL_INC_DA_MASK    0x40
#define    RTL8370_PKTGEN_PORT7_CTRL_RANDOM_OFFSET    5
#define    RTL8370_PKTGEN_PORT7_CTRL_RANDOM_MASK    0x20
#define    RTL8370_PKTGEN_PORT7_CTRL_CRC_NO_ERROR_OFFSET    4
#define    RTL8370_PKTGEN_PORT7_CTRL_CRC_NO_ERROR_MASK    0x10
#define    RTL8370_PKTGEN_PORT7_CTRL_CMD_CLEAR_OFFSET    3
#define    RTL8370_PKTGEN_PORT7_CTRL_CMD_CLEAR_MASK    0x8
#define    RTL8370_PKTGEN_PORT7_CTRL_CMD_CONTINUE_OFFSET    2
#define    RTL8370_PKTGEN_PORT7_CTRL_CMD_CONTINUE_MASK    0x4
#define    RTL8370_PKTGEN_PORT7_CTRL_CMD_PAUSE_OFFSET    1
#define    RTL8370_PKTGEN_PORT7_CTRL_CMD_PAUSE_MASK    0x2
#define    RTL8370_PKTGEN_PORT7_CTRL_CMD_START_OFFSET    0
#define    RTL8370_PKTGEN_PORT7_CTRL_CMD_START_MASK    0x1

#define    RTL8370_REG_P7_DUMMY5    0x00e2

#define    RTL8370_REG_PKTGEN_PORT7_DA0    0x00e3

#define    RTL8370_REG_PKTGEN_PORT7_DA1    0x00e4

#define    RTL8370_REG_PKTGEN_PORT7_DA2    0x00e5

#define    RTL8370_REG_PKTGEN_PORT7_SA0    0x00e6

#define    RTL8370_REG_PKTGEN_PORT7_SA1    0x00e7

#define    RTL8370_REG_PKTGEN_PORT7_SA2    0x00e8

#define    RTL8370_REG_PKTGEN_PORT7_COUNTER0    0x00e9

#define    RTL8370_REG_PKTGEN_PORT7_COUNTER1    0x00ea
#define    RTL8370_PKTGEN_PORT7_COUNTER1_OFFSET    0
#define    RTL8370_PKTGEN_PORT7_COUNTER1_MASK    0xFF

#define    RTL8370_REG_PKTGEN_PORT7_TX_LENGTH    0x00eb
#define    RTL8370_PKTGEN_PORT7_TX_LENGTH_OFFSET    0
#define    RTL8370_PKTGEN_PORT7_TX_LENGTH_MASK    0x3FFF

#define    RTL8370_REG_PKTGEN_PORT7_MAX_LENGTH    0x00ec
#define    RTL8370_PKTGEN_PORT7_MAX_LENGTH_OFFSET    0
#define    RTL8370_PKTGEN_PORT7_MAX_LENGTH_MASK    0x3FFF

#define    RTL8370_REG_P7_DUMMY6    0x00ed

#define    RTL8370_REG_PORT7_MISC_CFG    0x00ee
#define    RTL8370_PORT7_MISC_CFG_TIMER_OFFSET    12
#define    RTL8370_PORT7_MISC_CFG_TIMER_MASK    0xF000
#define    RTL8370_INGRESSBW_PORT7_FLOWCRTL_OFFSET    11
#define    RTL8370_INGRESSBW_PORT7_FLOWCRTL_MASK    0x800
#define    RTL8370_INGRESSBW_PORT7_IFG_OFFSET    10
#define    RTL8370_INGRESSBW_PORT7_IFG_MASK    0x400
#define    RTL8370_PORT7_MISC_CFG_RX_SPC_OFFSET    9
#define    RTL8370_PORT7_MISC_CFG_RX_SPC_MASK    0x200
#define    RTL8370_PORT7_MISC_CFG_CRC_SKIP_OFFSET    8
#define    RTL8370_PORT7_MISC_CFG_CRC_SKIP_MASK    0x100
#define    RTL8370_PORT7_MISC_CFG_MAC_LOOPBACK_OFFSET    6
#define    RTL8370_PORT7_MISC_CFG_MAC_LOOPBACK_MASK    0x40
#define    RTL8370_VLAN_PORT7_EGRESS_MODE_OFFSET    4
#define    RTL8370_VLAN_PORT7_EGRESS_MODE_MASK    0x30
#define    RTL8370_CONGESTION_PORT7_SUSTAIN_TIME_OFFSET    0
#define    RTL8370_CONGESTION_PORT7_SUSTAIN_TIME_MASK    0xF

#define    RTL8370_REG_INGRESSBW_PORT7_RATE_CRTL0    0x00ef

#define    RTL8370_REG_INGRESSBW_PORT7_RATE_CRTL1    0x00f0
#define    RTL8370_INGRESSBW_PORT7_RATE_CRTL1_DUMMY_OFFSET    1
#define    RTL8370_INGRESSBW_PORT7_RATE_CRTL1_DUMMY_MASK    0xFFFE
#define    RTL8370_INGRESSBW_PORT7_RATE16_OFFSET    0
#define    RTL8370_INGRESSBW_PORT7_RATE16_MASK    0x1

#define    RTL8370_REG_PORT7_FORCE_RATE0    0x00f1

#define    RTL8370_REG_PORT7_FORCE_RATE1    0x00f2

#define    RTL8370_REG_PORT7_CURENT_RATE0    0x00f3

#define    RTL8370_REG_PORT7_CURENT_RATE1    0x00f4

#define    RTL8370_REG_PORT7_PAGE_COUNTER    0x00f5
#define    RTL8370_PORT7_PAGE_COUNTER_OFFSET    0
#define    RTL8370_PORT7_PAGE_COUNTER_MASK    0x7F

#define    RTL8370_REG_PAGEMETER_PORT7_CTRL0    0x00f6

#define    RTL8370_REG_PAGEMETER_PORT7_CTRL1    0x00f7
#define    RTL8370_PAGEMETER_PORT7_CTRL1_OFFSET    0
#define    RTL8370_PAGEMETER_PORT7_CTRL1_MASK    0x3F

#define    RTL8370_REG_PORT7_EEECFG    0x00f8
#define    RTL8370_PORT7_EEECFG_EEEP_ENABLE_TX_OFFSET    14
#define    RTL8370_PORT7_EEECFG_EEEP_ENABLE_TX_MASK    0x4000
#define    RTL8370_PORT7_EEECFG_EEEP_ENABLE_RX_OFFSET    13
#define    RTL8370_PORT7_EEECFG_EEEP_ENABLE_RX_MASK    0x2000
#define    RTL8370_PORT7_EEECFG_EEE_FORCE_OFFSET    12
#define    RTL8370_PORT7_EEECFG_EEE_FORCE_MASK    0x1000
#define    RTL8370_PORT7_EEECFG_EEE_100M_OFFSET    11
#define    RTL8370_PORT7_EEECFG_EEE_100M_MASK    0x800
#define    RTL8370_PORT7_EEECFG_EEE_GIGA_OFFSET    10
#define    RTL8370_PORT7_EEECFG_EEE_GIGA_MASK    0x400
#define    RTL8370_PORT7_EEECFG_EEE_TX_OFFSET    9
#define    RTL8370_PORT7_EEECFG_EEE_TX_MASK    0x200
#define    RTL8370_PORT7_EEECFG_EEE_RX_OFFSET    8
#define    RTL8370_PORT7_EEECFG_EEE_RX_MASK    0x100
#define    RTL8370_PORT7_EEECFG_EEE_LPI_OFFSET    5
#define    RTL8370_PORT7_EEECFG_EEE_LPI_MASK    0x20
#define    RTL8370_PORT7_EEECFG_EEE_TX_LPI_OFFSET    4
#define    RTL8370_PORT7_EEECFG_EEE_TX_LPI_MASK    0x10
#define    RTL8370_PORT7_EEECFG_EEE_RX_LPI_OFFSET    3
#define    RTL8370_PORT7_EEECFG_EEE_RX_LPI_MASK    0x8
#define    RTL8370_PORT7_EEECFG_EEE_PAUSE_INDICATOR_OFFSET    2
#define    RTL8370_PORT7_EEECFG_EEE_PAUSE_INDICATOR_MASK    0x4
#define    RTL8370_PORT7_EEECFG_EEE_WAKE_REQ_OFFSET    1
#define    RTL8370_PORT7_EEECFG_EEE_WAKE_REQ_MASK    0x2
#define    RTL8370_PORT7_EEECFG_EEE_SLEEP_REQ_OFFSET    0
#define    RTL8370_PORT7_EEECFG_EEE_SLEEP_REQ_MASK    0x1

#define    RTL8370_REG_P7EEETXMTR    0x00f9

#define    RTL8370_REG_P7EEERXMTR    0x00fa

#define    RTL8370_REG_P7EEEPTXMTR    0x00fb

#define    RTL8370_REG_P7EEEPRXMTR    0x00fc

#define    RTL8370_REG_P7_DUMMY2    0x00fd

#define    RTL8370_REG_P7_DUMMY3    0x00fe

#define    RTL8370_REG_P7_DUMMY4    0x00ff

#define    RTL8370_REG_PKTGEN_PORT8_CTRL    0x0101
#define    RTL8370_PKTGEN_PORT8_CTRL_STATUS_OFFSET    15
#define    RTL8370_PKTGEN_PORT8_CTRL_STATUS_MASK    0x8000
#define    RTL8370_PKTGEN_PORT8_CTRL_ENABLED_OFFSET    9
#define    RTL8370_PKTGEN_PORT8_CTRL_ENABLED_MASK    0x200
#define    RTL8370_PKTGEN_PORT8_CTRL_INC_BC_OFFSET    8
#define    RTL8370_PKTGEN_PORT8_CTRL_INC_BC_MASK    0x100
#define    RTL8370_PKTGEN_PORT8_CTRL_INC_SA_OFFSET    7
#define    RTL8370_PKTGEN_PORT8_CTRL_INC_SA_MASK    0x80
#define    RTL8370_PKTGEN_PORT8_CTRL_INC_DA_OFFSET    6
#define    RTL8370_PKTGEN_PORT8_CTRL_INC_DA_MASK    0x40
#define    RTL8370_PKTGEN_PORT8_CTRL_RANDOM_OFFSET    5
#define    RTL8370_PKTGEN_PORT8_CTRL_RANDOM_MASK    0x20
#define    RTL8370_PKTGEN_PORT8_CTRL_CRC_NO_ERROR_OFFSET    4
#define    RTL8370_PKTGEN_PORT8_CTRL_CRC_NO_ERROR_MASK    0x10
#define    RTL8370_PKTGEN_PORT8_CTRL_CMD_CLEAR_OFFSET    3
#define    RTL8370_PKTGEN_PORT8_CTRL_CMD_CLEAR_MASK    0x8
#define    RTL8370_PKTGEN_PORT8_CTRL_CMD_CONTINUE_OFFSET    2
#define    RTL8370_PKTGEN_PORT8_CTRL_CMD_CONTINUE_MASK    0x4
#define    RTL8370_PKTGEN_PORT8_CTRL_CMD_PAUSE_OFFSET    1
#define    RTL8370_PKTGEN_PORT8_CTRL_CMD_PAUSE_MASK    0x2
#define    RTL8370_PKTGEN_PORT8_CTRL_CMD_START_OFFSET    0
#define    RTL8370_PKTGEN_PORT8_CTRL_CMD_START_MASK    0x1

#define    RTL8370_REG_P8_DUMMY5    0x0102

#define    RTL8370_REG_PKTGEN_PORT8_DA0    0x0103

#define    RTL8370_REG_PKTGEN_PORT8_DA1    0x0104

#define    RTL8370_REG_PKTGEN_PORT8_DA2    0x0105

#define    RTL8370_REG_PKTGEN_PORT8_SA0    0x0106

#define    RTL8370_REG_PKTGEN_PORT8_SA1    0x0107

#define    RTL8370_REG_PKTGEN_PORT8_SA2    0x0108

#define    RTL8370_REG_PKTGEN_PORT8_COUNTER0    0x0109

#define    RTL8370_REG_PKTGEN_PORT8_COUNTER1    0x010a
#define    RTL8370_PKTGEN_PORT8_COUNTER1_OFFSET    0
#define    RTL8370_PKTGEN_PORT8_COUNTER1_MASK    0xFF

#define    RTL8370_REG_PKTGEN_PORT8_TX_LENGTH    0x010b
#define    RTL8370_PKTGEN_PORT8_TX_LENGTH_OFFSET    0
#define    RTL8370_PKTGEN_PORT8_TX_LENGTH_MASK    0x3FFF

#define    RTL8370_REG_PKTGEN_PORT8_MAX_LENGTH    0x010c
#define    RTL8370_PKTGEN_PORT8_MAX_LENGTH_OFFSET    0
#define    RTL8370_PKTGEN_PORT8_MAX_LENGTH_MASK    0x3FFF

#define    RTL8370_REG_P8_DUMMY6    0x010d

#define    RTL8370_REG_PORT8_MISC_CFG    0x010e
#define    RTL8370_PORT8_MISC_CFG_TIMER_OFFSET    12
#define    RTL8370_PORT8_MISC_CFG_TIMER_MASK    0xF000
#define    RTL8370_INGRESSBW_PORT8_FLOWCRTL_OFFSET    11
#define    RTL8370_INGRESSBW_PORT8_FLOWCRTL_MASK    0x800
#define    RTL8370_INGRESSBW_PORT8_IFG_OFFSET    10
#define    RTL8370_INGRESSBW_PORT8_IFG_MASK    0x400
#define    RTL8370_PORT8_MISC_CFG_RX_SPC_OFFSET    9
#define    RTL8370_PORT8_MISC_CFG_RX_SPC_MASK    0x200
#define    RTL8370_PORT8_MISC_CFG_CRC_SKIP_OFFSET    8
#define    RTL8370_PORT8_MISC_CFG_CRC_SKIP_MASK    0x100
#define    RTL8370_PORT8_MISC_CFG_MAC_LOOPBACK_OFFSET    6
#define    RTL8370_PORT8_MISC_CFG_MAC_LOOPBACK_MASK    0x40
#define    RTL8370_VLAN_PORT8_EGRESS_MODE_OFFSET    4
#define    RTL8370_VLAN_PORT8_EGRESS_MODE_MASK    0x30
#define    RTL8370_CONGESTION_PORT8_SUSTAIN_TIME_OFFSET    0
#define    RTL8370_CONGESTION_PORT8_SUSTAIN_TIME_MASK    0xF

#define    RTL8370_REG_INGRESSBW_PORT8_RATE_CRTL0    0x010f

#define    RTL8370_REG_INGRESSBW_PORT8_RATE_CRTL1    0x0110
#define    RTL8370_INGRESSBW_PORT8_RATE_CRTL1_DUMMY_OFFSET    1
#define    RTL8370_INGRESSBW_PORT8_RATE_CRTL1_DUMMY_MASK    0xFFFE
#define    RTL8370_INGRESSBW_PORT8_RATE16_OFFSET    0
#define    RTL8370_INGRESSBW_PORT8_RATE16_MASK    0x1

#define    RTL8370_REG_PORT8_FORCE_RATE0    0x0111

#define    RTL8370_REG_PORT8_FORCE_RATE1    0x0112

#define    RTL8370_REG_PORT8_CURENT_RATE0    0x0113

#define    RTL8370_REG_PORT8_CURENT_RATE1    0x0114

#define    RTL8370_REG_PORT8_PAGE_COUNTER    0x0115
#define    RTL8370_PORT8_PAGE_COUNTER_OFFSET    0
#define    RTL8370_PORT8_PAGE_COUNTER_MASK    0x7F

#define    RTL8370_REG_PAGEMETER_PORT8_CTRL0    0x0116

#define    RTL8370_REG_PAGEMETER_PORT8_CTRL1    0x0117
#define    RTL8370_PAGEMETER_PORT8_CTRL1_OFFSET    0
#define    RTL8370_PAGEMETER_PORT8_CTRL1_MASK    0x3F

#define    RTL8370_REG_PORT8_EEECFG    0x0118
#define    RTL8370_PORT8_EEECFG_EEEP_ENABLE_TX_OFFSET    14
#define    RTL8370_PORT8_EEECFG_EEEP_ENABLE_TX_MASK    0x4000
#define    RTL8370_PORT8_EEECFG_EEEP_ENABLE_RX_OFFSET    13
#define    RTL8370_PORT8_EEECFG_EEEP_ENABLE_RX_MASK    0x2000
#define    RTL8370_PORT8_EEECFG_EEE_FORCE_OFFSET    12
#define    RTL8370_PORT8_EEECFG_EEE_FORCE_MASK    0x1000
#define    RTL8370_PORT8_EEECFG_EEE_100M_OFFSET    11
#define    RTL8370_PORT8_EEECFG_EEE_100M_MASK    0x800
#define    RTL8370_PORT8_EEECFG_EEE_GIGA_OFFSET    10
#define    RTL8370_PORT8_EEECFG_EEE_GIGA_MASK    0x400
#define    RTL8370_PORT8_EEECFG_EEE_TX_OFFSET    9
#define    RTL8370_PORT8_EEECFG_EEE_TX_MASK    0x200
#define    RTL8370_PORT8_EEECFG_EEE_RX_OFFSET    8
#define    RTL8370_PORT8_EEECFG_EEE_RX_MASK    0x100
#define    RTL8370_PORT8_EEECFG_EEE_LPI_OFFSET    5
#define    RTL8370_PORT8_EEECFG_EEE_LPI_MASK    0x20
#define    RTL8370_PORT8_EEECFG_EEE_TX_LPI_OFFSET    4
#define    RTL8370_PORT8_EEECFG_EEE_TX_LPI_MASK    0x10
#define    RTL8370_PORT8_EEECFG_EEE_RX_LPI_OFFSET    3
#define    RTL8370_PORT8_EEECFG_EEE_RX_LPI_MASK    0x8
#define    RTL8370_PORT8_EEECFG_EEE_PAUSE_INDICATOR_OFFSET    2
#define    RTL8370_PORT8_EEECFG_EEE_PAUSE_INDICATOR_MASK    0x4
#define    RTL8370_PORT8_EEECFG_EEE_WAKE_REQ_OFFSET    1
#define    RTL8370_PORT8_EEECFG_EEE_WAKE_REQ_MASK    0x2
#define    RTL8370_PORT8_EEECFG_EEE_SLEEP_REQ_OFFSET    0
#define    RTL8370_PORT8_EEECFG_EEE_SLEEP_REQ_MASK    0x1

#define    RTL8370_REG_P8EEETXMTR    0x0119

#define    RTL8370_REG_P8EEERXMTR    0x011a

#define    RTL8370_REG_P8EEEPTXMTR    0x011b

#define    RTL8370_REG_P8EEEPRXMTR    0x011c

#define    RTL8370_REG_P8_DUMMY2    0x011d

#define    RTL8370_REG_P8_DUMMY3    0x011e

#define    RTL8370_REG_P8_DUMMY4    0x011f

#define    RTL8370_REG_PKTGEN_PORT9_CTRL    0x0121
#define    RTL8370_PKTGEN_PORT9_CTRL_STATUS_OFFSET    15
#define    RTL8370_PKTGEN_PORT9_CTRL_STATUS_MASK    0x8000
#define    RTL8370_PKTGEN_PORT9_CTRL_ENABLED_OFFSET    9
#define    RTL8370_PKTGEN_PORT9_CTRL_ENABLED_MASK    0x200
#define    RTL8370_PKTGEN_PORT9_CTRL_INC_BC_OFFSET    8
#define    RTL8370_PKTGEN_PORT9_CTRL_INC_BC_MASK    0x100
#define    RTL8370_PKTGEN_PORT9_CTRL_INC_SA_OFFSET    7
#define    RTL8370_PKTGEN_PORT9_CTRL_INC_SA_MASK    0x80
#define    RTL8370_PKTGEN_PORT9_CTRL_INC_DA_OFFSET    6
#define    RTL8370_PKTGEN_PORT9_CTRL_INC_DA_MASK    0x40
#define    RTL8370_PKTGEN_PORT9_CTRL_RANDOM_OFFSET    5
#define    RTL8370_PKTGEN_PORT9_CTRL_RANDOM_MASK    0x20
#define    RTL8370_PKTGEN_PORT9_CTRL_CRC_NO_ERROR_OFFSET    4
#define    RTL8370_PKTGEN_PORT9_CTRL_CRC_NO_ERROR_MASK    0x10
#define    RTL8370_PKTGEN_PORT9_CTRL_CMD_CLEAR_OFFSET    3
#define    RTL8370_PKTGEN_PORT9_CTRL_CMD_CLEAR_MASK    0x8
#define    RTL8370_PKTGEN_PORT9_CTRL_CMD_CONTINUE_OFFSET    2
#define    RTL8370_PKTGEN_PORT9_CTRL_CMD_CONTINUE_MASK    0x4
#define    RTL8370_PKTGEN_PORT9_CTRL_CMD_PAUSE_OFFSET    1
#define    RTL8370_PKTGEN_PORT9_CTRL_CMD_PAUSE_MASK    0x2
#define    RTL8370_PKTGEN_PORT9_CTRL_CMD_START_OFFSET    0
#define    RTL8370_PKTGEN_PORT9_CTRL_CMD_START_MASK    0x1

#define    RTL8370_REG_P9_DUMMY5    0x0122

#define    RTL8370_REG_PKTGEN_PORT9_DA0    0x0123

#define    RTL8370_REG_PKTGEN_PORT9_DA1    0x0124

#define    RTL8370_REG_PKTGEN_PORT9_DA2    0x0125

#define    RTL8370_REG_PKTGEN_PORT9_SA0    0x0126

#define    RTL8370_REG_PKTGEN_PORT9_SA1    0x0127

#define    RTL8370_REG_PKTGEN_PORT9_SA2    0x0128

#define    RTL8370_REG_PKTGEN_PORT9_COUNTER0    0x0129

#define    RTL8370_REG_PKTGEN_PORT9_COUNTER1    0x012a
#define    RTL8370_PKTGEN_PORT9_COUNTER1_OFFSET    0
#define    RTL8370_PKTGEN_PORT9_COUNTER1_MASK    0xFF

#define    RTL8370_REG_PKTGEN_PORT9_TX_LENGTH    0x012b
#define    RTL8370_PKTGEN_PORT9_TX_LENGTH_OFFSET    0
#define    RTL8370_PKTGEN_PORT9_TX_LENGTH_MASK    0x3FFF

#define    RTL8370_REG_PKTGEN_PORT9_MAX_LENGTH    0x012c
#define    RTL8370_PKTGEN_PORT9_MAX_LENGTH_OFFSET    0
#define    RTL8370_PKTGEN_PORT9_MAX_LENGTH_MASK    0x3FFF

#define    RTL8370_REG_P9_DUMMY6    0x012d

#define    RTL8370_REG_PORT9_MISC_CFG    0x012e
#define    RTL8370_PORT9_MISC_CFG_TIMER_OFFSET    12
#define    RTL8370_PORT9_MISC_CFG_TIMER_MASK    0xF000
#define    RTL8370_INGRESSBW_PORT9_FLOWCRTL_OFFSET    11
#define    RTL8370_INGRESSBW_PORT9_FLOWCRTL_MASK    0x800
#define    RTL8370_INGRESSBW_PORT9_IFG_OFFSET    10
#define    RTL8370_INGRESSBW_PORT9_IFG_MASK    0x400
#define    RTL8370_PORT9_MISC_CFG_RX_SPC_OFFSET    9
#define    RTL8370_PORT9_MISC_CFG_RX_SPC_MASK    0x200
#define    RTL8370_PORT9_MISC_CFG_CRC_SKIP_OFFSET    8
#define    RTL8370_PORT9_MISC_CFG_CRC_SKIP_MASK    0x100
#define    RTL8370_PORT9_MISC_CFG_MAC_LOOPBACK_OFFSET    6
#define    RTL8370_PORT9_MISC_CFG_MAC_LOOPBACK_MASK    0x40
#define    RTL8370_VLAN_PORT9_EGRESS_MODE_OFFSET    4
#define    RTL8370_VLAN_PORT9_EGRESS_MODE_MASK    0x30
#define    RTL8370_CONGESTION_PORT9_SUSTAIN_TIME_OFFSET    0
#define    RTL8370_CONGESTION_PORT9_SUSTAIN_TIME_MASK    0xF

#define    RTL8370_REG_INGRESSBW_PORT9_RATE_CRTL0    0x012f

#define    RTL8370_REG_INGRESSBW_PORT9_RATE_CRTL1    0x0130
#define    RTL8370_INGRESSBW_PORT9_RATE_CRTL1_DUMMY_OFFSET    1
#define    RTL8370_INGRESSBW_PORT9_RATE_CRTL1_DUMMY_MASK    0xFFFE
#define    RTL8370_INGRESSBW_PORT9_RATE16_OFFSET    0
#define    RTL8370_INGRESSBW_PORT9_RATE16_MASK    0x1

#define    RTL8370_REG_PORT9_FORCE_RATE0    0x0131

#define    RTL8370_REG_PORT9_FORCE_RATE1    0x0132

#define    RTL8370_REG_PORT9_CURENT_RATE0    0x0133

#define    RTL8370_REG_PORT9_CURENT_RATE1    0x0134

#define    RTL8370_REG_PORT9_PAGE_COUNTER    0x0135
#define    RTL8370_PORT9_PAGE_COUNTER_OFFSET    0
#define    RTL8370_PORT9_PAGE_COUNTER_MASK    0x7F

#define    RTL8370_REG_PAGEMETER_PORT9_CTRL0    0x0136

#define    RTL8370_REG_PAGEMETER_PORT9_CTRL1    0x0137
#define    RTL8370_PAGEMETER_PORT9_CTRL1_OFFSET    0
#define    RTL8370_PAGEMETER_PORT9_CTRL1_MASK    0x3F

#define    RTL8370_REG_PORT9_EEECFG    0x0138
#define    RTL8370_PORT9_EEECFG_EEEP_ENABLE_TX_OFFSET    14
#define    RTL8370_PORT9_EEECFG_EEEP_ENABLE_TX_MASK    0x4000
#define    RTL8370_PORT9_EEECFG_EEEP_ENABLE_RX_OFFSET    13
#define    RTL8370_PORT9_EEECFG_EEEP_ENABLE_RX_MASK    0x2000
#define    RTL8370_PORT9_EEECFG_EEE_FORCE_OFFSET    12
#define    RTL8370_PORT9_EEECFG_EEE_FORCE_MASK    0x1000
#define    RTL8370_PORT9_EEECFG_EEE_100M_OFFSET    11
#define    RTL8370_PORT9_EEECFG_EEE_100M_MASK    0x800
#define    RTL8370_PORT9_EEECFG_EEE_GIGA_OFFSET    10
#define    RTL8370_PORT9_EEECFG_EEE_GIGA_MASK    0x400
#define    RTL8370_PORT9_EEECFG_EEE_TX_OFFSET    9
#define    RTL8370_PORT9_EEECFG_EEE_TX_MASK    0x200
#define    RTL8370_PORT9_EEECFG_EEE_RX_OFFSET    8
#define    RTL8370_PORT9_EEECFG_EEE_RX_MASK    0x100
#define    RTL8370_PORT9_EEECFG_EEE_LPI_OFFSET    5
#define    RTL8370_PORT9_EEECFG_EEE_LPI_MASK    0x20
#define    RTL8370_PORT9_EEECFG_EEE_TX_LPI_OFFSET    4
#define    RTL8370_PORT9_EEECFG_EEE_TX_LPI_MASK    0x10
#define    RTL8370_PORT9_EEECFG_EEE_RX_LPI_OFFSET    3
#define    RTL8370_PORT9_EEECFG_EEE_RX_LPI_MASK    0x8
#define    RTL8370_PORT9_EEECFG_EEE_PAUSE_INDICATOR_OFFSET    2
#define    RTL8370_PORT9_EEECFG_EEE_PAUSE_INDICATOR_MASK    0x4
#define    RTL8370_PORT9_EEECFG_EEE_WAKE_REQ_OFFSET    1
#define    RTL8370_PORT9_EEECFG_EEE_WAKE_REQ_MASK    0x2
#define    RTL8370_PORT9_EEECFG_EEE_SLEEP_REQ_OFFSET    0
#define    RTL8370_PORT9_EEECFG_EEE_SLEEP_REQ_MASK    0x1

#define    RTL8370_REG_P9EEETXMTR    0x0139

#define    RTL8370_REG_P9EEERXMTR    0x013a

#define    RTL8370_REG_P9EEEPTXMTR    0x013b

#define    RTL8370_REG_P9EEEPRXMTR    0x013c

#define    RTL8370_REG_P9_DUMMY2    0x013d

#define    RTL8370_REG_P9_DUMMY3    0x013e

#define    RTL8370_REG_P9_DUMMY4    0x013f

#define    RTL8370_REG_PKTGEN_PORT10_CTRL    0x0141
#define    RTL8370_PKTGEN_PORT10_CTRL_STATUS_OFFSET    15
#define    RTL8370_PKTGEN_PORT10_CTRL_STATUS_MASK    0x8000
#define    RTL8370_PKTGEN_PORT10_CTRL_ENABLED_OFFSET    9
#define    RTL8370_PKTGEN_PORT10_CTRL_ENABLED_MASK    0x200
#define    RTL8370_PKTGEN_PORT10_CTRL_INC_BC_OFFSET    8
#define    RTL8370_PKTGEN_PORT10_CTRL_INC_BC_MASK    0x100
#define    RTL8370_PKTGEN_PORT10_CTRL_INC_SA_OFFSET    7
#define    RTL8370_PKTGEN_PORT10_CTRL_INC_SA_MASK    0x80
#define    RTL8370_PKTGEN_PORT10_CTRL_INC_DA_OFFSET    6
#define    RTL8370_PKTGEN_PORT10_CTRL_INC_DA_MASK    0x40
#define    RTL8370_PKTGEN_PORT10_CTRL_RANDOM_OFFSET    5
#define    RTL8370_PKTGEN_PORT10_CTRL_RANDOM_MASK    0x20
#define    RTL8370_PKTGEN_PORT10_CTRL_CRC_NO_ERROR_OFFSET    4
#define    RTL8370_PKTGEN_PORT10_CTRL_CRC_NO_ERROR_MASK    0x10
#define    RTL8370_PKTGEN_PORT10_CTRL_CMD_CLEAR_OFFSET    3
#define    RTL8370_PKTGEN_PORT10_CTRL_CMD_CLEAR_MASK    0x8
#define    RTL8370_PKTGEN_PORT10_CTRL_CMD_CONTINUE_OFFSET    2
#define    RTL8370_PKTGEN_PORT10_CTRL_CMD_CONTINUE_MASK    0x4
#define    RTL8370_PKTGEN_PORT10_CTRL_CMD_PAUSE_OFFSET    1
#define    RTL8370_PKTGEN_PORT10_CTRL_CMD_PAUSE_MASK    0x2
#define    RTL8370_PKTGEN_PORT10_CTRL_CMD_START_OFFSET    0
#define    RTL8370_PKTGEN_PORT10_CTRL_CMD_START_MASK    0x1

#define    RTL8370_REG_P10_DUMMY5    0x0142

#define    RTL8370_REG_PKTGEN_PORT10_DA0    0x0143

#define    RTL8370_REG_PKTGEN_PORT10_DA1    0x0144

#define    RTL8370_REG_PKTGEN_PORT10_DA2    0x0145

#define    RTL8370_REG_PKTGEN_PORT10_SA0    0x0146

#define    RTL8370_REG_PKTGEN_PORT10_SA1    0x0147

#define    RTL8370_REG_PKTGEN_PORT10_SA2    0x0148

#define    RTL8370_REG_PKTGEN_PORT10_COUNTER0    0x0149

#define    RTL8370_REG_PKTGEN_PORT10_COUNTER1    0x014a
#define    RTL8370_PKTGEN_PORT10_COUNTER1_OFFSET    0
#define    RTL8370_PKTGEN_PORT10_COUNTER1_MASK    0xFF

#define    RTL8370_REG_PKTGEN_PORT10_TX_LENGTH    0x014b
#define    RTL8370_PKTGEN_PORT10_TX_LENGTH_OFFSET    0
#define    RTL8370_PKTGEN_PORT10_TX_LENGTH_MASK    0x3FFF

#define    RTL8370_REG_PKTGEN_PORT10_MAX_LENGTH    0x014c
#define    RTL8370_PKTGEN_PORT10_MAX_LENGTH_OFFSET    0
#define    RTL8370_PKTGEN_PORT10_MAX_LENGTH_MASK    0x3FFF

#define    RTL8370_REG_P10_DUMMY6    0x014d

#define    RTL8370_REG_PORT10_MISC_CFG    0x014e
#define    RTL8370_PORT10_MISC_CFG_TIMER_OFFSET    12
#define    RTL8370_PORT10_MISC_CFG_TIMER_MASK    0xF000
#define    RTL8370_INGRESSBW_PORT10_FLOWCRTL_OFFSET    11
#define    RTL8370_INGRESSBW_PORT10_FLOWCRTL_MASK    0x800
#define    RTL8370_INGRESSBW_PORT10_IFG_OFFSET    10
#define    RTL8370_INGRESSBW_PORT10_IFG_MASK    0x400
#define    RTL8370_PORT10_MISC_CFG_RX_SPC_OFFSET    9
#define    RTL8370_PORT10_MISC_CFG_RX_SPC_MASK    0x200
#define    RTL8370_PORT10_MISC_CFG_CRC_SKIP_OFFSET    8
#define    RTL8370_PORT10_MISC_CFG_CRC_SKIP_MASK    0x100
#define    RTL8370_PORT10_MISC_CFG_MAC_LOOPBACK_OFFSET    6
#define    RTL8370_PORT10_MISC_CFG_MAC_LOOPBACK_MASK    0x40
#define    RTL8370_VLAN_PORT10_EGRESS_MODE_OFFSET    4
#define    RTL8370_VLAN_PORT10_EGRESS_MODE_MASK    0x30
#define    RTL8370_CONGESTION_PORT10_SUSTAIN_TIME_OFFSET    0
#define    RTL8370_CONGESTION_PORT10_SUSTAIN_TIME_MASK    0xF

#define    RTL8370_REG_INGRESSBW_PORT10_RATE_CRTL0    0x014f

#define    RTL8370_REG_INGRESSBW_PORT10_RATE_CRTL1    0x0150
#define    RTL8370_INGRESSBW_PORT10_RATE_CRTL1_DUMMY_OFFSET    1
#define    RTL8370_INGRESSBW_PORT10_RATE_CRTL1_DUMMY_MASK    0xFFFE
#define    RTL8370_INGRESSBW_PORT10_RATE16_OFFSET    0
#define    RTL8370_INGRESSBW_PORT10_RATE16_MASK    0x1

#define    RTL8370_REG_PORT10_FORCE_RATE0    0x0151

#define    RTL8370_REG_PORT10_FORCE_RATE1    0x0152

#define    RTL8370_REG_PORT10_CURENT_RATE0    0x0153

#define    RTL8370_REG_PORT10_CURENT_RATE1    0x0154

#define    RTL8370_REG_PORT10_PAGE_COUNTER    0x0155
#define    RTL8370_PORT10_PAGE_COUNTER_OFFSET    0
#define    RTL8370_PORT10_PAGE_COUNTER_MASK    0x7F

#define    RTL8370_REG_PAGEMETER_PORT10_CTRL0    0x0156

#define    RTL8370_REG_PAGEMETER_PORT10_CTRL1    0x0157
#define    RTL8370_PAGEMETER_PORT10_CTRL1_OFFSET    0
#define    RTL8370_PAGEMETER_PORT10_CTRL1_MASK    0x3F

#define    RTL8370_REG_PORT10_EEECFG    0x0158
#define    RTL8370_PORT10_EEECFG_EEEP_ENABLE_TX_OFFSET    14
#define    RTL8370_PORT10_EEECFG_EEEP_ENABLE_TX_MASK    0x4000
#define    RTL8370_PORT10_EEECFG_EEEP_ENABLE_RX_OFFSET    13
#define    RTL8370_PORT10_EEECFG_EEEP_ENABLE_RX_MASK    0x2000
#define    RTL8370_PORT10_EEECFG_EEE_FORCE_OFFSET    12
#define    RTL8370_PORT10_EEECFG_EEE_FORCE_MASK    0x1000
#define    RTL8370_PORT10_EEECFG_EEE_100M_OFFSET    11
#define    RTL8370_PORT10_EEECFG_EEE_100M_MASK    0x800
#define    RTL8370_PORT10_EEECFG_EEE_GIGA_OFFSET    10
#define    RTL8370_PORT10_EEECFG_EEE_GIGA_MASK    0x400
#define    RTL8370_PORT10_EEECFG_EEE_TX_OFFSET    9
#define    RTL8370_PORT10_EEECFG_EEE_TX_MASK    0x200
#define    RTL8370_PORT10_EEECFG_EEE_RX_OFFSET    8
#define    RTL8370_PORT10_EEECFG_EEE_RX_MASK    0x100
#define    RTL8370_PORT10_EEECFG_EEE_LPI_OFFSET    5
#define    RTL8370_PORT10_EEECFG_EEE_LPI_MASK    0x20
#define    RTL8370_PORT10_EEECFG_EEE_TX_LPI_OFFSET    4
#define    RTL8370_PORT10_EEECFG_EEE_TX_LPI_MASK    0x10
#define    RTL8370_PORT10_EEECFG_EEE_RX_LPI_OFFSET    3
#define    RTL8370_PORT10_EEECFG_EEE_RX_LPI_MASK    0x8
#define    RTL8370_PORT10_EEECFG_EEE_PAUSE_INDICATOR_OFFSET    2
#define    RTL8370_PORT10_EEECFG_EEE_PAUSE_INDICATOR_MASK    0x4
#define    RTL8370_PORT10_EEECFG_EEE_WAKE_REQ_OFFSET    1
#define    RTL8370_PORT10_EEECFG_EEE_WAKE_REQ_MASK    0x2
#define    RTL8370_PORT10_EEECFG_EEE_SLEEP_REQ_OFFSET    0
#define    RTL8370_PORT10_EEECFG_EEE_SLEEP_REQ_MASK    0x1

#define    RTL8370_REG_P10EEETXMTR    0x0159

#define    RTL8370_REG_P10EEERXMTR    0x015a

#define    RTL8370_REG_P10EEEPTXMTR    0x015b

#define    RTL8370_REG_P10EEEPRXMTR    0x015c

#define    RTL8370_REG_P10_DUMMY2    0x015d

#define    RTL8370_REG_P10_DUMMY3    0x015e

#define    RTL8370_REG_P10_DUMMY4    0x015f

#define    RTL8370_REG_PKTGEN_PORT11_CTRL    0x0161
#define    RTL8370_PKTGEN_PORT11_CTRL_STATUS_OFFSET    15
#define    RTL8370_PKTGEN_PORT11_CTRL_STATUS_MASK    0x8000
#define    RTL8370_PKTGEN_PORT11_CTRL_ENABLED_OFFSET    9
#define    RTL8370_PKTGEN_PORT11_CTRL_ENABLED_MASK    0x200
#define    RTL8370_PKTGEN_PORT11_CTRL_INC_BC_OFFSET    8
#define    RTL8370_PKTGEN_PORT11_CTRL_INC_BC_MASK    0x100
#define    RTL8370_PKTGEN_PORT11_CTRL_INC_SA_OFFSET    7
#define    RTL8370_PKTGEN_PORT11_CTRL_INC_SA_MASK    0x80
#define    RTL8370_PKTGEN_PORT11_CTRL_INC_DA_OFFSET    6
#define    RTL8370_PKTGEN_PORT11_CTRL_INC_DA_MASK    0x40
#define    RTL8370_PKTGEN_PORT11_CTRL_RANDOM_OFFSET    5
#define    RTL8370_PKTGEN_PORT11_CTRL_RANDOM_MASK    0x20
#define    RTL8370_PKTGEN_PORT11_CTRL_CRC_NO_ERROR_OFFSET    4
#define    RTL8370_PKTGEN_PORT11_CTRL_CRC_NO_ERROR_MASK    0x10
#define    RTL8370_PKTGEN_PORT11_CTRL_CMD_CLEAR_OFFSET    3
#define    RTL8370_PKTGEN_PORT11_CTRL_CMD_CLEAR_MASK    0x8
#define    RTL8370_PKTGEN_PORT11_CTRL_CMD_CONTINUE_OFFSET    2
#define    RTL8370_PKTGEN_PORT11_CTRL_CMD_CONTINUE_MASK    0x4
#define    RTL8370_PKTGEN_PORT11_CTRL_CMD_PAUSE_OFFSET    1
#define    RTL8370_PKTGEN_PORT11_CTRL_CMD_PAUSE_MASK    0x2
#define    RTL8370_PKTGEN_PORT11_CTRL_CMD_START_OFFSET    0
#define    RTL8370_PKTGEN_PORT11_CTRL_CMD_START_MASK    0x1

#define    RTL8370_REG_P11_DUMMY5    0x0162

#define    RTL8370_REG_PKTGEN_PORT11_DA0    0x0163

#define    RTL8370_REG_PKTGEN_PORT11_DA1    0x0164

#define    RTL8370_REG_PKTGEN_PORT11_DA2    0x0165

#define    RTL8370_REG_PKTGEN_PORT11_SA0    0x0166

#define    RTL8370_REG_PKTGEN_PORT11_SA1    0x0167

#define    RTL8370_REG_PKTGEN_PORT11_SA2    0x0168

#define    RTL8370_REG_PKTGEN_PORT11_COUNTER0    0x0169

#define    RTL8370_REG_PKTGEN_PORT11_COUNTER1    0x016a
#define    RTL8370_PKTGEN_PORT11_COUNTER1_OFFSET    0
#define    RTL8370_PKTGEN_PORT11_COUNTER1_MASK    0xFF

#define    RTL8370_REG_PKTGEN_PORT11_TX_LENGTH    0x016b
#define    RTL8370_PKTGEN_PORT11_TX_LENGTH_OFFSET    0
#define    RTL8370_PKTGEN_PORT11_TX_LENGTH_MASK    0x3FFF

#define    RTL8370_REG_PKTGEN_PORT11_MAX_LENGTH    0x016c
#define    RTL8370_PKTGEN_PORT11_MAX_LENGTH_OFFSET    0
#define    RTL8370_PKTGEN_PORT11_MAX_LENGTH_MASK    0x3FFF

#define    RTL8370_REG_P11_DUMMY6    0x016d

#define    RTL8370_REG_PORT11_MISC_CFG    0x016e
#define    RTL8370_PORT11_MISC_CFG_TIMER_OFFSET    12
#define    RTL8370_PORT11_MISC_CFG_TIMER_MASK    0xF000
#define    RTL8370_INGRESSBW_PORT11_FLOWCRTL_OFFSET    11
#define    RTL8370_INGRESSBW_PORT11_FLOWCRTL_MASK    0x800
#define    RTL8370_INGRESSBW_PORT11_IFG_OFFSET    10
#define    RTL8370_INGRESSBW_PORT11_IFG_MASK    0x400
#define    RTL8370_PORT11_MISC_CFG_RX_SPC_OFFSET    9
#define    RTL8370_PORT11_MISC_CFG_RX_SPC_MASK    0x200
#define    RTL8370_PORT11_MISC_CFG_CRC_SKIP_OFFSET    8
#define    RTL8370_PORT11_MISC_CFG_CRC_SKIP_MASK    0x100
#define    RTL8370_PORT11_MISC_CFG_MAC_LOOPBACK_OFFSET    6
#define    RTL8370_PORT11_MISC_CFG_MAC_LOOPBACK_MASK    0x40
#define    RTL8370_VLAN_PORT11_EGRESS_MODE_OFFSET    4
#define    RTL8370_VLAN_PORT11_EGRESS_MODE_MASK    0x30
#define    RTL8370_CONGESTION_PORT11_SUSTAIN_TIME_OFFSET    0
#define    RTL8370_CONGESTION_PORT11_SUSTAIN_TIME_MASK    0xF

#define    RTL8370_REG_INGRESSBW_PORT11_RATE_CRTL0    0x016f

#define    RTL8370_REG_INGRESSBW_PORT11_RATE_CRTL1    0x0170
#define    RTL8370_INGRESSBW_PORT11_RATE_CRTL1_DUMMY_OFFSET    1
#define    RTL8370_INGRESSBW_PORT11_RATE_CRTL1_DUMMY_MASK    0xFFFE
#define    RTL8370_INGRESSBW_PORT11_RATE16_OFFSET    0
#define    RTL8370_INGRESSBW_PORT11_RATE16_MASK    0x1

#define    RTL8370_REG_PORT11_FORCE_RATE0    0x0171

#define    RTL8370_REG_PORT11_FORCE_RATE1    0x0172

#define    RTL8370_REG_PORT11_CURENT_RATE0    0x0173

#define    RTL8370_REG_PORT11_CURENT_RATE1    0x0174

#define    RTL8370_REG_PORT11_PAGE_COUNTER    0x0175
#define    RTL8370_PORT11_PAGE_COUNTER_OFFSET    0
#define    RTL8370_PORT11_PAGE_COUNTER_MASK    0x7F

#define    RTL8370_REG_PAGEMETER_PORT11_CTRL0    0x0176

#define    RTL8370_REG_PAGEMETER_PORT11_CTRL1    0x0177
#define    RTL8370_PAGEMETER_PORT11_CTRL1_OFFSET    0
#define    RTL8370_PAGEMETER_PORT11_CTRL1_MASK    0x3F

#define    RTL8370_REG_PORT11_EEECFG    0x0178
#define    RTL8370_PORT11_EEECFG_EEEP_ENABLE_RX_OFFSET    14
#define    RTL8370_PORT11_EEECFG_EEEP_ENABLE_RX_MASK    0x4000
#define    RTL8370_PORT11_EEECFG_EEE_FORCE_OFFSET    13
#define    RTL8370_PORT11_EEECFG_EEE_FORCE_MASK    0x2000
#define    RTL8370_PORT11_EEECFG_EEE_100M_OFFSET    11
#define    RTL8370_PORT11_EEECFG_EEE_100M_MASK    0x800
#define    RTL8370_PORT11_EEECFG_EEE_GIGA_OFFSET    10
#define    RTL8370_PORT11_EEECFG_EEE_GIGA_MASK    0x400
#define    RTL8370_PORT11_EEECFG_EEE_TX_OFFSET    9
#define    RTL8370_PORT11_EEECFG_EEE_TX_MASK    0x200
#define    RTL8370_PORT11_EEECFG_EEE_RX_OFFSET    8
#define    RTL8370_PORT11_EEECFG_EEE_RX_MASK    0x100
#define    RTL8370_PORT11_EEECFG_EEE_LPI_OFFSET    5
#define    RTL8370_PORT11_EEECFG_EEE_LPI_MASK    0x20
#define    RTL8370_PORT11_EEECFG_EEE_TX_LPI_OFFSET    4
#define    RTL8370_PORT11_EEECFG_EEE_TX_LPI_MASK    0x10
#define    RTL8370_PORT11_EEECFG_EEE_RX_LPI_OFFSET    3
#define    RTL8370_PORT11_EEECFG_EEE_RX_LPI_MASK    0x8
#define    RTL8370_PORT11_EEECFG_EEE_PAUSE_INDICATOR_OFFSET    2
#define    RTL8370_PORT11_EEECFG_EEE_PAUSE_INDICATOR_MASK    0x4
#define    RTL8370_PORT11_EEECFG_EEE_WAKE_REQ_OFFSET    1
#define    RTL8370_PORT11_EEECFG_EEE_WAKE_REQ_MASK    0x2
#define    RTL8370_PORT11_EEECFG_EEE_SLEEP_REQ_OFFSET    0
#define    RTL8370_PORT11_EEECFG_EEE_SLEEP_REQ_MASK    0x1

#define    RTL8370_REG_P11EEETXMTR    0x0179

#define    RTL8370_REG_P11EEERXMTR    0x017a

#define    RTL8370_REG_P11EEEPTXMTR    0x017b

#define    RTL8370_REG_P11EEEPRXMTR    0x017c

#define    RTL8370_REG_P11_DUMMY2    0x017d

#define    RTL8370_REG_P11_DUMMY3    0x017e

#define    RTL8370_REG_P11_DUMMY4    0x017f

#define    RTL8370_REG_PKTGEN_PORT12_CTRL    0x0181
#define    RTL8370_PKTGEN_PORT12_CTRL_STATUS_OFFSET    15
#define    RTL8370_PKTGEN_PORT12_CTRL_STATUS_MASK    0x8000
#define    RTL8370_PKTGEN_PORT12_CTRL_ENABLED_OFFSET    9
#define    RTL8370_PKTGEN_PORT12_CTRL_ENABLED_MASK    0x200
#define    RTL8370_PKTGEN_PORT12_CTRL_INC_BC_OFFSET    8
#define    RTL8370_PKTGEN_PORT12_CTRL_INC_BC_MASK    0x100
#define    RTL8370_PKTGEN_PORT12_CTRL_INC_SA_OFFSET    7
#define    RTL8370_PKTGEN_PORT12_CTRL_INC_SA_MASK    0x80
#define    RTL8370_PKTGEN_PORT12_CTRL_INC_DA_OFFSET    6
#define    RTL8370_PKTGEN_PORT12_CTRL_INC_DA_MASK    0x40
#define    RTL8370_PKTGEN_PORT12_CTRL_RANDOM_OFFSET    5
#define    RTL8370_PKTGEN_PORT12_CTRL_RANDOM_MASK    0x20
#define    RTL8370_PKTGEN_PORT12_CTRL_CRC_NO_ERROR_OFFSET    4
#define    RTL8370_PKTGEN_PORT12_CTRL_CRC_NO_ERROR_MASK    0x10
#define    RTL8370_PKTGEN_PORT12_CTRL_CMD_CLEAR_OFFSET    3
#define    RTL8370_PKTGEN_PORT12_CTRL_CMD_CLEAR_MASK    0x8
#define    RTL8370_PKTGEN_PORT12_CTRL_CMD_CONTINUE_OFFSET    2
#define    RTL8370_PKTGEN_PORT12_CTRL_CMD_CONTINUE_MASK    0x4
#define    RTL8370_PKTGEN_PORT12_CTRL_CMD_PAUSE_OFFSET    1
#define    RTL8370_PKTGEN_PORT12_CTRL_CMD_PAUSE_MASK    0x2
#define    RTL8370_PKTGEN_PORT12_CTRL_CMD_START_OFFSET    0
#define    RTL8370_PKTGEN_PORT12_CTRL_CMD_START_MASK    0x1

#define    RTL8370_REG_P12_DUMMY5    0x0182

#define    RTL8370_REG_PKTGEN_PORT12_DA0    0x0183

#define    RTL8370_REG_PKTGEN_PORT12_DA1    0x0184

#define    RTL8370_REG_PKTGEN_PORT12_DA2    0x0185

#define    RTL8370_REG_PKTGEN_PORT12_SA0    0x0186

#define    RTL8370_REG_PKTGEN_PORT12_SA1    0x0187

#define    RTL8370_REG_PKTGEN_PORT12_SA2    0x0188

#define    RTL8370_REG_PKTGEN_PORT12_COUNTER0    0x0189

#define    RTL8370_REG_PKTGEN_PORT12_COUNTER1    0x018a
#define    RTL8370_PKTGEN_PORT12_COUNTER1_OFFSET    0
#define    RTL8370_PKTGEN_PORT12_COUNTER1_MASK    0xFF

#define    RTL8370_REG_PKTGEN_PORT12_TX_LENGTH    0x018b
#define    RTL8370_PKTGEN_PORT12_TX_LENGTH_OFFSET    0
#define    RTL8370_PKTGEN_PORT12_TX_LENGTH_MASK    0x3FFF

#define    RTL8370_REG_PKTGEN_PORT12_MAX_LENGTH    0x018c
#define    RTL8370_PKTGEN_PORT12_MAX_LENGTH_OFFSET    0
#define    RTL8370_PKTGEN_PORT12_MAX_LENGTH_MASK    0x3FFF

#define    RTL8370_REG_P12_DUMMY6    0x018d

#define    RTL8370_REG_PORT12_MISC_CFG    0x018e
#define    RTL8370_PORT12_MISC_CFG_TIMER_OFFSET    12
#define    RTL8370_PORT12_MISC_CFG_TIMER_MASK    0xF000
#define    RTL8370_INGRESSBW_PORT12_FLOWCRTL_OFFSET    11
#define    RTL8370_INGRESSBW_PORT12_FLOWCRTL_MASK    0x800
#define    RTL8370_INGRESSBW_PORT12_IFG_OFFSET    10
#define    RTL8370_INGRESSBW_PORT12_IFG_MASK    0x400
#define    RTL8370_PORT12_MISC_CFG_RX_SPC_OFFSET    9
#define    RTL8370_PORT12_MISC_CFG_RX_SPC_MASK    0x200
#define    RTL8370_PORT12_MISC_CFG_CRC_SKIP_OFFSET    8
#define    RTL8370_PORT12_MISC_CFG_CRC_SKIP_MASK    0x100
#define    RTL8370_PORT12_MISC_CFG_MAC_LOOPBACK_OFFSET    6
#define    RTL8370_PORT12_MISC_CFG_MAC_LOOPBACK_MASK    0x40
#define    RTL8370_VLAN_PORT12_EGRESS_MODE_OFFSET    4
#define    RTL8370_VLAN_PORT12_EGRESS_MODE_MASK    0x30
#define    RTL8370_CONGESTION_PORT12_SUSTAIN_TIME_OFFSET    0
#define    RTL8370_CONGESTION_PORT12_SUSTAIN_TIME_MASK    0xF

#define    RTL8370_REG_INGRESSBW_PORT12_RATE_CRTL0    0x018f

#define    RTL8370_REG_INGRESSBW_PORT12_RATE_CRTL1    0x0190
#define    RTL8370_INGRESSBW_PORT12_RATE_CRTL1_DUMMY_OFFSET    1
#define    RTL8370_INGRESSBW_PORT12_RATE_CRTL1_DUMMY_MASK    0xFFFE
#define    RTL8370_INGRESSBW_PORT12_RATE16_OFFSET    0
#define    RTL8370_INGRESSBW_PORT12_RATE16_MASK    0x1

#define    RTL8370_REG_PORT12_FORCE_RATE0    0x0191

#define    RTL8370_REG_PORT12_FORCE_RATE1    0x0192

#define    RTL8370_REG_PORT12_CURENT_RATE0    0x0193

#define    RTL8370_REG_PORT12_CURENT_RATE1    0x0194

#define    RTL8370_REG_PORT12_PAGE_COUNTER    0x0195
#define    RTL8370_PORT12_PAGE_COUNTER_OFFSET    0
#define    RTL8370_PORT12_PAGE_COUNTER_MASK    0x7F

#define    RTL8370_REG_PAGEMETER_PORT12_CTRL0    0x0196

#define    RTL8370_REG_PAGEMETER_PORT12_CTRL1    0x0197
#define    RTL8370_PAGEMETER_PORT12_CTRL1_OFFSET    0
#define    RTL8370_PAGEMETER_PORT12_CTRL1_MASK    0x3F

#define    RTL8370_REG_PORT12_EEECFG    0x0198
#define    RTL8370_PORT12_EEECFG_EEEP_ENABLE_TX_OFFSET    14
#define    RTL8370_PORT12_EEECFG_EEEP_ENABLE_TX_MASK    0x4000
#define    RTL8370_PORT12_EEECFG_EEEP_ENABLE_RX_OFFSET    13
#define    RTL8370_PORT12_EEECFG_EEEP_ENABLE_RX_MASK    0x2000
#define    RTL8370_PORT12_EEECFG_EEE_FORCE_OFFSET    12
#define    RTL8370_PORT12_EEECFG_EEE_FORCE_MASK    0x1000
#define    RTL8370_PORT12_EEECFG_EEE_100M_OFFSET    11
#define    RTL8370_PORT12_EEECFG_EEE_100M_MASK    0x800
#define    RTL8370_PORT12_EEECFG_EEE_GIGA_OFFSET    10
#define    RTL8370_PORT12_EEECFG_EEE_GIGA_MASK    0x400
#define    RTL8370_PORT12_EEECFG_EEE_TX_OFFSET    9
#define    RTL8370_PORT12_EEECFG_EEE_TX_MASK    0x200
#define    RTL8370_PORT12_EEECFG_EEE_RX_OFFSET    8
#define    RTL8370_PORT12_EEECFG_EEE_RX_MASK    0x100
#define    RTL8370_PORT12_EEECFG_EEE_LPI_OFFSET    5
#define    RTL8370_PORT12_EEECFG_EEE_LPI_MASK    0x20
#define    RTL8370_PORT12_EEECFG_EEE_TX_LPI_OFFSET    4
#define    RTL8370_PORT12_EEECFG_EEE_TX_LPI_MASK    0x10
#define    RTL8370_PORT12_EEECFG_EEE_RX_LPI_OFFSET    3
#define    RTL8370_PORT12_EEECFG_EEE_RX_LPI_MASK    0x8
#define    RTL8370_PORT12_EEECFG_EEE_PAUSE_INDICATOR_OFFSET    2
#define    RTL8370_PORT12_EEECFG_EEE_PAUSE_INDICATOR_MASK    0x4
#define    RTL8370_PORT12_EEECFG_EEE_WAKE_REQ_OFFSET    1
#define    RTL8370_PORT12_EEECFG_EEE_WAKE_REQ_MASK    0x2
#define    RTL8370_PORT12_EEECFG_EEE_SLEEP_REQ_OFFSET    0
#define    RTL8370_PORT12_EEECFG_EEE_SLEEP_REQ_MASK    0x1

#define    RTL8370_REG_P12EEETXMTR    0x0199

#define    RTL8370_REG_P12EEERXMTR    0x019a

#define    RTL8370_REG_P12EEEPTXMTR    0x019b

#define    RTL8370_REG_P12EEEPRXMTR    0x019c

#define    RTL8370_REG_P12_DUMMY2    0x019d

#define    RTL8370_REG_P12_DUMMY3    0x019e

#define    RTL8370_REG_P12_DUMMY4    0x019f

#define    RTL8370_REG_PKTGEN_PORT13_CTRL    0x01a1
#define    RTL8370_PKTGEN_PORT13_CTRL_STATUS_OFFSET    15
#define    RTL8370_PKTGEN_PORT13_CTRL_STATUS_MASK    0x8000
#define    RTL8370_PKTGEN_PORT13_CTRL_ENABLED_OFFSET    9
#define    RTL8370_PKTGEN_PORT13_CTRL_ENABLED_MASK    0x200
#define    RTL8370_PKTGEN_PORT13_CTRL_INC_BC_OFFSET    8
#define    RTL8370_PKTGEN_PORT13_CTRL_INC_BC_MASK    0x100
#define    RTL8370_PKTGEN_PORT13_CTRL_INC_SA_OFFSET    7
#define    RTL8370_PKTGEN_PORT13_CTRL_INC_SA_MASK    0x80
#define    RTL8370_PKTGEN_PORT13_CTRL_INC_DA_OFFSET    6
#define    RTL8370_PKTGEN_PORT13_CTRL_INC_DA_MASK    0x40
#define    RTL8370_PKTGEN_PORT13_CTRL_RANDOM_OFFSET    5
#define    RTL8370_PKTGEN_PORT13_CTRL_RANDOM_MASK    0x20
#define    RTL8370_PKTGEN_PORT13_CTRL_CRC_NO_ERROR_OFFSET    4
#define    RTL8370_PKTGEN_PORT13_CTRL_CRC_NO_ERROR_MASK    0x10
#define    RTL8370_PKTGEN_PORT13_CTRL_CMD_CLEAR_OFFSET    3
#define    RTL8370_PKTGEN_PORT13_CTRL_CMD_CLEAR_MASK    0x8
#define    RTL8370_PKTGEN_PORT13_CTRL_CMD_CONTINUE_OFFSET    2
#define    RTL8370_PKTGEN_PORT13_CTRL_CMD_CONTINUE_MASK    0x4
#define    RTL8370_PKTGEN_PORT13_CTRL_CMD_PAUSE_OFFSET    1
#define    RTL8370_PKTGEN_PORT13_CTRL_CMD_PAUSE_MASK    0x2
#define    RTL8370_PKTGEN_PORT13_CTRL_CMD_START_OFFSET    0
#define    RTL8370_PKTGEN_PORT13_CTRL_CMD_START_MASK    0x1

#define    RTL8370_REG_P13_DUMMY5    0x01a2

#define    RTL8370_REG_PKTGEN_PORT13_DA0    0x01a3

#define    RTL8370_REG_PKTGEN_PORT13_DA1    0x01a4

#define    RTL8370_REG_PKTGEN_PORT13_DA2    0x01a5

#define    RTL8370_REG_PKTGEN_PORT13_SA0    0x01a6

#define    RTL8370_REG_PKTGEN_PORT13_SA1    0x01a7

#define    RTL8370_REG_PKTGEN_PORT13_SA2    0x01a8

#define    RTL8370_REG_PKTGEN_PORT13_COUNTER0    0x01a9

#define    RTL8370_REG_PKTGEN_PORT13_COUNTER1    0x01aa
#define    RTL8370_PKTGEN_PORT13_COUNTER1_OFFSET    0
#define    RTL8370_PKTGEN_PORT13_COUNTER1_MASK    0xFF

#define    RTL8370_REG_PKTGEN_PORT13_TX_LENGTH    0x01ab
#define    RTL8370_PKTGEN_PORT13_TX_LENGTH_OFFSET    0
#define    RTL8370_PKTGEN_PORT13_TX_LENGTH_MASK    0x3FFF

#define    RTL8370_REG_PKTGEN_PORT13_MAX_LENGTH    0x01ac
#define    RTL8370_PKTGEN_PORT13_MAX_LENGTH_OFFSET    0
#define    RTL8370_PKTGEN_PORT13_MAX_LENGTH_MASK    0x3FFF

#define    RTL8370_REG_P13_DUMMY6    0x01ad

#define    RTL8370_REG_PORT13_MISC_CFG    0x01ae
#define    RTL8370_PORT13_MISC_CFG_TIMER_OFFSET    12
#define    RTL8370_PORT13_MISC_CFG_TIMER_MASK    0xF000
#define    RTL8370_INGRESSBW_PORT13_FLOWCRTL_OFFSET    11
#define    RTL8370_INGRESSBW_PORT13_FLOWCRTL_MASK    0x800
#define    RTL8370_INGRESSBW_PORT13_IFG_OFFSET    10
#define    RTL8370_INGRESSBW_PORT13_IFG_MASK    0x400
#define    RTL8370_PORT13_MISC_CFG_RX_SPC_OFFSET    9
#define    RTL8370_PORT13_MISC_CFG_RX_SPC_MASK    0x200
#define    RTL8370_PORT13_MISC_CFG_CRC_SKIP_OFFSET    8
#define    RTL8370_PORT13_MISC_CFG_CRC_SKIP_MASK    0x100
#define    RTL8370_PORT13_MISC_CFG_MAC_LOOPBACK_OFFSET    6
#define    RTL8370_PORT13_MISC_CFG_MAC_LOOPBACK_MASK    0x40
#define    RTL8370_VLAN_PORT13_EGRESS_MODE_OFFSET    4
#define    RTL8370_VLAN_PORT13_EGRESS_MODE_MASK    0x30
#define    RTL8370_CONGESTION_PORT13_SUSTAIN_TIME_OFFSET    0
#define    RTL8370_CONGESTION_PORT13_SUSTAIN_TIME_MASK    0xF

#define    RTL8370_REG_INGRESSBW_PORT13_RATE_CRTL0    0x01af

#define    RTL8370_REG_INGRESSBW_PORT13_RATE_CRTL1    0x01b0
#define    RTL8370_INGRESSBW_PORT13_RATE_CRTL1_DUMMY_OFFSET    1
#define    RTL8370_INGRESSBW_PORT13_RATE_CRTL1_DUMMY_MASK    0xFFFE
#define    RTL8370_INGRESSBW_PORT13_RATE16_OFFSET    0
#define    RTL8370_INGRESSBW_PORT13_RATE16_MASK    0x1

#define    RTL8370_REG_PORT13_FORCE_RATE0    0x01b1

#define    RTL8370_REG_PORT13_FORCE_RATE1    0x01b2

#define    RTL8370_REG_PORT13_CURENT_RATE0    0x01b3

#define    RTL8370_REG_PORT13_CURENT_RATE1    0x01b4

#define    RTL8370_REG_PORT13_PAGE_COUNTER    0x01b5
#define    RTL8370_PORT13_PAGE_COUNTER_OFFSET    0
#define    RTL8370_PORT13_PAGE_COUNTER_MASK    0x7F

#define    RTL8370_REG_PAGEMETER_PORT13_CTRL0    0x01b6

#define    RTL8370_REG_PAGEMETER_PORT13_CTRL1    0x01b7
#define    RTL8370_PAGEMETER_PORT13_CTRL1_OFFSET    0
#define    RTL8370_PAGEMETER_PORT13_CTRL1_MASK    0x3F

#define    RTL8370_REG_PORT13_EEECFG    0x01b8
#define    RTL8370_PORT13_EEECFG_EEEP_ENABLE_TX_OFFSET    14
#define    RTL8370_PORT13_EEECFG_EEEP_ENABLE_TX_MASK    0x4000
#define    RTL8370_PORT13_EEECFG_EEEP_ENABLE_RX_OFFSET    13
#define    RTL8370_PORT13_EEECFG_EEEP_ENABLE_RX_MASK    0x2000
#define    RTL8370_PORT13_EEECFG_EEE_FORCE_OFFSET    12
#define    RTL8370_PORT13_EEECFG_EEE_FORCE_MASK    0x1000
#define    RTL8370_PORT13_EEECFG_EEE_100M_OFFSET    11
#define    RTL8370_PORT13_EEECFG_EEE_100M_MASK    0x800
#define    RTL8370_PORT13_EEECFG_EEE_GIGA_OFFSET    10
#define    RTL8370_PORT13_EEECFG_EEE_GIGA_MASK    0x400
#define    RTL8370_PORT13_EEECFG_EEE_TX_OFFSET    9
#define    RTL8370_PORT13_EEECFG_EEE_TX_MASK    0x200
#define    RTL8370_PORT13_EEECFG_EEE_RX_OFFSET    8
#define    RTL8370_PORT13_EEECFG_EEE_RX_MASK    0x100
#define    RTL8370_PORT13_EEECFG_EEE_LPI_OFFSET    5
#define    RTL8370_PORT13_EEECFG_EEE_LPI_MASK    0x20
#define    RTL8370_PORT13_EEECFG_EEE_TX_LPI_OFFSET    4
#define    RTL8370_PORT13_EEECFG_EEE_TX_LPI_MASK    0x10
#define    RTL8370_PORT13_EEECFG_EEE_RX_LPI_OFFSET    3
#define    RTL8370_PORT13_EEECFG_EEE_RX_LPI_MASK    0x8
#define    RTL8370_PORT13_EEECFG_EEE_PAUSE_INDICATOR_OFFSET    2
#define    RTL8370_PORT13_EEECFG_EEE_PAUSE_INDICATOR_MASK    0x4
#define    RTL8370_PORT13_EEECFG_EEE_WAKE_REQ_OFFSET    1
#define    RTL8370_PORT13_EEECFG_EEE_WAKE_REQ_MASK    0x2
#define    RTL8370_PORT13_EEECFG_EEE_SLEEP_REQ_OFFSET    0
#define    RTL8370_PORT13_EEECFG_EEE_SLEEP_REQ_MASK    0x1

#define    RTL8370_REG_P13EEETXMTR    0x01b9

#define    RTL8370_REG_P13EEERXMTR    0x01ba

#define    RTL8370_REG_P13EEEPTXMTR    0x01bb

#define    RTL8370_REG_P13EEEPRXMTR    0x01bc

#define    RTL8370_REG_P13_DUMMY2    0x01bd

#define    RTL8370_REG_P13_DUMMY3    0x01be

#define    RTL8370_REG_P13_DUMMY4    0x01bf

#define    RTL8370_REG_PKTGEN_PORT14_CTRL    0x01c1
#define    RTL8370_PKTGEN_PORT14_CTRL_STATUS_OFFSET    15
#define    RTL8370_PKTGEN_PORT14_CTRL_STATUS_MASK    0x8000
#define    RTL8370_PKTGEN_PORT14_CTRL_ENABLED_OFFSET    9
#define    RTL8370_PKTGEN_PORT14_CTRL_ENABLED_MASK    0x200
#define    RTL8370_PKTGEN_PORT14_CTRL_INC_BC_OFFSET    8
#define    RTL8370_PKTGEN_PORT14_CTRL_INC_BC_MASK    0x100
#define    RTL8370_PKTGEN_PORT14_CTRL_INC_SA_OFFSET    7
#define    RTL8370_PKTGEN_PORT14_CTRL_INC_SA_MASK    0x80
#define    RTL8370_PKTGEN_PORT14_CTRL_INC_DA_OFFSET    6
#define    RTL8370_PKTGEN_PORT14_CTRL_INC_DA_MASK    0x40
#define    RTL8370_PKTGEN_PORT14_CTRL_RANDOM_OFFSET    5
#define    RTL8370_PKTGEN_PORT14_CTRL_RANDOM_MASK    0x20
#define    RTL8370_PKTGEN_PORT14_CTRL_CRC_NO_ERROR_OFFSET    4
#define    RTL8370_PKTGEN_PORT14_CTRL_CRC_NO_ERROR_MASK    0x10
#define    RTL8370_PKTGEN_PORT14_CTRL_CMD_CLEAR_OFFSET    3
#define    RTL8370_PKTGEN_PORT14_CTRL_CMD_CLEAR_MASK    0x8
#define    RTL8370_PKTGEN_PORT14_CTRL_CMD_CONTINUE_OFFSET    2
#define    RTL8370_PKTGEN_PORT14_CTRL_CMD_CONTINUE_MASK    0x4
#define    RTL8370_PKTGEN_PORT14_CTRL_CMD_PAUSE_OFFSET    1
#define    RTL8370_PKTGEN_PORT14_CTRL_CMD_PAUSE_MASK    0x2
#define    RTL8370_PKTGEN_PORT14_CTRL_CMD_START_OFFSET    0
#define    RTL8370_PKTGEN_PORT14_CTRL_CMD_START_MASK    0x1

#define    RTL8370_REG_P14_DUMMY5    0x01c2

#define    RTL8370_REG_PKTGEN_PORT14_DA0    0x01c3

#define    RTL8370_REG_PKTGEN_PORT14_DA1    0x01c4

#define    RTL8370_REG_PKTGEN_PORT14_DA2    0x01c5

#define    RTL8370_REG_PKTGEN_PORT14_SA0    0x01c6

#define    RTL8370_REG_PKTGEN_PORT14_SA1    0x01c7

#define    RTL8370_REG_PKTGEN_PORT14_SA2    0x01c8

#define    RTL8370_REG_PKTGEN_PORT14_COUNTER0    0x01c9

#define    RTL8370_REG_PKTGEN_PORT14_COUNTER1    0x01ca
#define    RTL8370_PKTGEN_PORT14_COUNTER1_OFFSET    0
#define    RTL8370_PKTGEN_PORT14_COUNTER1_MASK    0xFF

#define    RTL8370_REG_PKTGEN_PORT14_TX_LENGTH    0x01cb
#define    RTL8370_PKTGEN_PORT14_TX_LENGTH_OFFSET    0
#define    RTL8370_PKTGEN_PORT14_TX_LENGTH_MASK    0x3FFF

#define    RTL8370_REG_PKTGEN_PORT14_MAX_LENGTH    0x01cc
#define    RTL8370_PKTGEN_PORT14_MAX_LENGTH_OFFSET    0
#define    RTL8370_PKTGEN_PORT14_MAX_LENGTH_MASK    0x3FFF

#define    RTL8370_REG_P14_DUMMY6    0x01cd

#define    RTL8370_REG_PORT14_MISC_CFG    0x01ce
#define    RTL8370_PORT14_MISC_CFG_TIMER_OFFSET    12
#define    RTL8370_PORT14_MISC_CFG_TIMER_MASK    0xF000
#define    RTL8370_INGRESSBW_PORT14_FLOWCRTL_OFFSET    11
#define    RTL8370_INGRESSBW_PORT14_FLOWCRTL_MASK    0x800
#define    RTL8370_INGRESSBW_PORT14_IFG_OFFSET    10
#define    RTL8370_INGRESSBW_PORT14_IFG_MASK    0x400
#define    RTL8370_PORT14_MISC_CFG_RX_SPC_OFFSET    9
#define    RTL8370_PORT14_MISC_CFG_RX_SPC_MASK    0x200
#define    RTL8370_PORT14_MISC_CFG_CRC_SKIP_OFFSET    8
#define    RTL8370_PORT14_MISC_CFG_CRC_SKIP_MASK    0x100
#define    RTL8370_PORT14_MISC_CFG_MAC_LOOPBACK_OFFSET    6
#define    RTL8370_PORT14_MISC_CFG_MAC_LOOPBACK_MASK    0x40
#define    RTL8370_VLAN_PORT14_EGRESS_MODE_OFFSET    4
#define    RTL8370_VLAN_PORT14_EGRESS_MODE_MASK    0x30
#define    RTL8370_CONGESTION_PORT14_SUSTAIN_TIME_OFFSET    0
#define    RTL8370_CONGESTION_PORT14_SUSTAIN_TIME_MASK    0xF

#define    RTL8370_REG_INGRESSBW_PORT14_RATE_CRTL0    0x01cf

#define    RTL8370_REG_INGRESSBW_PORT14_RATE_CRTL1    0x01d0
#define    RTL8370_INGRESSBW_PORT14_RATE_CRTL1_DUMMY_OFFSET    1
#define    RTL8370_INGRESSBW_PORT14_RATE_CRTL1_DUMMY_MASK    0xFFFE
#define    RTL8370_INGRESSBW_PORT14_RATE16_OFFSET    0
#define    RTL8370_INGRESSBW_PORT14_RATE16_MASK    0x1

#define    RTL8370_REG_PORT14_FORCE_RATE0    0x01d1

#define    RTL8370_REG_PORT14_FORCE_RATE1    0x01d2

#define    RTL8370_REG_PORT14_CURENT_RATE0    0x01d3

#define    RTL8370_REG_PORT14_CURENT_RATE1    0x01d4

#define    RTL8370_REG_PORT14_PAGE_COUNTER    0x01d5
#define    RTL8370_PORT14_PAGE_COUNTER_OFFSET    0
#define    RTL8370_PORT14_PAGE_COUNTER_MASK    0x7F

#define    RTL8370_REG_PAGEMETER_PORT14_CTRL0    0x01d6

#define    RTL8370_REG_PAGEMETER_PORT14_CTRL1    0x01d7
#define    RTL8370_PAGEMETER_PORT14_CTRL1_OFFSET    0
#define    RTL8370_PAGEMETER_PORT14_CTRL1_MASK    0x3F

#define    RTL8370_REG_PORT14_EEECFG    0x01d8
#define    RTL8370_PORT14_EEECFG_EEEP_ENABLE_TX_OFFSET    14
#define    RTL8370_PORT14_EEECFG_EEEP_ENABLE_TX_MASK    0x4000
#define    RTL8370_PORT14_EEECFG_EEEP_ENABLE_RX_OFFSET    13
#define    RTL8370_PORT14_EEECFG_EEEP_ENABLE_RX_MASK    0x2000
#define    RTL8370_PORT14_EEECFG_EEE_FORCE_OFFSET    12
#define    RTL8370_PORT14_EEECFG_EEE_FORCE_MASK    0x1000
#define    RTL8370_PORT14_EEECFG_EEE_100M_OFFSET    11
#define    RTL8370_PORT14_EEECFG_EEE_100M_MASK    0x800
#define    RTL8370_PORT14_EEECFG_EEE_GIGA_OFFSET    10
#define    RTL8370_PORT14_EEECFG_EEE_GIGA_MASK    0x400
#define    RTL8370_PORT14_EEECFG_EEE_TX_OFFSET    9
#define    RTL8370_PORT14_EEECFG_EEE_TX_MASK    0x200
#define    RTL8370_PORT14_EEECFG_EEE_RX_OFFSET    8
#define    RTL8370_PORT14_EEECFG_EEE_RX_MASK    0x100
#define    RTL8370_PORT14_EEECFG_EEE_LPI_OFFSET    5
#define    RTL8370_PORT14_EEECFG_EEE_LPI_MASK    0x20
#define    RTL8370_PORT14_EEECFG_EEE_TX_LPI_OFFSET    4
#define    RTL8370_PORT14_EEECFG_EEE_TX_LPI_MASK    0x10
#define    RTL8370_PORT14_EEECFG_EEE_RX_LPI_OFFSET    3
#define    RTL8370_PORT14_EEECFG_EEE_RX_LPI_MASK    0x8
#define    RTL8370_PORT14_EEECFG_EEE_PAUSE_INDICATOR_OFFSET    2
#define    RTL8370_PORT14_EEECFG_EEE_PAUSE_INDICATOR_MASK    0x4
#define    RTL8370_PORT14_EEECFG_EEE_WAKE_REQ_OFFSET    1
#define    RTL8370_PORT14_EEECFG_EEE_WAKE_REQ_MASK    0x2
#define    RTL8370_PORT14_EEECFG_EEE_SLEEP_REQ_OFFSET    0
#define    RTL8370_PORT14_EEECFG_EEE_SLEEP_REQ_MASK    0x1

#define    RTL8370_REG_P14EEETXMTR    0x01d9

#define    RTL8370_REG_P14EEERXMTR    0x01da

#define    RTL8370_REG_P14EEEPTXMTR    0x01db

#define    RTL8370_REG_P14EEEPRXMTR    0x01dc

#define    RTL8370_REG_P14_DUMMY2    0x01dd

#define    RTL8370_REG_P14_DUMMY3    0x01de

#define    RTL8370_REG_P14_DUMMY4    0x01df

#define    RTL8370_REG_PKTGEN_PORT15_CTRL    0x01e1
#define    RTL8370_PKTGEN_PORT15_CTRL_STATUS_OFFSET    15
#define    RTL8370_PKTGEN_PORT15_CTRL_STATUS_MASK    0x8000
#define    RTL8370_PKTGEN_PORT15_CTRL_ENABLED_OFFSET    9
#define    RTL8370_PKTGEN_PORT15_CTRL_ENABLED_MASK    0x200
#define    RTL8370_PKTGEN_PORT15_CTRL_INC_BC_OFFSET    8
#define    RTL8370_PKTGEN_PORT15_CTRL_INC_BC_MASK    0x100
#define    RTL8370_PKTGEN_PORT15_CTRL_INC_SA_OFFSET    7
#define    RTL8370_PKTGEN_PORT15_CTRL_INC_SA_MASK    0x80
#define    RTL8370_PKTGEN_PORT15_CTRL_INC_DA_OFFSET    6
#define    RTL8370_PKTGEN_PORT15_CTRL_INC_DA_MASK    0x40
#define    RTL8370_PKTGEN_PORT15_CTRL_RANDOM_OFFSET    5
#define    RTL8370_PKTGEN_PORT15_CTRL_RANDOM_MASK    0x20
#define    RTL8370_PKTGEN_PORT15_CTRL_CRC_NO_ERROR_OFFSET    4
#define    RTL8370_PKTGEN_PORT15_CTRL_CRC_NO_ERROR_MASK    0x10
#define    RTL8370_PKTGEN_PORT15_CTRL_CMD_CLEAR_OFFSET    3
#define    RTL8370_PKTGEN_PORT15_CTRL_CMD_CLEAR_MASK    0x8
#define    RTL8370_PKTGEN_PORT15_CTRL_CMD_CONTINUE_OFFSET    2
#define    RTL8370_PKTGEN_PORT15_CTRL_CMD_CONTINUE_MASK    0x4
#define    RTL8370_PKTGEN_PORT15_CTRL_CMD_PAUSE_OFFSET    1
#define    RTL8370_PKTGEN_PORT15_CTRL_CMD_PAUSE_MASK    0x2
#define    RTL8370_PKTGEN_PORT15_CTRL_CMD_START_OFFSET    0
#define    RTL8370_PKTGEN_PORT15_CTRL_CMD_START_MASK    0x1

#define    RTL8370_REG_P15_DUMMY5    0x01e2

#define    RTL8370_REG_PKTGEN_PORT15_DA0    0x01e3

#define    RTL8370_REG_PKTGEN_PORT15_DA1    0x01e4

#define    RTL8370_REG_PKTGEN_PORT15_DA2    0x01e5

#define    RTL8370_REG_PKTGEN_PORT15_SA0    0x01e6

#define    RTL8370_REG_PKTGEN_PORT15_SA1    0x01e7

#define    RTL8370_REG_PKTGEN_PORT15_SA2    0x01e8

#define    RTL8370_REG_PKTGEN_PORT15_COUNTER0    0x01e9

#define    RTL8370_REG_PKTGEN_PORT15_COUNTER1    0x01ea
#define    RTL8370_PKTGEN_PORT15_COUNTER1_OFFSET    0
#define    RTL8370_PKTGEN_PORT15_COUNTER1_MASK    0xFF

#define    RTL8370_REG_PKTGEN_PORT15_TX_LENGTH    0x01eb
#define    RTL8370_PKTGEN_PORT15_TX_LENGTH_OFFSET    0
#define    RTL8370_PKTGEN_PORT15_TX_LENGTH_MASK    0x3FFF

#define    RTL8370_REG_PKTGEN_PORT15_MAX_LENGTH    0x01ec
#define    RTL8370_PKTGEN_PORT15_MAX_LENGTH_OFFSET    0
#define    RTL8370_PKTGEN_PORT15_MAX_LENGTH_MASK    0x3FFF

#define    RTL8370_REG_P15_DUMMY6    0x01ed

#define    RTL8370_REG_PORT15_MISC_CFG    0x01ee
#define    RTL8370_PORT15_MISC_CFG_TIMER_OFFSET    12
#define    RTL8370_PORT15_MISC_CFG_TIMER_MASK    0xF000
#define    RTL8370_INGRESSBW_PORT15_FLOWCRTL_OFFSET    11
#define    RTL8370_INGRESSBW_PORT15_FLOWCRTL_MASK    0x800
#define    RTL8370_INGRESSBW_PORT15_IFG_OFFSET    10
#define    RTL8370_INGRESSBW_PORT15_IFG_MASK    0x400
#define    RTL8370_PORT15_MISC_CFG_RX_SPC_OFFSET    9
#define    RTL8370_PORT15_MISC_CFG_RX_SPC_MASK    0x200
#define    RTL8370_PORT15_MISC_CFG_CRC_SKIP_OFFSET    8
#define    RTL8370_PORT15_MISC_CFG_CRC_SKIP_MASK    0x100
#define    RTL8370_PORT15_MISC_CFG_MAC_LOOPBACK_OFFSET    6
#define    RTL8370_PORT15_MISC_CFG_MAC_LOOPBACK_MASK    0x40
#define    RTL8370_VLAN_PORT15_EGRESS_MODE_OFFSET    4
#define    RTL8370_VLAN_PORT15_EGRESS_MODE_MASK    0x30
#define    RTL8370_CONGESTION_PORT15_SUSTAIN_TIME_OFFSET    0
#define    RTL8370_CONGESTION_PORT15_SUSTAIN_TIME_MASK    0xF

#define    RTL8370_REG_INGRESSBW_PORT15_RATE_CRTL0    0x01ef

#define    RTL8370_REG_INGRESSBW_PORT15_RATE_CRTL1    0x01f0
#define    RTL8370_INGRESSBW_PORT15_RATE_CRTL1_DUMMY_OFFSET    1
#define    RTL8370_INGRESSBW_PORT15_RATE_CRTL1_DUMMY_MASK    0xFFFE
#define    RTL8370_INGRESSBW_PORT15_RATE16_OFFSET    0
#define    RTL8370_INGRESSBW_PORT15_RATE16_MASK    0x1

#define    RTL8370_REG_PORT15_FORCE_RATE0    0x01f1

#define    RTL8370_REG_PORT15_FORCE_RATE1    0x01f2

#define    RTL8370_REG_PORT15_CURENT_RATE0    0x01f3

#define    RTL8370_REG_PORT15_CURENT_RATE1    0x01f4

#define    RTL8370_REG_PORT15_PAGE_COUNTER    0x01f5
#define    RTL8370_PORT15_PAGE_COUNTER_OFFSET    0
#define    RTL8370_PORT15_PAGE_COUNTER_MASK    0x7F

#define    RTL8370_REG_PAGEMETER_PORT15_CTRL0    0x01f6

#define    RTL8370_REG_PAGEMETER_PORT15_CTRL1    0x01f7
#define    RTL8370_PAGEMETER_PORT15_CTRL1_OFFSET    0
#define    RTL8370_PAGEMETER_PORT15_CTRL1_MASK    0x3F

#define    RTL8370_REG_PORT15_EEECFG    0x01f8
#define    RTL8370_PORT15_EEECFG_EEEP_ENABLE_TX_OFFSET    14
#define    RTL8370_PORT15_EEECFG_EEEP_ENABLE_TX_MASK    0x4000
#define    RTL8370_PORT15_EEECFG_EEEP_ENABLE_RX_OFFSET    13
#define    RTL8370_PORT15_EEECFG_EEEP_ENABLE_RX_MASK    0x2000
#define    RTL8370_PORT15_EEECFG_EEE_FORCE_OFFSET    12
#define    RTL8370_PORT15_EEECFG_EEE_FORCE_MASK    0x1000
#define    RTL8370_PORT15_EEECFG_EEE_100M_OFFSET    11
#define    RTL8370_PORT15_EEECFG_EEE_100M_MASK    0x800
#define    RTL8370_PORT15_EEECFG_EEE_GIGA_OFFSET    10
#define    RTL8370_PORT15_EEECFG_EEE_GIGA_MASK    0x400
#define    RTL8370_PORT15_EEECFG_EEE_TX_OFFSET    9
#define    RTL8370_PORT15_EEECFG_EEE_TX_MASK    0x200
#define    RTL8370_PORT15_EEECFG_EEE_RX_OFFSET    8
#define    RTL8370_PORT15_EEECFG_EEE_RX_MASK    0x100
#define    RTL8370_PORT15_EEECFG_EEE_LPI_OFFSET    5
#define    RTL8370_PORT15_EEECFG_EEE_LPI_MASK    0x20
#define    RTL8370_PORT15_EEECFG_EEE_TX_LPI_OFFSET    4
#define    RTL8370_PORT15_EEECFG_EEE_TX_LPI_MASK    0x10
#define    RTL8370_PORT15_EEECFG_EEE_RX_LPI_OFFSET    3
#define    RTL8370_PORT15_EEECFG_EEE_RX_LPI_MASK    0x8
#define    RTL8370_PORT15_EEECFG_EEE_PAUSE_INDICATOR_OFFSET    2
#define    RTL8370_PORT15_EEECFG_EEE_PAUSE_INDICATOR_MASK    0x4
#define    RTL8370_PORT15_EEECFG_EEE_WAKE_REQ_OFFSET    1
#define    RTL8370_PORT15_EEECFG_EEE_WAKE_REQ_MASK    0x2
#define    RTL8370_PORT15_EEECFG_EEE_SLEEP_REQ_OFFSET    0
#define    RTL8370_PORT15_EEECFG_EEE_SLEEP_REQ_MASK    0x1

#define    RTL8370_REG_P15EEETXMTR    0x01f9

#define    RTL8370_REG_P15EEERXMTR    0x01fa

#define    RTL8370_REG_P15EEEPTXMTR    0x01fb

#define    RTL8370_REG_P15EEEPRXMTR    0x01fc

#define    RTL8370_REG_P15_DUMMY2    0x01fd

#define    RTL8370_REG_P15_DUMMY3    0x01fe

#define    RTL8370_REG_P15_DUMMY4    0x01ff

/* (16'h0200) outq_reg */

#define    RTL8370_REG_FLOWCTRL_QUEUE0_DROP_ON    0x0200
#define    RTL8370_FLOWCTRL_QUEUE0_DROP_ON_OFFSET    0
#define    RTL8370_FLOWCTRL_QUEUE0_DROP_ON_MASK    0xFFF

#define    RTL8370_REG_FLOWCTRL_QUEUE1_DROP_ON    0x0201
#define    RTL8370_FLOWCTRL_QUEUE1_DROP_ON_OFFSET    0
#define    RTL8370_FLOWCTRL_QUEUE1_DROP_ON_MASK    0xFFF

#define    RTL8370_REG_FLOWCTRL_QUEUE2_DROP_ON    0x0202
#define    RTL8370_FLOWCTRL_QUEUE2_DROP_ON_OFFSET    0
#define    RTL8370_FLOWCTRL_QUEUE2_DROP_ON_MASK    0xFFF

#define    RTL8370_REG_FLOWCTRL_QUEUE3_DROP_ON    0x0203
#define    RTL8370_FLOWCTRL_QUEUE3_DROP_ON_OFFSET    0
#define    RTL8370_FLOWCTRL_QUEUE3_DROP_ON_MASK    0xFFF

#define    RTL8370_REG_FLOWCTRL_QUEUE4_DROP_ON    0x0204
#define    RTL8370_FLOWCTRL_QUEUE4_DROP_ON_OFFSET    0
#define    RTL8370_FLOWCTRL_QUEUE4_DROP_ON_MASK    0xFFF

#define    RTL8370_REG_FLOWCTRL_QUEUE5_DROP_ON    0x0205
#define    RTL8370_FLOWCTRL_QUEUE5_DROP_ON_OFFSET    0
#define    RTL8370_FLOWCTRL_QUEUE5_DROP_ON_MASK    0xFFF

#define    RTL8370_REG_FLOWCTRL_QUEUE6_DROP_ON    0x0206
#define    RTL8370_FLOWCTRL_QUEUE6_DROP_ON_OFFSET    0
#define    RTL8370_FLOWCTRL_QUEUE6_DROP_ON_MASK    0xFFF

#define    RTL8370_REG_FLOWCTRL_QUEUE7_DROP_ON    0x0207
#define    RTL8370_FLOWCTRL_QUEUE7_DROP_ON_OFFSET    0
#define    RTL8370_FLOWCTRL_QUEUE7_DROP_ON_MASK    0xFFF

#define    RTL8370_REG_FLOWCTRL_PORT0_DROP_ON    0x0208
#define    RTL8370_FLOWCTRL_PORT0_DROP_ON_OFFSET    0
#define    RTL8370_FLOWCTRL_PORT0_DROP_ON_MASK    0xFFF

#define    RTL8370_REG_FLOWCTRL_PORT1_DROP_ON    0x0209
#define    RTL8370_FLOWCTRL_PORT1_DROP_ON_OFFSET    0
#define    RTL8370_FLOWCTRL_PORT1_DROP_ON_MASK    0xFFF

#define    RTL8370_REG_FLOWCTRL_PORT2_DROP_ON    0x020a
#define    RTL8370_FLOWCTRL_PORT2_DROP_ON_OFFSET    0
#define    RTL8370_FLOWCTRL_PORT2_DROP_ON_MASK    0xFFF

#define    RTL8370_REG_FLOWCTRL_PORT3_DROP_ON    0x020b
#define    RTL8370_FLOWCTRL_PORT3_DROP_ON_OFFSET    0
#define    RTL8370_FLOWCTRL_PORT3_DROP_ON_MASK    0xFFF

#define    RTL8370_REG_FLOWCTRL_PORT4_DROP_ON    0x020c
#define    RTL8370_FLOWCTRL_PORT4_DROP_ON_OFFSET    0
#define    RTL8370_FLOWCTRL_PORT4_DROP_ON_MASK    0xFFF

#define    RTL8370_REG_FLOWCTRL_PORT5_DROP_ON    0x020d
#define    RTL8370_FLOWCTRL_PORT5_DROP_ON_OFFSET    0
#define    RTL8370_FLOWCTRL_PORT5_DROP_ON_MASK    0xFFF

#define    RTL8370_REG_FLOWCTRL_PORT6_DROP_ON    0x020e
#define    RTL8370_FLOWCTRL_PORT6_DROP_ON_OFFSET    0
#define    RTL8370_FLOWCTRL_PORT6_DROP_ON_MASK    0xFFF

#define    RTL8370_REG_FLOWCTRL_PORT7_DROP_ON    0x020f
#define    RTL8370_FLOWCTRL_PORT7_DROP_ON_OFFSET    0
#define    RTL8370_FLOWCTRL_PORT7_DROP_ON_MASK    0xFFF

#define    RTL8370_REG_FLOWCTRL_PORT8_DROP_ON    0x0210
#define    RTL8370_FLOWCTRL_PORT8_DROP_ON_OFFSET    0
#define    RTL8370_FLOWCTRL_PORT8_DROP_ON_MASK    0xFFF

#define    RTL8370_REG_FLOWCTRL_PORT9_DROP_ON    0x0211
#define    RTL8370_FLOWCTRL_PORT9_DROP_ON_OFFSET    0
#define    RTL8370_FLOWCTRL_PORT9_DROP_ON_MASK    0xFFF

#define    RTL8370_REG_FLOWCTRL_PORT10_DROP_ON    0x0212
#define    RTL8370_FLOWCTRL_PORT10_DROP_ON_OFFSET    0
#define    RTL8370_FLOWCTRL_PORT10_DROP_ON_MASK    0xFFF

#define    RTL8370_REG_FLOWCTRL_PORT11_DROP_ON    0x0213
#define    RTL8370_FLOWCTRL_PORT11_DROP_ON_OFFSET    0
#define    RTL8370_FLOWCTRL_PORT11_DROP_ON_MASK    0xFFF

#define    RTL8370_REG_FLOWCTRL_PORT12_DROP_ON    0x0214
#define    RTL8370_FLOWCTRL_PORT12_DROP_ON_OFFSET    0
#define    RTL8370_FLOWCTRL_PORT12_DROP_ON_MASK    0xFFF

#define    RTL8370_REG_FLOWCTRL_PORT13_DROP_ON    0x0215
#define    RTL8370_FLOWCTRL_PORT13_DROP_ON_OFFSET    0
#define    RTL8370_FLOWCTRL_PORT13_DROP_ON_MASK    0xFFF

#define    RTL8370_REG_FLOWCTRL_PORT14_DROP_ON    0x0216
#define    RTL8370_FLOWCTRL_PORT14_DROP_ON_OFFSET    0
#define    RTL8370_FLOWCTRL_PORT14_DROP_ON_MASK    0xFFF

#define    RTL8370_REG_FLOWCTRL_PORT15_DROP_ON    0x0217
#define    RTL8370_FLOWCTRL_PORT15_DROP_ON_OFFSET    0
#define    RTL8370_FLOWCTRL_PORT15_DROP_ON_MASK    0xFFF

#define    RTL8370_REG_FLOWCTRL_PORT_GAP    0x0218
#define    RTL8370_FLOWCTRL_PORT_GAP_OFFSET    0
#define    RTL8370_FLOWCTRL_PORT_GAP_MASK    0xFFF

#define    RTL8370_REG_FLOWCTRL_QUEUE_GAP    0x0219
#define    RTL8370_FLOWCTRL_QUEUE_GAP_OFFSET    0
#define    RTL8370_FLOWCTRL_QUEUE_GAP_MASK    0xFFF

#define    RTL8370_REG_PORT_QEMPTY    0x022d

#define    RTL8370_REG_FLOWCTRL_DEBUG_CRTL0    0x022e
#define    RTL8370_FLOWCTRL_DEBUG_CRTL0_OFFSET    0
#define    RTL8370_FLOWCTRL_DEBUG_CRTL0_MASK    0xF

#define    RTL8370_REG_FLOWCTRL_DEBUG_CRTL1    0x022f
#define    RTL8370_TOTAL_OFFSET    9
#define    RTL8370_TOTAL_MASK    0x200
#define    RTL8370_PORT_MAX_OFFSET    8
#define    RTL8370_PORT_MAX_MASK    0x100
#define    RTL8370_QMAX_MASK_OFFSET    0
#define    RTL8370_QMAX_MASK_MASK    0xFF

#define    RTL8370_REG_FLOWCTRL_QUEUE0_PAGE_COUNT    0x0230
#define    RTL8370_FLOWCTRL_QUEUE0_PAGE_COUNT_OFFSET    0
#define    RTL8370_FLOWCTRL_QUEUE0_PAGE_COUNT_MASK    0xFFF

#define    RTL8370_REG_FLOWCTRL_QUEUE1_PAGE_COUNT    0x0231
#define    RTL8370_FLOWCTRL_QUEUE1_PAGE_COUNT_OFFSET    0
#define    RTL8370_FLOWCTRL_QUEUE1_PAGE_COUNT_MASK    0xFFF

#define    RTL8370_REG_FLOWCTRL_QUEUE2_PAGE_COUNT    0x0232
#define    RTL8370_FLOWCTRL_QUEUE2_PAGE_COUNT_OFFSET    0
#define    RTL8370_FLOWCTRL_QUEUE2_PAGE_COUNT_MASK    0xFFF

#define    RTL8370_REG_FLOWCTRL_QUEUE3_PAGE_COUNT    0x0233
#define    RTL8370_FLOWCTRL_QUEUE3_PAGE_COUNT_OFFSET    0
#define    RTL8370_FLOWCTRL_QUEUE3_PAGE_COUNT_MASK    0xFFF

#define    RTL8370_REG_FLOWCTRL_QUEUE4_PAGE_COUNT    0x0234
#define    RTL8370_FLOWCTRL_QUEUE4_PAGE_COUNT_OFFSET    0
#define    RTL8370_FLOWCTRL_QUEUE4_PAGE_COUNT_MASK    0xFFF

#define    RTL8370_REG_FLOWCTRL_QUEUE5_PAGE_COUNT    0x0235
#define    RTL8370_FLOWCTRL_QUEUE5_PAGE_COUNT_OFFSET    0
#define    RTL8370_FLOWCTRL_QUEUE5_PAGE_COUNT_MASK    0xFFF

#define    RTL8370_REG_FLOWCTRL_QUEUE6_PAGE_COUNT    0x0236
#define    RTL8370_FLOWCTRL_QUEUE6_PAGE_COUNT_OFFSET    0
#define    RTL8370_FLOWCTRL_QUEUE6_PAGE_COUNT_MASK    0xFFF

#define    RTL8370_REG_FLOWCTRL_QUEUE7_PAGE_COUNT    0x0237
#define    RTL8370_FLOWCTRL_QUEUE7_PAGE_COUNT_OFFSET    0
#define    RTL8370_FLOWCTRL_QUEUE7_PAGE_COUNT_MASK    0xFFF

#define    RTL8370_REG_FLOWCTRL_PORT_PAGE_COUNT    0x0238
#define    RTL8370_FLOWCTRL_PORT_PAGE_COUNT_OFFSET    0
#define    RTL8370_FLOWCTRL_PORT_PAGE_COUNT_MASK    0xFFF

#define    RTL8370_REG_FLOWCTRL_QUEUE0_MAX_PAGE_COUNT    0x0239
#define    RTL8370_FLOWCTRL_QUEUE0_MAX_PAGE_COUNT_OFFSET    0
#define    RTL8370_FLOWCTRL_QUEUE0_MAX_PAGE_COUNT_MASK    0xFFF

#define    RTL8370_REG_FLOWCTRL_QUEUE1_MAX_PAGE_COUNT    0x023a
#define    RTL8370_FLOWCTRL_QUEUE1_MAX_PAGE_COUNT_OFFSET    0
#define    RTL8370_FLOWCTRL_QUEUE1_MAX_PAGE_COUNT_MASK    0xFFF

#define    RTL8370_REG_FLOWCTRL_QUEUE2_MAX_PAGE_COUNT    0x023b
#define    RTL8370_FLOWCTRL_QUEUE2_MAX_PAGE_COUNT_OFFSET    0
#define    RTL8370_FLOWCTRL_QUEUE2_MAX_PAGE_COUNT_MASK    0xFFF

#define    RTL8370_REG_FLOWCTRL_QUEUE3_MAX_PAGE_COUNT    0x023c
#define    RTL8370_FLOWCTRL_QUEUE3_MAX_PAGE_COUNT_OFFSET    0
#define    RTL8370_FLOWCTRL_QUEUE3_MAX_PAGE_COUNT_MASK    0xFFF

#define    RTL8370_REG_FLOWCTRL_QUEUE4_MAX_PAGE_COUNT    0x023d
#define    RTL8370_FLOWCTRL_QUEUE4_MAX_PAGE_COUNT_OFFSET    0
#define    RTL8370_FLOWCTRL_QUEUE4_MAX_PAGE_COUNT_MASK    0xFFF

#define    RTL8370_REG_FLOWCTRL_QUEUE5_MAX_PAGE_COUNT    0x023e
#define    RTL8370_FLOWCTRL_QUEUE5_MAX_PAGE_COUNT_OFFSET    0
#define    RTL8370_FLOWCTRL_QUEUE5_MAX_PAGE_COUNT_MASK    0xFFF

#define    RTL8370_REG_FLOWCTRL_QUEUE6_MAX_PAGE_COUNT    0x023f
#define    RTL8370_FLOWCTRL_QUEUE6_MAX_PAGE_COUNT_OFFSET    0
#define    RTL8370_FLOWCTRL_QUEUE6_MAX_PAGE_COUNT_MASK    0xFFF

#define    RTL8370_REG_FLOWCTRL_QUEUE7_MAX_PAGE_COUNT    0x0240
#define    RTL8370_FLOWCTRL_QUEUE7_MAX_PAGE_COUNT_OFFSET    0
#define    RTL8370_FLOWCTRL_QUEUE7_MAX_PAGE_COUNT_MASK    0xFFF

#define    RTL8370_REG_FLOWCTRL_PORT_MAX_PAGE_COUNT    0x0241
#define    RTL8370_FLOWCTRL_PORT_MAX_PAGE_COUNT_OFFSET    0
#define    RTL8370_FLOWCTRL_PORT_MAX_PAGE_COUNT_MASK    0xFFF

#define    RTL8370_REG_FLOWCTRL_TOTAL_PACKET_COUNT0    0x0242

#define    RTL8370_REG_FLOWCTRL_TOTAL_PACKET_COUNT1    0x0243

#define    RTL8370_REG_HIGH_QUEUE_MASK0    0x0244
#define    RTL8370_PORT1_HIGH_QUEUE_MASK_OFFSET    8
#define    RTL8370_PORT1_HIGH_QUEUE_MASK_MASK    0xFF00
#define    RTL8370_PORT0_HIGH_QUEUE_MASK_OFFSET    0
#define    RTL8370_PORT0_HIGH_QUEUE_MASK_MASK    0xFF

#define    RTL8370_REG_HIGH_QUEUE_MASK1    0x0245
#define    RTL8370_PORT3_HIGH_QUEUE_MASK_OFFSET    8
#define    RTL8370_PORT3_HIGH_QUEUE_MASK_MASK    0xFF00
#define    RTL8370_PORT2_HIGH_QUEUE_MASK_OFFSET    0
#define    RTL8370_PORT2_HIGH_QUEUE_MASK_MASK    0xFF

#define    RTL8370_REG_HIGH_QUEUE_MASK2    0x0246
#define    RTL8370_PORT5_HIGH_QUEUE_MASK_OFFSET    8
#define    RTL8370_PORT5_HIGH_QUEUE_MASK_MASK    0xFF00
#define    RTL8370_PORT4_HIGH_QUEUE_MASK_OFFSET    0
#define    RTL8370_PORT4_HIGH_QUEUE_MASK_MASK    0xFF

#define    RTL8370_REG_HIGH_QUEUE_MASK3    0x0247
#define    RTL8370_PORT7_HIGH_QUEUE_MASK_OFFSET    8
#define    RTL8370_PORT7_HIGH_QUEUE_MASK_MASK    0xFF00
#define    RTL8370_PORT6_HIGH_QUEUE_MASK_OFFSET    0
#define    RTL8370_PORT6_HIGH_QUEUE_MASK_MASK    0xFF

#define    RTL8370_REG_HIGH_QUEUE_MASK4    0x0248
#define    RTL8370_PORT9_HIGH_QUEUE_MASK_OFFSET    8
#define    RTL8370_PORT9_HIGH_QUEUE_MASK_MASK    0xFF00
#define    RTL8370_PORT8_HIGH_QUEUE_MASK_OFFSET    0
#define    RTL8370_PORT8_HIGH_QUEUE_MASK_MASK    0xFF

#define    RTL8370_REG_HIGH_QUEUE_MASK5    0x0249
#define    RTL8370_PORT11_HIGH_QUEUE_MASK_OFFSET    8
#define    RTL8370_PORT11_HIGH_QUEUE_MASK_MASK    0xFF00
#define    RTL8370_PORT10_HIGH_QUEUE_MASK_OFFSET    0
#define    RTL8370_PORT10_HIGH_QUEUE_MASK_MASK    0xFF

#define    RTL8370_REG_HIGH_QUEUE_MASK6    0x024a
#define    RTL8370_PORT13_HIGH_QUEUE_MASK_OFFSET    8
#define    RTL8370_PORT13_HIGH_QUEUE_MASK_MASK    0xFF00
#define    RTL8370_PORT12_HIGH_QUEUE_MASK_OFFSET    0
#define    RTL8370_PORT12_HIGH_QUEUE_MASK_MASK    0xFF

#define    RTL8370_REG_HIGH_QUEUE_MASK7    0x024b
#define    RTL8370_PORT15_HIGH_QUEUE_MASK_OFFSET    8
#define    RTL8370_PORT15_HIGH_QUEUE_MASK_MASK    0xFF00
#define    RTL8370_PORT14_HIGH_QUEUE_MASK_OFFSET    0
#define    RTL8370_PORT14_HIGH_QUEUE_MASK_MASK    0xFF

#define    RTL8370_REG_LOW_QUEUE_TH    0x024c
#define    RTL8370_LOW_QUEUE_TH_OFFSET    0
#define    RTL8370_LOW_QUEUE_TH_MASK    0xFFF

/* (16'h0300) sch_reg */

#define    RTL8370_REG_SCHEDULE_WFQ_CTRL    0x0300
#define    RTL8370_RETURN_TO_0_OFFSET    1
#define    RTL8370_RETURN_TO_0_MASK    0x2
#define    RTL8370_WFQ_IFG_OFFSET    0
#define    RTL8370_WFQ_IFG_MASK    0x1

#define    RTL8370_REG_SCHEDULE_WFQ_BURST_SIZE    0x0301

#define    RTL8370_REG_SCHEDULE_QUEUE_TYPE_CTRL0    0x0302
#define    RTL8370_PORT1_QUEUE7_TYPE_OFFSET    15
#define    RTL8370_PORT1_QUEUE7_TYPE_MASK    0x8000
#define    RTL8370_PORT1_QUEUE6_TYPE_OFFSET    14
#define    RTL8370_PORT1_QUEUE6_TYPE_MASK    0x4000
#define    RTL8370_PORT1_QUEUE5_TYPE_OFFSET    13
#define    RTL8370_PORT1_QUEUE5_TYPE_MASK    0x2000
#define    RTL8370_PORT1_QUEUE4_TYPE_OFFSET    12
#define    RTL8370_PORT1_QUEUE4_TYPE_MASK    0x1000
#define    RTL8370_PORT1_QUEUE3_TYPE_OFFSET    11
#define    RTL8370_PORT1_QUEUE3_TYPE_MASK    0x800
#define    RTL8370_PORT1_QUEUE2_TYPE_OFFSET    10
#define    RTL8370_PORT1_QUEUE2_TYPE_MASK    0x400
#define    RTL8370_PORT1_QUEUE1_TYPE_OFFSET    9
#define    RTL8370_PORT1_QUEUE1_TYPE_MASK    0x200
#define    RTL8370_PORT1_QUEUE0_TYPE_OFFSET    8
#define    RTL8370_PORT1_QUEUE0_TYPE_MASK    0x100
#define    RTL8370_PORT0_QUEUE7_TYPE_OFFSET    7
#define    RTL8370_PORT0_QUEUE7_TYPE_MASK    0x80
#define    RTL8370_PORT0_QUEUE6_TYPE_OFFSET    6
#define    RTL8370_PORT0_QUEUE6_TYPE_MASK    0x40
#define    RTL8370_PORT0_QUEUE5_TYPE_OFFSET    5
#define    RTL8370_PORT0_QUEUE5_TYPE_MASK    0x20
#define    RTL8370_PORT0_QUEUE4_TYPE_OFFSET    4
#define    RTL8370_PORT0_QUEUE4_TYPE_MASK    0x10
#define    RTL8370_PORT0_QUEUE3_TYPE_OFFSET    3
#define    RTL8370_PORT0_QUEUE3_TYPE_MASK    0x8
#define    RTL8370_PORT0_QUEUE2_TYPE_OFFSET    2
#define    RTL8370_PORT0_QUEUE2_TYPE_MASK    0x4
#define    RTL8370_PORT0_QUEUE1_TYPE_OFFSET    1
#define    RTL8370_PORT0_QUEUE1_TYPE_MASK    0x2
#define    RTL8370_PORT0_QUEUE0_TYPE_OFFSET    0
#define    RTL8370_PORT0_QUEUE0_TYPE_MASK    0x1

#define    RTL8370_REG_SCHEDULE_QUEUE_TYPE_CTRL1    0x0303
#define    RTL8370_PORT3_QUEUE7_TYPE_OFFSET    15
#define    RTL8370_PORT3_QUEUE7_TYPE_MASK    0x8000
#define    RTL8370_PORT3_QUEUE6_TYPE_OFFSET    14
#define    RTL8370_PORT3_QUEUE6_TYPE_MASK    0x4000
#define    RTL8370_PORT3_QUEUE5_TYPE_OFFSET    13
#define    RTL8370_PORT3_QUEUE5_TYPE_MASK    0x2000
#define    RTL8370_PORT3_QUEUE4_TYPE_OFFSET    12
#define    RTL8370_PORT3_QUEUE4_TYPE_MASK    0x1000
#define    RTL8370_PORT3_QUEUE3_TYPE_OFFSET    11
#define    RTL8370_PORT3_QUEUE3_TYPE_MASK    0x800
#define    RTL8370_PORT3_QUEUE2_TYPE_OFFSET    10
#define    RTL8370_PORT3_QUEUE2_TYPE_MASK    0x400
#define    RTL8370_PORT3_QUEUE1_TYPE_OFFSET    9
#define    RTL8370_PORT3_QUEUE1_TYPE_MASK    0x200
#define    RTL8370_PORT3_QUEUE0_TYPE_OFFSET    8
#define    RTL8370_PORT3_QUEUE0_TYPE_MASK    0x100
#define    RTL8370_PORT2_QUEUE7_TYPE_OFFSET    7
#define    RTL8370_PORT2_QUEUE7_TYPE_MASK    0x80
#define    RTL8370_PORT2_QUEUE6_TYPE_OFFSET    6
#define    RTL8370_PORT2_QUEUE6_TYPE_MASK    0x40
#define    RTL8370_PORT2_QUEUE5_TYPE_OFFSET    5
#define    RTL8370_PORT2_QUEUE5_TYPE_MASK    0x20
#define    RTL8370_PORT2_QUEUE4_TYPE_OFFSET    4
#define    RTL8370_PORT2_QUEUE4_TYPE_MASK    0x10
#define    RTL8370_PORT2_QUEUE3_TYPE_OFFSET    3
#define    RTL8370_PORT2_QUEUE3_TYPE_MASK    0x8
#define    RTL8370_PORT2_QUEUE2_TYPE_OFFSET    2
#define    RTL8370_PORT2_QUEUE2_TYPE_MASK    0x4
#define    RTL8370_PORT2_QUEUE1_TYPE_OFFSET    1
#define    RTL8370_PORT2_QUEUE1_TYPE_MASK    0x2
#define    RTL8370_PORT2_QUEUE0_TYPE_OFFSET    0
#define    RTL8370_PORT2_QUEUE0_TYPE_MASK    0x1

#define    RTL8370_REG_SCHEDULE_QUEUE_TYPE_CTRL2    0x0304
#define    RTL8370_PORT5_QUEUE7_TYPE_OFFSET    15
#define    RTL8370_PORT5_QUEUE7_TYPE_MASK    0x8000
#define    RTL8370_PORT5_QUEUE6_TYPE_OFFSET    14
#define    RTL8370_PORT5_QUEUE6_TYPE_MASK    0x4000
#define    RTL8370_PORT5_QUEUE5_TYPE_OFFSET    13
#define    RTL8370_PORT5_QUEUE5_TYPE_MASK    0x2000
#define    RTL8370_PORT5_QUEUE4_TYPE_OFFSET    12
#define    RTL8370_PORT5_QUEUE4_TYPE_MASK    0x1000
#define    RTL8370_PORT5_QUEUE3_TYPE_OFFSET    11
#define    RTL8370_PORT5_QUEUE3_TYPE_MASK    0x800
#define    RTL8370_PORT5_QUEUE2_TYPE_OFFSET    10
#define    RTL8370_PORT5_QUEUE2_TYPE_MASK    0x400
#define    RTL8370_PORT5_QUEUE1_TYPE_OFFSET    9
#define    RTL8370_PORT5_QUEUE1_TYPE_MASK    0x200
#define    RTL8370_PORT5_QUEUE0_TYPE_OFFSET    8
#define    RTL8370_PORT5_QUEUE0_TYPE_MASK    0x100
#define    RTL8370_PORT4_QUEUE7_TYPE_OFFSET    7
#define    RTL8370_PORT4_QUEUE7_TYPE_MASK    0x80
#define    RTL8370_PORT4_QUEUE6_TYPE_OFFSET    6
#define    RTL8370_PORT4_QUEUE6_TYPE_MASK    0x40
#define    RTL8370_PORT4_QUEUE5_TYPE_OFFSET    5
#define    RTL8370_PORT4_QUEUE5_TYPE_MASK    0x20
#define    RTL8370_PORT4_QUEUE4_TYPE_OFFSET    4
#define    RTL8370_PORT4_QUEUE4_TYPE_MASK    0x10
#define    RTL8370_PORT4_QUEUE3_TYPE_OFFSET    3
#define    RTL8370_PORT4_QUEUE3_TYPE_MASK    0x8
#define    RTL8370_PORT4_QUEUE2_TYPE_OFFSET    2
#define    RTL8370_PORT4_QUEUE2_TYPE_MASK    0x4
#define    RTL8370_PORT4_QUEUE1_TYPE_OFFSET    1
#define    RTL8370_PORT4_QUEUE1_TYPE_MASK    0x2
#define    RTL8370_PORT4_QUEUE0_TYPE_OFFSET    0
#define    RTL8370_PORT4_QUEUE0_TYPE_MASK    0x1

#define    RTL8370_REG_SCHEDULE_QUEUE_TYPE_CTRL3    0x0305
#define    RTL8370_PORT7_QUEUE7_TYPE_OFFSET    15
#define    RTL8370_PORT7_QUEUE7_TYPE_MASK    0x8000
#define    RTL8370_PORT7_QUEUE6_TYPE_OFFSET    14
#define    RTL8370_PORT7_QUEUE6_TYPE_MASK    0x4000
#define    RTL8370_PORT7_QUEUE5_TYPE_OFFSET    13
#define    RTL8370_PORT7_QUEUE5_TYPE_MASK    0x2000
#define    RTL8370_PORT7_QUEUE4_TYPE_OFFSET    12
#define    RTL8370_PORT7_QUEUE4_TYPE_MASK    0x1000
#define    RTL8370_PORT7_QUEUE3_TYPE_OFFSET    11
#define    RTL8370_PORT7_QUEUE3_TYPE_MASK    0x800
#define    RTL8370_PORT7_QUEUE2_TYPE_OFFSET    10
#define    RTL8370_PORT7_QUEUE2_TYPE_MASK    0x400
#define    RTL8370_PORT7_QUEUE1_TYPE_OFFSET    9
#define    RTL8370_PORT7_QUEUE1_TYPE_MASK    0x200
#define    RTL8370_PORT7_QUEUE0_TYPE_OFFSET    8
#define    RTL8370_PORT7_QUEUE0_TYPE_MASK    0x100
#define    RTL8370_PORT6_QUEUE7_TYPE_OFFSET    7
#define    RTL8370_PORT6_QUEUE7_TYPE_MASK    0x80
#define    RTL8370_PORT6_QUEUE6_TYPE_OFFSET    6
#define    RTL8370_PORT6_QUEUE6_TYPE_MASK    0x40
#define    RTL8370_PORT6_QUEUE5_TYPE_OFFSET    5
#define    RTL8370_PORT6_QUEUE5_TYPE_MASK    0x20
#define    RTL8370_PORT6_QUEUE4_TYPE_OFFSET    4
#define    RTL8370_PORT6_QUEUE4_TYPE_MASK    0x10
#define    RTL8370_PORT6_QUEUE3_TYPE_OFFSET    3
#define    RTL8370_PORT6_QUEUE3_TYPE_MASK    0x8
#define    RTL8370_PORT6_QUEUE2_TYPE_OFFSET    2
#define    RTL8370_PORT6_QUEUE2_TYPE_MASK    0x4
#define    RTL8370_PORT6_QUEUE1_TYPE_OFFSET    1
#define    RTL8370_PORT6_QUEUE1_TYPE_MASK    0x2
#define    RTL8370_PORT6_QUEUE0_TYPE_OFFSET    0
#define    RTL8370_PORT6_QUEUE0_TYPE_MASK    0x1

#define    RTL8370_REG_SCHEDULE_QUEUE_TYPE_CTRL4    0x0306
#define    RTL8370_PORT9_QUEUE7_TYPE_OFFSET    15
#define    RTL8370_PORT9_QUEUE7_TYPE_MASK    0x8000
#define    RTL8370_PORT9_QUEUE6_TYPE_OFFSET    14
#define    RTL8370_PORT9_QUEUE6_TYPE_MASK    0x4000
#define    RTL8370_PORT9_QUEUE5_TYPE_OFFSET    13
#define    RTL8370_PORT9_QUEUE5_TYPE_MASK    0x2000
#define    RTL8370_PORT9_QUEUE4_TYPE_OFFSET    12
#define    RTL8370_PORT9_QUEUE4_TYPE_MASK    0x1000
#define    RTL8370_PORT9_QUEUE3_TYPE_OFFSET    11
#define    RTL8370_PORT9_QUEUE3_TYPE_MASK    0x800
#define    RTL8370_PORT9_QUEUE2_TYPE_OFFSET    10
#define    RTL8370_PORT9_QUEUE2_TYPE_MASK    0x400
#define    RTL8370_PORT9_QUEUE1_TYPE_OFFSET    9
#define    RTL8370_PORT9_QUEUE1_TYPE_MASK    0x200
#define    RTL8370_PORT9_QUEUE0_TYPE_OFFSET    8
#define    RTL8370_PORT9_QUEUE0_TYPE_MASK    0x100
#define    RTL8370_PORT8_QUEUE7_TYPE_OFFSET    7
#define    RTL8370_PORT8_QUEUE7_TYPE_MASK    0x80
#define    RTL8370_PORT8_QUEUE6_TYPE_OFFSET    6
#define    RTL8370_PORT8_QUEUE6_TYPE_MASK    0x40
#define    RTL8370_PORT8_QUEUE5_TYPE_OFFSET    5
#define    RTL8370_PORT8_QUEUE5_TYPE_MASK    0x20
#define    RTL8370_PORT8_QUEUE4_TYPE_OFFSET    4
#define    RTL8370_PORT8_QUEUE4_TYPE_MASK    0x10
#define    RTL8370_PORT8_QUEUE3_TYPE_OFFSET    3
#define    RTL8370_PORT8_QUEUE3_TYPE_MASK    0x8
#define    RTL8370_PORT8_QUEUE2_TYPE_OFFSET    2
#define    RTL8370_PORT8_QUEUE2_TYPE_MASK    0x4
#define    RTL8370_PORT8_QUEUE1_TYPE_OFFSET    1
#define    RTL8370_PORT8_QUEUE1_TYPE_MASK    0x2
#define    RTL8370_PORT8_QUEUE0_TYPE_OFFSET    0
#define    RTL8370_PORT8_QUEUE0_TYPE_MASK    0x1

#define    RTL8370_REG_SCHEDULE_QUEUE_TYPE_CTRL5    0x0307
#define    RTL8370_PORT11_QUEUE7_TYPE_OFFSET    15
#define    RTL8370_PORT11_QUEUE7_TYPE_MASK    0x8000
#define    RTL8370_PORT11_QUEUE6_TYPE_OFFSET    14
#define    RTL8370_PORT11_QUEUE6_TYPE_MASK    0x4000
#define    RTL8370_PORT11_QUEUE5_TYPE_OFFSET    13
#define    RTL8370_PORT11_QUEUE5_TYPE_MASK    0x2000
#define    RTL8370_PORT11_QUEUE4_TYPE_OFFSET    12
#define    RTL8370_PORT11_QUEUE4_TYPE_MASK    0x1000
#define    RTL8370_PORT11_QUEUE3_TYPE_OFFSET    11
#define    RTL8370_PORT11_QUEUE3_TYPE_MASK    0x800
#define    RTL8370_PORT11_QUEUE2_TYPE_OFFSET    10
#define    RTL8370_PORT11_QUEUE2_TYPE_MASK    0x400
#define    RTL8370_PORT11_QUEUE1_TYPE_OFFSET    9
#define    RTL8370_PORT11_QUEUE1_TYPE_MASK    0x200
#define    RTL8370_PORT11_QUEUE0_TYPE_OFFSET    8
#define    RTL8370_PORT11_QUEUE0_TYPE_MASK    0x100
#define    RTL8370_PORT10_QUEUE7_TYPE_OFFSET    7
#define    RTL8370_PORT10_QUEUE7_TYPE_MASK    0x80
#define    RTL8370_PORT10_QUEUE6_TYPE_OFFSET    6
#define    RTL8370_PORT10_QUEUE6_TYPE_MASK    0x40
#define    RTL8370_PORT10_QUEUE5_TYPE_OFFSET    5
#define    RTL8370_PORT10_QUEUE5_TYPE_MASK    0x20
#define    RTL8370_PORT10_QUEUE4_TYPE_OFFSET    4
#define    RTL8370_PORT10_QUEUE4_TYPE_MASK    0x10
#define    RTL8370_PORT10_QUEUE3_TYPE_OFFSET    3
#define    RTL8370_PORT10_QUEUE3_TYPE_MASK    0x8
#define    RTL8370_PORT10_QUEUE2_TYPE_OFFSET    2
#define    RTL8370_PORT10_QUEUE2_TYPE_MASK    0x4
#define    RTL8370_PORT10_QUEUE1_TYPE_OFFSET    1
#define    RTL8370_PORT10_QUEUE1_TYPE_MASK    0x2
#define    RTL8370_PORT10_QUEUE0_TYPE_OFFSET    0
#define    RTL8370_PORT10_QUEUE0_TYPE_MASK    0x1

#define    RTL8370_REG_SCHEDULE_QUEUE_TYPE_CTRL6    0x0308
#define    RTL8370_PORT13_QUEUE7_TYPE_OFFSET    15
#define    RTL8370_PORT13_QUEUE7_TYPE_MASK    0x8000
#define    RTL8370_PORT13_QUEUE6_TYPE_OFFSET    14
#define    RTL8370_PORT13_QUEUE6_TYPE_MASK    0x4000
#define    RTL8370_PORT13_QUEUE5_TYPE_OFFSET    13
#define    RTL8370_PORT13_QUEUE5_TYPE_MASK    0x2000
#define    RTL8370_PORT13_QUEUE4_TYPE_OFFSET    12
#define    RTL8370_PORT13_QUEUE4_TYPE_MASK    0x1000
#define    RTL8370_PORT13_QUEUE3_TYPE_OFFSET    11
#define    RTL8370_PORT13_QUEUE3_TYPE_MASK    0x800
#define    RTL8370_PORT13_QUEUE2_TYPE_OFFSET    10
#define    RTL8370_PORT13_QUEUE2_TYPE_MASK    0x400
#define    RTL8370_PORT13_QUEUE1_TYPE_OFFSET    9
#define    RTL8370_PORT13_QUEUE1_TYPE_MASK    0x200
#define    RTL8370_PORT13_QUEUE0_TYPE_OFFSET    8
#define    RTL8370_PORT13_QUEUE0_TYPE_MASK    0x100
#define    RTL8370_PORT12_QUEUE7_TYPE_OFFSET    7
#define    RTL8370_PORT12_QUEUE7_TYPE_MASK    0x80
#define    RTL8370_PORT12_QUEUE6_TYPE_OFFSET    6
#define    RTL8370_PORT12_QUEUE6_TYPE_MASK    0x40
#define    RTL8370_PORT12_QUEUE5_TYPE_OFFSET    5
#define    RTL8370_PORT12_QUEUE5_TYPE_MASK    0x20
#define    RTL8370_PORT12_QUEUE4_TYPE_OFFSET    4
#define    RTL8370_PORT12_QUEUE4_TYPE_MASK    0x10
#define    RTL8370_PORT12_QUEUE3_TYPE_OFFSET    3
#define    RTL8370_PORT12_QUEUE3_TYPE_MASK    0x8
#define    RTL8370_PORT12_QUEUE2_TYPE_OFFSET    2
#define    RTL8370_PORT12_QUEUE2_TYPE_MASK    0x4
#define    RTL8370_PORT12_QUEUE1_TYPE_OFFSET    1
#define    RTL8370_PORT12_QUEUE1_TYPE_MASK    0x2
#define    RTL8370_PORT12_QUEUE0_TYPE_OFFSET    0
#define    RTL8370_PORT12_QUEUE0_TYPE_MASK    0x1

#define    RTL8370_REG_SCHEDULE_QUEUE_TYPE_CTRL7    0x0309
#define    RTL8370_PORT15_QUEUE7_TYPE_OFFSET    15
#define    RTL8370_PORT15_QUEUE7_TYPE_MASK    0x8000
#define    RTL8370_PORT15_QUEUE6_TYPE_OFFSET    14
#define    RTL8370_PORT15_QUEUE6_TYPE_MASK    0x4000
#define    RTL8370_PORT15_QUEUE5_TYPE_OFFSET    13
#define    RTL8370_PORT15_QUEUE5_TYPE_MASK    0x2000
#define    RTL8370_PORT15_QUEUE4_TYPE_OFFSET    12
#define    RTL8370_PORT15_QUEUE4_TYPE_MASK    0x1000
#define    RTL8370_PORT15_QUEUE3_TYPE_OFFSET    11
#define    RTL8370_PORT15_QUEUE3_TYPE_MASK    0x800
#define    RTL8370_PORT15_QUEUE2_TYPE_OFFSET    10
#define    RTL8370_PORT15_QUEUE2_TYPE_MASK    0x400
#define    RTL8370_PORT15_QUEUE1_TYPE_OFFSET    9
#define    RTL8370_PORT15_QUEUE1_TYPE_MASK    0x200
#define    RTL8370_PORT15_QUEUE0_TYPE_OFFSET    8
#define    RTL8370_PORT15_QUEUE0_TYPE_MASK    0x100
#define    RTL8370_PORT14_QUEUE7_TYPE_OFFSET    7
#define    RTL8370_PORT14_QUEUE7_TYPE_MASK    0x80
#define    RTL8370_PORT14_QUEUE6_TYPE_OFFSET    6
#define    RTL8370_PORT14_QUEUE6_TYPE_MASK    0x40
#define    RTL8370_PORT14_QUEUE5_TYPE_OFFSET    5
#define    RTL8370_PORT14_QUEUE5_TYPE_MASK    0x20
#define    RTL8370_PORT14_QUEUE4_TYPE_OFFSET    4
#define    RTL8370_PORT14_QUEUE4_TYPE_MASK    0x10
#define    RTL8370_PORT14_QUEUE3_TYPE_OFFSET    3
#define    RTL8370_PORT14_QUEUE3_TYPE_MASK    0x8
#define    RTL8370_PORT14_QUEUE2_TYPE_OFFSET    2
#define    RTL8370_PORT14_QUEUE2_TYPE_MASK    0x4
#define    RTL8370_PORT14_QUEUE1_TYPE_OFFSET    1
#define    RTL8370_PORT14_QUEUE1_TYPE_MASK    0x2
#define    RTL8370_PORT14_QUEUE0_TYPE_OFFSET    0
#define    RTL8370_PORT14_QUEUE0_TYPE_MASK    0x1

#define    RTL8370_REG_SCHEDULE_APR_CRTL0    0x030a
#define    RTL8370_PORT15_APR_ENABLE_OFFSET    15
#define    RTL8370_PORT15_APR_ENABLE_MASK    0x8000
#define    RTL8370_PORT14_APR_ENABLE_OFFSET    14
#define    RTL8370_PORT14_APR_ENABLE_MASK    0x4000
#define    RTL8370_PORT13_APR_ENABLE_OFFSET    13
#define    RTL8370_PORT13_APR_ENABLE_MASK    0x2000
#define    RTL8370_PORT12_APR_ENABLE_OFFSET    12
#define    RTL8370_PORT12_APR_ENABLE_MASK    0x1000
#define    RTL8370_PORT11_APR_ENABLE_OFFSET    11
#define    RTL8370_PORT11_APR_ENABLE_MASK    0x800
#define    RTL8370_PORT10_APR_ENABLE_OFFSET    10
#define    RTL8370_PORT10_APR_ENABLE_MASK    0x400
#define    RTL8370_PORT9_APR_ENABLE_OFFSET    9
#define    RTL8370_PORT9_APR_ENABLE_MASK    0x200
#define    RTL8370_PORT8_APR_ENABLE_OFFSET    8
#define    RTL8370_PORT8_APR_ENABLE_MASK    0x100
#define    RTL8370_PORT7_APR_ENABLE_OFFSET    7
#define    RTL8370_PORT7_APR_ENABLE_MASK    0x80
#define    RTL8370_PORT6_APR_ENABLE_OFFSET    6
#define    RTL8370_PORT6_APR_ENABLE_MASK    0x40
#define    RTL8370_PORT5_APR_ENABLE_OFFSET    5
#define    RTL8370_PORT5_APR_ENABLE_MASK    0x20
#define    RTL8370_PORT4_APR_ENABLE_OFFSET    4
#define    RTL8370_PORT4_APR_ENABLE_MASK    0x10
#define    RTL8370_PORT3_APR_ENABLE_OFFSET    3
#define    RTL8370_PORT3_APR_ENABLE_MASK    0x8
#define    RTL8370_PORT2_APR_ENABLE_OFFSET    2
#define    RTL8370_PORT2_APR_ENABLE_MASK    0x4
#define    RTL8370_PORT1_APR_ENABLE_OFFSET    1
#define    RTL8370_PORT1_APR_ENABLE_MASK    0x2
#define    RTL8370_PORT0_APR_ENABLE_OFFSET    0
#define    RTL8370_PORT0_APR_ENABLE_MASK    0x1

#define    RTL8370_REG_SCHEDULE_PORT0_QUEUE0_WFQ_WEIGHT    0x030c
#define    RTL8370_SCHEDULE_PORT0_QUEUE0_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT0_QUEUE0_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT0_QUEUE1_WFQ_WEIGHT    0x030d
#define    RTL8370_SCHEDULE_PORT0_QUEUE1_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT0_QUEUE1_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT0_QUEUE2_WFQ_WEIGHT    0x030e
#define    RTL8370_SCHEDULE_PORT0_QUEUE2_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT0_QUEUE2_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT0_QUEUE3_WFQ_WEIGHT    0x030f
#define    RTL8370_SCHEDULE_PORT0_QUEUE3_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT0_QUEUE3_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT0_QUEUE4_WFQ_WEIGHT    0x0310
#define    RTL8370_SCHEDULE_PORT0_QUEUE4_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT0_QUEUE4_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT0_QUEUE5_WFQ_WEIGHT    0x0311
#define    RTL8370_SCHEDULE_PORT0_QUEUE5_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT0_QUEUE5_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT0_QUEUE6_WFQ_WEIGHT    0x0312
#define    RTL8370_SCHEDULE_PORT0_QUEUE6_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT0_QUEUE6_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT0_QUEUE7_WFQ_WEIGHT    0x0313
#define    RTL8370_SCHEDULE_PORT0_QUEUE7_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT0_QUEUE7_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT1_QUEUE0_WFQ_WEIGHT    0x0314
#define    RTL8370_SCHEDULE_PORT1_QUEUE0_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT1_QUEUE0_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT1_QUEUE1_WFQ_WEIGHT    0x0315
#define    RTL8370_SCHEDULE_PORT1_QUEUE1_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT1_QUEUE1_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT1_QUEUE2_WFQ_WEIGHT    0x0316
#define    RTL8370_SCHEDULE_PORT1_QUEUE2_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT1_QUEUE2_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT1_QUEUE3_WFQ_WEIGHT    0x0317
#define    RTL8370_SCHEDULE_PORT1_QUEUE3_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT1_QUEUE3_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT1_QUEUE4_WFQ_WEIGHT    0x0318
#define    RTL8370_SCHEDULE_PORT1_QUEUE4_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT1_QUEUE4_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT1_QUEUE5_WFQ_WEIGHT    0x0319
#define    RTL8370_SCHEDULE_PORT1_QUEUE5_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT1_QUEUE5_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT1_QUEUE6_WFQ_WEIGHT    0x031a
#define    RTL8370_SCHEDULE_PORT1_QUEUE6_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT1_QUEUE6_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT1_QUEUE7_WFQ_WEIGHT    0x031b
#define    RTL8370_SCHEDULE_PORT1_QUEUE7_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT1_QUEUE7_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT2_QUEUE0_WFQ_WEIGHT    0x031c
#define    RTL8370_SCHEDULE_PORT2_QUEUE0_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT2_QUEUE0_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT2_QUEUE1_WFQ_WEIGHT    0x031d
#define    RTL8370_SCHEDULE_PORT2_QUEUE1_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT2_QUEUE1_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT2_QUEUE2_WFQ_WEIGHT    0x031e
#define    RTL8370_SCHEDULE_PORT2_QUEUE2_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT2_QUEUE2_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT2_QUEUE3_WFQ_WEIGHT    0x031f
#define    RTL8370_SCHEDULE_PORT2_QUEUE3_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT2_QUEUE3_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT2_QUEUE4_WFQ_WEIGHT    0x0320
#define    RTL8370_SCHEDULE_PORT2_QUEUE4_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT2_QUEUE4_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT2_QUEUE5_WFQ_WEIGHT    0x0321
#define    RTL8370_SCHEDULE_PORT2_QUEUE5_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT2_QUEUE5_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT2_QUEUE6_WFQ_WEIGHT    0x0322
#define    RTL8370_SCHEDULE_PORT2_QUEUE6_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT2_QUEUE6_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT2_QUEUE7_WFQ_WEIGHT    0x0323
#define    RTL8370_SCHEDULE_PORT2_QUEUE7_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT2_QUEUE7_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT3_QUEUE0_WFQ_WEIGHT    0x0324
#define    RTL8370_SCHEDULE_PORT3_QUEUE0_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT3_QUEUE0_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT3_QUEUE1_WFQ_WEIGHT    0x0325
#define    RTL8370_SCHEDULE_PORT3_QUEUE1_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT3_QUEUE1_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT3_QUEUE2_WFQ_WEIGHT    0x0326
#define    RTL8370_SCHEDULE_PORT3_QUEUE2_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT3_QUEUE2_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT3_QUEUE3_WFQ_WEIGHT    0x0327
#define    RTL8370_SCHEDULE_PORT3_QUEUE3_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT3_QUEUE3_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT3_QUEUE4_WFQ_WEIGHT    0x0328
#define    RTL8370_SCHEDULE_PORT3_QUEUE4_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT3_QUEUE4_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT3_QUEUE5_WFQ_WEIGHT    0x0329
#define    RTL8370_SCHEDULE_PORT3_QUEUE5_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT3_QUEUE5_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT3_QUEUE6_WFQ_WEIGHT    0x032a
#define    RTL8370_SCHEDULE_PORT3_QUEUE6_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT3_QUEUE6_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT3_QUEUE7_WFQ_WEIGHT    0x032b
#define    RTL8370_SCHEDULE_PORT3_QUEUE7_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT3_QUEUE7_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT4_QUEUE0_WFQ_WEIGHT    0x032c
#define    RTL8370_SCHEDULE_PORT4_QUEUE0_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT4_QUEUE0_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT4_QUEUE1_WFQ_WEIGHT    0x032d
#define    RTL8370_SCHEDULE_PORT4_QUEUE1_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT4_QUEUE1_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT4_QUEUE2_WFQ_WEIGHT    0x032e
#define    RTL8370_SCHEDULE_PORT4_QUEUE2_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT4_QUEUE2_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT4_QUEUE3_WFQ_WEIGHT    0x032f
#define    RTL8370_SCHEDULE_PORT4_QUEUE3_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT4_QUEUE3_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT4_QUEUE4_WFQ_WEIGHT    0x0330
#define    RTL8370_SCHEDULE_PORT4_QUEUE4_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT4_QUEUE4_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT4_QUEUE5_WFQ_WEIGHT    0x0331
#define    RTL8370_SCHEDULE_PORT4_QUEUE5_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT4_QUEUE5_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT4_QUEUE6_WFQ_WEIGHT    0x0332
#define    RTL8370_SCHEDULE_PORT4_QUEUE6_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT4_QUEUE6_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT4_QUEUE7_WFQ_WEIGHT    0x0333
#define    RTL8370_SCHEDULE_PORT4_QUEUE7_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT4_QUEUE7_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT5_QUEUE0_WFQ_WEIGHT    0x0334
#define    RTL8370_SCHEDULE_PORT5_QUEUE0_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT5_QUEUE0_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT5_QUEUE1_WFQ_WEIGHT    0x0335
#define    RTL8370_SCHEDULE_PORT5_QUEUE1_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT5_QUEUE1_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT5_QUEUE2_WFQ_WEIGHT    0x0336
#define    RTL8370_SCHEDULE_PORT5_QUEUE2_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT5_QUEUE2_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT5_QUEUE3_WFQ_WEIGHT    0x0337
#define    RTL8370_SCHEDULE_PORT5_QUEUE3_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT5_QUEUE3_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT5_QUEUE4_WFQ_WEIGHT    0x0338
#define    RTL8370_SCHEDULE_PORT5_QUEUE4_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT5_QUEUE4_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT5_QUEUE5_WFQ_WEIGHT    0x0339
#define    RTL8370_SCHEDULE_PORT5_QUEUE5_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT5_QUEUE5_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT5_QUEUE6_WFQ_WEIGHT    0x033a
#define    RTL8370_SCHEDULE_PORT5_QUEUE6_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT5_QUEUE6_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT5_QUEUE7_WFQ_WEIGHT    0x033b
#define    RTL8370_SCHEDULE_PORT5_QUEUE7_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT5_QUEUE7_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT6_QUEUE0_WFQ_WEIGHT    0x033c
#define    RTL8370_SCHEDULE_PORT6_QUEUE0_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT6_QUEUE0_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT6_QUEUE1_WFQ_WEIGHT    0x033d
#define    RTL8370_SCHEDULE_PORT6_QUEUE1_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT6_QUEUE1_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT6_QUEUE2_WFQ_WEIGHT    0x033e
#define    RTL8370_SCHEDULE_PORT6_QUEUE2_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT6_QUEUE2_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT6_QUEUE3_WFQ_WEIGHT    0x033f
#define    RTL8370_SCHEDULE_PORT6_QUEUE3_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT6_QUEUE3_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT6_QUEUE4_WFQ_WEIGHT    0x0340
#define    RTL8370_SCHEDULE_PORT6_QUEUE4_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT6_QUEUE4_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT6_QUEUE5_WFQ_WEIGHT    0x0341
#define    RTL8370_SCHEDULE_PORT6_QUEUE5_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT6_QUEUE5_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT6_QUEUE6_WFQ_WEIGHT    0x0342
#define    RTL8370_SCHEDULE_PORT6_QUEUE6_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT6_QUEUE6_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT6_QUEUE7_WFQ_WEIGHT    0x0343
#define    RTL8370_SCHEDULE_PORT6_QUEUE7_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT6_QUEUE7_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT7_QUEUE0_WFQ_WEIGHT    0x0344
#define    RTL8370_SCHEDULE_PORT7_QUEUE0_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT7_QUEUE0_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT7_QUEUE1_WFQ_WEIGHT    0x0345
#define    RTL8370_SCHEDULE_PORT7_QUEUE1_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT7_QUEUE1_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT7_QUEUE2_WFQ_WEIGHT    0x0346
#define    RTL8370_SCHEDULE_PORT7_QUEUE2_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT7_QUEUE2_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT7_QUEUE3_WFQ_WEIGHT    0x0347
#define    RTL8370_SCHEDULE_PORT7_QUEUE3_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT7_QUEUE3_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT7_QUEUE4_WFQ_WEIGHT    0x0348
#define    RTL8370_SCHEDULE_PORT7_QUEUE4_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT7_QUEUE4_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT7_QUEUE5_WFQ_WEIGHT    0x0349
#define    RTL8370_SCHEDULE_PORT7_QUEUE5_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT7_QUEUE5_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT7_QUEUE6_WFQ_WEIGHT    0x034a
#define    RTL8370_SCHEDULE_PORT7_QUEUE6_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT7_QUEUE6_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT7_QUEUE7_WFQ_WEIGHT    0x034b
#define    RTL8370_SCHEDULE_PORT7_QUEUE7_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT7_QUEUE7_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT8_QUEUE0_WFQ_WEIGHT    0x034c
#define    RTL8370_SCHEDULE_PORT8_QUEUE0_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT8_QUEUE0_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT8_QUEUE1_WFQ_WEIGHT    0x034d
#define    RTL8370_SCHEDULE_PORT8_QUEUE1_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT8_QUEUE1_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT8_QUEUE2_WFQ_WEIGHT    0x034e
#define    RTL8370_SCHEDULE_PORT8_QUEUE2_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT8_QUEUE2_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT8_QUEUE3_WFQ_WEIGHT    0x034f
#define    RTL8370_SCHEDULE_PORT8_QUEUE3_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT8_QUEUE3_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT8_QUEUE4_WFQ_WEIGHT    0x0350
#define    RTL8370_SCHEDULE_PORT8_QUEUE4_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT8_QUEUE4_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT8_QUEUE5_WFQ_WEIGHT    0x0351
#define    RTL8370_SCHEDULE_PORT8_QUEUE5_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT8_QUEUE5_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT8_QUEUE6_WFQ_WEIGHT    0x0352
#define    RTL8370_SCHEDULE_PORT8_QUEUE6_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT8_QUEUE6_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT8_QUEUE7_WFQ_WEIGHT    0x0353
#define    RTL8370_SCHEDULE_PORT8_QUEUE7_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT8_QUEUE7_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT9_QUEUE0_WFQ_WEIGHT    0x0354
#define    RTL8370_SCHEDULE_PORT9_QUEUE0_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT9_QUEUE0_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT9_QUEUE1_WFQ_WEIGHT    0x0355
#define    RTL8370_SCHEDULE_PORT9_QUEUE1_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT9_QUEUE1_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT9_QUEUE2_WFQ_WEIGHT    0x0356
#define    RTL8370_SCHEDULE_PORT9_QUEUE2_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT9_QUEUE2_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT9_QUEUE3_WFQ_WEIGHT    0x0357
#define    RTL8370_SCHEDULE_PORT9_QUEUE3_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT9_QUEUE3_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT9_QUEUE4_WFQ_WEIGHT    0x0358
#define    RTL8370_SCHEDULE_PORT9_QUEUE4_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT9_QUEUE4_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT9_QUEUE5_WFQ_WEIGHT    0x0359
#define    RTL8370_SCHEDULE_PORT9_QUEUE5_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT9_QUEUE5_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT9_QUEUE6_WFQ_WEIGHT    0x035a
#define    RTL8370_SCHEDULE_PORT9_QUEUE6_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT9_QUEUE6_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT9_QUEUE7_WFQ_WEIGHT    0x035b
#define    RTL8370_SCHEDULE_PORT9_QUEUE7_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT9_QUEUE7_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT10_QUEUE0_WFQ_WEIGHT    0x035c
#define    RTL8370_SCHEDULE_PORT10_QUEUE0_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT10_QUEUE0_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT10_QUEUE1_WFQ_WEIGHT    0x035d
#define    RTL8370_SCHEDULE_PORT10_QUEUE1_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT10_QUEUE1_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT10_QUEUE2_WFQ_WEIGHT    0x035e
#define    RTL8370_SCHEDULE_PORT10_QUEUE2_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT10_QUEUE2_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT10_QUEUE3_WFQ_WEIGHT    0x035f
#define    RTL8370_SCHEDULE_PORT10_QUEUE3_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT10_QUEUE3_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT10_QUEUE4_WFQ_WEIGHT    0x0360
#define    RTL8370_SCHEDULE_PORT10_QUEUE4_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT10_QUEUE4_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT10_QUEUE5_WFQ_WEIGHT    0x0361
#define    RTL8370_SCHEDULE_PORT10_QUEUE5_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT10_QUEUE5_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT10_QUEUE6_WFQ_WEIGHT    0x0362
#define    RTL8370_SCHEDULE_PORT10_QUEUE6_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT10_QUEUE6_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT10_QUEUE7_WFQ_WEIGHT    0x0363
#define    RTL8370_SCHEDULE_PORT10_QUEUE7_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT10_QUEUE7_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT11_QUEUE0_WFQ_WEIGHT    0x0364
#define    RTL8370_SCHEDULE_PORT11_QUEUE0_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT11_QUEUE0_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT11_QUEUE1_WFQ_WEIGHT    0x0365
#define    RTL8370_SCHEDULE_PORT11_QUEUE1_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT11_QUEUE1_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT11_QUEUE2_WFQ_WEIGHT    0x0366
#define    RTL8370_SCHEDULE_PORT11_QUEUE2_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT11_QUEUE2_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT11_QUEUE3_WFQ_WEIGHT    0x0367
#define    RTL8370_SCHEDULE_PORT11_QUEUE3_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT11_QUEUE3_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT11_QUEUE4_WFQ_WEIGHT    0x0368
#define    RTL8370_SCHEDULE_PORT11_QUEUE4_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT11_QUEUE4_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT11_QUEUE5_WFQ_WEIGHT    0x0369
#define    RTL8370_SCHEDULE_PORT11_QUEUE5_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT11_QUEUE5_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT11_QUEUE6_WFQ_WEIGHT    0x036a
#define    RTL8370_SCHEDULE_PORT11_QUEUE6_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT11_QUEUE6_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT11_QUEUE7_WFQ_WEIGHT    0x036b
#define    RTL8370_SCHEDULE_PORT11_QUEUE7_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT11_QUEUE7_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT12_QUEUE0_WFQ_WEIGHT    0x036c
#define    RTL8370_SCHEDULE_PORT12_QUEUE0_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT12_QUEUE0_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT12_QUEUE1_WFQ_WEIGHT    0x036d
#define    RTL8370_SCHEDULE_PORT12_QUEUE1_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT12_QUEUE1_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT12_QUEUE2_WFQ_WEIGHT    0x036e
#define    RTL8370_SCHEDULE_PORT12_QUEUE2_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT12_QUEUE2_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT12_QUEUE3_WFQ_WEIGHT    0x036f
#define    RTL8370_SCHEDULE_PORT12_QUEUE3_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT12_QUEUE3_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT12_QUEUE4_WFQ_WEIGHT    0x0370
#define    RTL8370_SCHEDULE_PORT12_QUEUE4_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT12_QUEUE4_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT12_QUEUE5_WFQ_WEIGHT    0x0371
#define    RTL8370_SCHEDULE_PORT12_QUEUE5_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT12_QUEUE5_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT12_QUEUE6_WFQ_WEIGHT    0x0372
#define    RTL8370_SCHEDULE_PORT12_QUEUE6_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT12_QUEUE6_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT12_QUEUE7_WFQ_WEIGHT    0x0373
#define    RTL8370_SCHEDULE_PORT12_QUEUE7_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT12_QUEUE7_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT13_QUEUE0_WFQ_WEIGHT    0x0374
#define    RTL8370_SCHEDULE_PORT13_QUEUE0_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT13_QUEUE0_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT13_QUEUE1_WFQ_WEIGHT    0x0375
#define    RTL8370_SCHEDULE_PORT13_QUEUE1_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT13_QUEUE1_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT13_QUEUE2_WFQ_WEIGHT    0x0376
#define    RTL8370_SCHEDULE_PORT13_QUEUE2_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT13_QUEUE2_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT13_QUEUE3_WFQ_WEIGHT    0x0377
#define    RTL8370_SCHEDULE_PORT13_QUEUE3_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT13_QUEUE3_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT13_QUEUE4_WFQ_WEIGHT    0x0378
#define    RTL8370_SCHEDULE_PORT13_QUEUE4_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT13_QUEUE4_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT13_QUEUE5_WFQ_WEIGHT    0x0379
#define    RTL8370_SCHEDULE_PORT13_QUEUE5_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT13_QUEUE5_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT13_QUEUE6_WFQ_WEIGHT    0x037a
#define    RTL8370_SCHEDULE_PORT13_QUEUE6_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT13_QUEUE6_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT13_QUEUE7_WFQ_WEIGHT    0x037b
#define    RTL8370_SCHEDULE_PORT13_QUEUE7_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT13_QUEUE7_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT14_QUEUE0_WFQ_WEIGHT    0x037c
#define    RTL8370_SCHEDULE_PORT14_QUEUE0_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT14_QUEUE0_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT14_QUEUE1_WFQ_WEIGHT    0x037d
#define    RTL8370_SCHEDULE_PORT14_QUEUE1_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT14_QUEUE1_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT14_QUEUE2_WFQ_WEIGHT    0x037e
#define    RTL8370_SCHEDULE_PORT14_QUEUE2_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT14_QUEUE2_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT14_QUEUE3_WFQ_WEIGHT    0x037f
#define    RTL8370_SCHEDULE_PORT14_QUEUE3_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT14_QUEUE3_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT14_QUEUE4_WFQ_WEIGHT    0x0380
#define    RTL8370_SCHEDULE_PORT14_QUEUE4_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT14_QUEUE4_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT14_QUEUE5_WFQ_WEIGHT    0x0381
#define    RTL8370_SCHEDULE_PORT14_QUEUE5_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT14_QUEUE5_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT14_QUEUE6_WFQ_WEIGHT    0x0382
#define    RTL8370_SCHEDULE_PORT14_QUEUE6_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT14_QUEUE6_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT14_QUEUE7_WFQ_WEIGHT    0x0383
#define    RTL8370_SCHEDULE_PORT14_QUEUE7_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT14_QUEUE7_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT15_QUEUE0_WFQ_WEIGHT    0x0384
#define    RTL8370_SCHEDULE_PORT15_QUEUE0_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT15_QUEUE0_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT15_QUEUE1_WFQ_WEIGHT    0x0385
#define    RTL8370_SCHEDULE_PORT15_QUEUE1_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT15_QUEUE1_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT15_QUEUE2_WFQ_WEIGHT    0x0386
#define    RTL8370_SCHEDULE_PORT15_QUEUE2_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT15_QUEUE2_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT15_QUEUE3_WFQ_WEIGHT    0x0387
#define    RTL8370_SCHEDULE_PORT15_QUEUE3_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT15_QUEUE3_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT15_QUEUE4_WFQ_WEIGHT    0x0388
#define    RTL8370_SCHEDULE_PORT15_QUEUE4_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT15_QUEUE4_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT15_QUEUE5_WFQ_WEIGHT    0x0389
#define    RTL8370_SCHEDULE_PORT15_QUEUE5_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT15_QUEUE5_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT15_QUEUE6_WFQ_WEIGHT    0x038a
#define    RTL8370_SCHEDULE_PORT15_QUEUE6_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT15_QUEUE6_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_SCHEDULE_PORT15_QUEUE7_WFQ_WEIGHT    0x038b
#define    RTL8370_SCHEDULE_PORT15_QUEUE7_WFQ_WEIGHT_OFFSET    0
#define    RTL8370_SCHEDULE_PORT15_QUEUE7_WFQ_WEIGHT_MASK    0x7F

#define    RTL8370_REG_PORT0_EGRESSBW_CTRL0    0x038c

#define    RTL8370_REG_PORT0_EGRESSBW_CTRL1    0x038d
#define    RTL8370_PORT0_EGRESSBW_CTRL1_OFFSET    0
#define    RTL8370_PORT0_EGRESSBW_CTRL1_MASK    0x1

#define    RTL8370_REG_PORT1_EGRESSBW_CTRL0    0x038e

#define    RTL8370_REG_PORT1_EGRESSBW_CTRL1    0x038f
#define    RTL8370_PORT1_EGRESSBW_CTRL1_OFFSET    0
#define    RTL8370_PORT1_EGRESSBW_CTRL1_MASK    0x1

#define    RTL8370_REG_PORT2_EGRESSBW_CTRL0    0x0390

#define    RTL8370_REG_PORT2_EGRESSBW_CTRL1    0x0391
#define    RTL8370_PORT2_EGRESSBW_CTRL1_OFFSET    0
#define    RTL8370_PORT2_EGRESSBW_CTRL1_MASK    0x1

#define    RTL8370_REG_PORT3_EGRESSBW_CTRL0    0x0392

#define    RTL8370_REG_PORT3_EGRESSBW_CTRL1    0x0393
#define    RTL8370_PORT3_EGRESSBW_CTRL1_OFFSET    0
#define    RTL8370_PORT3_EGRESSBW_CTRL1_MASK    0x1

#define    RTL8370_REG_PORT4_EGRESSBW_CTRL0    0x0394

#define    RTL8370_REG_PORT4_EGRESSBW_CTRL1    0x0395
#define    RTL8370_PORT4_EGRESSBW_CTRL1_OFFSET    0
#define    RTL8370_PORT4_EGRESSBW_CTRL1_MASK    0x1

#define    RTL8370_REG_PORT5_EGRESSBW_CTRL0    0x0396

#define    RTL8370_REG_PORT5_EGRESSBW_CTRL1    0x0397
#define    RTL8370_PORT5_EGRESSBW_CTRL1_OFFSET    0
#define    RTL8370_PORT5_EGRESSBW_CTRL1_MASK    0x1

#define    RTL8370_REG_PORT6_EGRESSBW_CTRL0    0x0398

#define    RTL8370_REG_PORT6_EGRESSBW_CTRL1    0x0399
#define    RTL8370_PORT6_EGRESSBW_CTRL1_OFFSET    0
#define    RTL8370_PORT6_EGRESSBW_CTRL1_MASK    0x1

#define    RTL8370_REG_PORT7_EGRESSBW_CTRL0    0x039a

#define    RTL8370_REG_PORT7_EGRESSBW_CTRL1    0x039b
#define    RTL8370_PORT7_EGRESSBW_CTRL1_OFFSET    0
#define    RTL8370_PORT7_EGRESSBW_CTRL1_MASK    0x1

#define    RTL8370_REG_PORT8_EGRESSBW_CTRL0    0x039c

#define    RTL8370_REG_PORT8_EGRESSBW_CTRL1    0x039d
#define    RTL8370_PORT8_EGRESSBW_CTRL1_OFFSET    0
#define    RTL8370_PORT8_EGRESSBW_CTRL1_MASK    0x1

#define    RTL8370_REG_PORT9_EGRESSBW_CTRL0    0x039e

#define    RTL8370_REG_PORT9_EGRESSBW_CTRL1    0x039f
#define    RTL8370_PORT9_EGRESSBW_CTRL1_OFFSET    0
#define    RTL8370_PORT9_EGRESSBW_CTRL1_MASK    0x1

#define    RTL8370_REG_PORT10_EGRESSBW_CTRL0    0x03a0

#define    RTL8370_REG_PORT10_EGRESSBW_CTRL1    0x03a1
#define    RTL8370_PORT10_EGRESSBW_CTRL1_OFFSET    0
#define    RTL8370_PORT10_EGRESSBW_CTRL1_MASK    0x1

#define    RTL8370_REG_PORT11_EGRESSBW_CTRL0    0x03a2

#define    RTL8370_REG_PORT11_EGRESSBW_CTRL1    0x03a3
#define    RTL8370_PORT11_EGRESSBW_CTRL1_OFFSET    0
#define    RTL8370_PORT11_EGRESSBW_CTRL1_MASK    0x1

#define    RTL8370_REG_PORT12_EGRESSBW_CTRL0    0x03a4

#define    RTL8370_REG_PORT12_EGRESSBW_CTRL1    0x03a5
#define    RTL8370_PORT12_EGRESSBW_CTRL1_OFFSET    0
#define    RTL8370_PORT12_EGRESSBW_CTRL1_MASK    0x1

#define    RTL8370_REG_PORT13_EGRESSBW_CTRL0    0x03a6

#define    RTL8370_REG_PORT13_EGRESSBW_CTRL1    0x03a7
#define    RTL8370_PORT13_EGRESSBW_CTRL1_OFFSET    0
#define    RTL8370_PORT13_EGRESSBW_CTRL1_MASK    0x1

#define    RTL8370_REG_PORT14_EGRESSBW_CTRL0    0x03a8

#define    RTL8370_REG_PORT14_EGRESSBW_CTRL1    0x03a9
#define    RTL8370_PORT14_EGRESSBW_CTRL1_OFFSET    0
#define    RTL8370_PORT14_EGRESSBW_CTRL1_MASK    0x1

#define    RTL8370_REG_PORT15_EGRESSBW_CTRL0    0x03aa

#define    RTL8370_REG_PORT15_EGRESSBW_CTRL1    0x03ab
#define    RTL8370_PORT15_EGRESSBW_CTRL1_OFFSET    0
#define    RTL8370_PORT15_EGRESSBW_CTRL1_MASK    0x1

#define    RTL8370_REG_SCHEDULE_PORT0_APR_METER_CTRL0    0x03ac
#define    RTL8370_PORT0_QUEUE4_APR_METER_OFFSET    12
#define    RTL8370_PORT0_QUEUE4_APR_METER_MASK    0x7000
#define    RTL8370_PORT0_QUEUE3_APR_METER_OFFSET    9
#define    RTL8370_PORT0_QUEUE3_APR_METER_MASK    0xE00
#define    RTL8370_PORT0_QUEUE2_APR_METER_OFFSET    6
#define    RTL8370_PORT0_QUEUE2_APR_METER_MASK    0x1C0
#define    RTL8370_PORT0_QUEUE1_APR_METER_OFFSET    3
#define    RTL8370_PORT0_QUEUE1_APR_METER_MASK    0x38
#define    RTL8370_PORT0_QUEUE0_APR_METER_OFFSET    0
#define    RTL8370_PORT0_QUEUE0_APR_METER_MASK    0x7

#define    RTL8370_REG_SCHEDULE_PORT0_APR_METER_CTRL1    0x03ad
#define    RTL8370_PORT0_QUEUE7_APR_METER_OFFSET    6
#define    RTL8370_PORT0_QUEUE7_APR_METER_MASK    0x1C0
#define    RTL8370_PORT0_QUEUE6_APR_METER_OFFSET    3
#define    RTL8370_PORT0_QUEUE6_APR_METER_MASK    0x38
#define    RTL8370_PORT0_QUEUE5_APR_METER_OFFSET    0
#define    RTL8370_PORT0_QUEUE5_APR_METER_MASK    0x7

#define    RTL8370_REG_SCHEDULE_PORT1_APR_METER_CTRL0    0x03b0
#define    RTL8370_PORT1_QUEUE4_APR_METER_OFFSET    12
#define    RTL8370_PORT1_QUEUE4_APR_METER_MASK    0x7000
#define    RTL8370_PORT1_QUEUE3_APR_METER_OFFSET    9
#define    RTL8370_PORT1_QUEUE3_APR_METER_MASK    0xE00
#define    RTL8370_PORT1_QUEUE2_APR_METER_OFFSET    6
#define    RTL8370_PORT1_QUEUE2_APR_METER_MASK    0x1C0
#define    RTL8370_PORT1_QUEUE1_APR_METER_OFFSET    3
#define    RTL8370_PORT1_QUEUE1_APR_METER_MASK    0x38
#define    RTL8370_PORT1_QUEUE0_APR_METER_OFFSET    0
#define    RTL8370_PORT1_QUEUE0_APR_METER_MASK    0x7

#define    RTL8370_REG_SCHEDULE_PORT1_APR_METER_CTRL1    0x03b1
#define    RTL8370_PORT1_QUEUE7_APR_METER_OFFSET    6
#define    RTL8370_PORT1_QUEUE7_APR_METER_MASK    0x1C0
#define    RTL8370_PORT1_QUEUE6_APR_METER_OFFSET    3
#define    RTL8370_PORT1_QUEUE6_APR_METER_MASK    0x38
#define    RTL8370_PORT1_QUEUE5_APR_METER_OFFSET    0
#define    RTL8370_PORT1_QUEUE5_APR_METER_MASK    0x7

#define    RTL8370_REG_SCHEDULE_PORT2_APR_METER_CTRL0    0x03b4
#define    RTL8370_PORT2_QUEUE4_APR_METER_OFFSET    12
#define    RTL8370_PORT2_QUEUE4_APR_METER_MASK    0x7000
#define    RTL8370_PORT2_QUEUE3_APR_METER_OFFSET    9
#define    RTL8370_PORT2_QUEUE3_APR_METER_MASK    0xE00
#define    RTL8370_PORT2_QUEUE2_APR_METER_OFFSET    6
#define    RTL8370_PORT2_QUEUE2_APR_METER_MASK    0x1C0
#define    RTL8370_PORT2_QUEUE1_APR_METER_OFFSET    3
#define    RTL8370_PORT2_QUEUE1_APR_METER_MASK    0x38
#define    RTL8370_PORT2_QUEUE0_APR_METER_OFFSET    0
#define    RTL8370_PORT2_QUEUE0_APR_METER_MASK    0x7

#define    RTL8370_REG_SCHEDULE_PORT2_APR_METER_CTRL1    0x03b5
#define    RTL8370_PORT2_QUEUE7_APR_METER_OFFSET    6
#define    RTL8370_PORT2_QUEUE7_APR_METER_MASK    0x1C0
#define    RTL8370_PORT2_QUEUE6_APR_METER_OFFSET    3
#define    RTL8370_PORT2_QUEUE6_APR_METER_MASK    0x38
#define    RTL8370_PORT2_QUEUE5_APR_METER_OFFSET    0
#define    RTL8370_PORT2_QUEUE5_APR_METER_MASK    0x7

#define    RTL8370_REG_SCHEDULE_PORT3_APR_METER_CTRL0    0x03b8
#define    RTL8370_PORT3_QUEUE4_APR_METER_OFFSET    12
#define    RTL8370_PORT3_QUEUE4_APR_METER_MASK    0x7000
#define    RTL8370_PORT3_QUEUE3_APR_METER_OFFSET    9
#define    RTL8370_PORT3_QUEUE3_APR_METER_MASK    0xE00
#define    RTL8370_PORT3_QUEUE2_APR_METER_OFFSET    6
#define    RTL8370_PORT3_QUEUE2_APR_METER_MASK    0x1C0
#define    RTL8370_PORT3_QUEUE1_APR_METER_OFFSET    3
#define    RTL8370_PORT3_QUEUE1_APR_METER_MASK    0x38
#define    RTL8370_PORT3_QUEUE0_APR_METER_OFFSET    0
#define    RTL8370_PORT3_QUEUE0_APR_METER_MASK    0x7

#define    RTL8370_REG_SCHEDULE_PORT3_APR_METER_CTRL1    0x03b9
#define    RTL8370_PORT3_QUEUE7_APR_METER_OFFSET    6
#define    RTL8370_PORT3_QUEUE7_APR_METER_MASK    0x1C0
#define    RTL8370_PORT3_QUEUE6_APR_METER_OFFSET    3
#define    RTL8370_PORT3_QUEUE6_APR_METER_MASK    0x38
#define    RTL8370_PORT3_QUEUE5_APR_METER_OFFSET    0
#define    RTL8370_PORT3_QUEUE5_APR_METER_MASK    0x7

#define    RTL8370_REG_SCHEDULE_PORT4_APR_METER_CTRL0    0x03bc
#define    RTL8370_PORT4_QUEUE4_APR_METER_OFFSET    12
#define    RTL8370_PORT4_QUEUE4_APR_METER_MASK    0x7000
#define    RTL8370_PORT4_QUEUE3_APR_METER_OFFSET    9
#define    RTL8370_PORT4_QUEUE3_APR_METER_MASK    0xE00
#define    RTL8370_PORT4_QUEUE2_APR_METER_OFFSET    6
#define    RTL8370_PORT4_QUEUE2_APR_METER_MASK    0x1C0
#define    RTL8370_PORT4_QUEUE1_APR_METER_OFFSET    3
#define    RTL8370_PORT4_QUEUE1_APR_METER_MASK    0x38
#define    RTL8370_PORT4_QUEUE0_APR_METER_OFFSET    0
#define    RTL8370_PORT4_QUEUE0_APR_METER_MASK    0x7

#define    RTL8370_REG_SCHEDULE_PORT4_APR_METER_CTRL1    0x03bd
#define    RTL8370_PORT4_QUEUE7_APR_METER_OFFSET    6
#define    RTL8370_PORT4_QUEUE7_APR_METER_MASK    0x1C0
#define    RTL8370_PORT4_QUEUE6_APR_METER_OFFSET    3
#define    RTL8370_PORT4_QUEUE6_APR_METER_MASK    0x38
#define    RTL8370_PORT4_QUEUE5_APR_METER_OFFSET    0
#define    RTL8370_PORT4_QUEUE5_APR_METER_MASK    0x7

#define    RTL8370_REG_SCHEDULE_PORT5_APR_METER_CTRL0    0x03c0
#define    RTL8370_PORT5_QUEUE4_APR_METER_OFFSET    12
#define    RTL8370_PORT5_QUEUE4_APR_METER_MASK    0x7000
#define    RTL8370_PORT5_QUEUE3_APR_METER_OFFSET    9
#define    RTL8370_PORT5_QUEUE3_APR_METER_MASK    0xE00
#define    RTL8370_PORT5_QUEUE2_APR_METER_OFFSET    6
#define    RTL8370_PORT5_QUEUE2_APR_METER_MASK    0x1C0
#define    RTL8370_PORT5_QUEUE1_APR_METER_OFFSET    3
#define    RTL8370_PORT5_QUEUE1_APR_METER_MASK    0x38
#define    RTL8370_PORT5_QUEUE0_APR_METER_OFFSET    0
#define    RTL8370_PORT5_QUEUE0_APR_METER_MASK    0x7

#define    RTL8370_REG_SCHEDULE_PORT5_APR_METER_CTRL1    0x03c1
#define    RTL8370_PORT5_QUEUE7_APR_METER_OFFSET    6
#define    RTL8370_PORT5_QUEUE7_APR_METER_MASK    0x1C0
#define    RTL8370_PORT5_QUEUE6_APR_METER_OFFSET    3
#define    RTL8370_PORT5_QUEUE6_APR_METER_MASK    0x38
#define    RTL8370_PORT5_QUEUE5_APR_METER_OFFSET    0
#define    RTL8370_PORT5_QUEUE5_APR_METER_MASK    0x7

#define    RTL8370_REG_SCHEDULE_PORT6_APR_METER_CTRL0    0x03c4
#define    RTL8370_PORT6_QUEUE4_APR_METER_OFFSET    12
#define    RTL8370_PORT6_QUEUE4_APR_METER_MASK    0x7000
#define    RTL8370_PORT6_QUEUE3_APR_METER_OFFSET    9
#define    RTL8370_PORT6_QUEUE3_APR_METER_MASK    0xE00
#define    RTL8370_PORT6_QUEUE2_APR_METER_OFFSET    6
#define    RTL8370_PORT6_QUEUE2_APR_METER_MASK    0x1C0
#define    RTL8370_PORT6_QUEUE1_APR_METER_OFFSET    3
#define    RTL8370_PORT6_QUEUE1_APR_METER_MASK    0x38
#define    RTL8370_PORT6_QUEUE0_APR_METER_OFFSET    0
#define    RTL8370_PORT6_QUEUE0_APR_METER_MASK    0x7

#define    RTL8370_REG_SCHEDULE_PORT6_APR_METER_CTRL1    0x03c5
#define    RTL8370_PORT6_QUEUE7_APR_METER_OFFSET    6
#define    RTL8370_PORT6_QUEUE7_APR_METER_MASK    0x1C0
#define    RTL8370_PORT6_QUEUE6_APR_METER_OFFSET    3
#define    RTL8370_PORT6_QUEUE6_APR_METER_MASK    0x38
#define    RTL8370_PORT6_QUEUE5_APR_METER_OFFSET    0
#define    RTL8370_PORT6_QUEUE5_APR_METER_MASK    0x7

#define    RTL8370_REG_SCHEDULE_PORT7_APR_METER_CTRL0    0x03c8
#define    RTL8370_PORT7_QUEUE4_APR_METER_OFFSET    12
#define    RTL8370_PORT7_QUEUE4_APR_METER_MASK    0x7000
#define    RTL8370_PORT7_QUEUE3_APR_METER_OFFSET    9
#define    RTL8370_PORT7_QUEUE3_APR_METER_MASK    0xE00
#define    RTL8370_PORT7_QUEUE2_APR_METER_OFFSET    6
#define    RTL8370_PORT7_QUEUE2_APR_METER_MASK    0x1C0
#define    RTL8370_PORT7_QUEUE1_APR_METER_OFFSET    3
#define    RTL8370_PORT7_QUEUE1_APR_METER_MASK    0x38
#define    RTL8370_PORT7_QUEUE0_APR_METER_OFFSET    0
#define    RTL8370_PORT7_QUEUE0_APR_METER_MASK    0x7

#define    RTL8370_REG_SCHEDULE_PORT7_APR_METER_CTRL1    0x03c9
#define    RTL8370_PORT7_QUEUE7_APR_METER_OFFSET    6
#define    RTL8370_PORT7_QUEUE7_APR_METER_MASK    0x1C0
#define    RTL8370_PORT7_QUEUE6_APR_METER_OFFSET    3
#define    RTL8370_PORT7_QUEUE6_APR_METER_MASK    0x38
#define    RTL8370_PORT7_QUEUE5_APR_METER_OFFSET    0
#define    RTL8370_PORT7_QUEUE5_APR_METER_MASK    0x7

#define    RTL8370_REG_SCHEDULE_PORT8_APR_METER_CTRL0    0x03cc
#define    RTL8370_PORT8_QUEUE4_APR_METER_OFFSET    12
#define    RTL8370_PORT8_QUEUE4_APR_METER_MASK    0x7000
#define    RTL8370_PORT8_QUEUE3_APR_METER_OFFSET    9
#define    RTL8370_PORT8_QUEUE3_APR_METER_MASK    0xE00
#define    RTL8370_PORT8_QUEUE2_APR_METER_OFFSET    6
#define    RTL8370_PORT8_QUEUE2_APR_METER_MASK    0x1C0
#define    RTL8370_PORT8_QUEUE1_APR_METER_OFFSET    3
#define    RTL8370_PORT8_QUEUE1_APR_METER_MASK    0x38
#define    RTL8370_PORT8_QUEUE0_APR_METER_OFFSET    0
#define    RTL8370_PORT8_QUEUE0_APR_METER_MASK    0x7

#define    RTL8370_REG_SCHEDULE_PORT8_APR_METER_CTRL1    0x03cd
#define    RTL8370_PORT8_QUEUE7_APR_METER_OFFSET    6
#define    RTL8370_PORT8_QUEUE7_APR_METER_MASK    0x1C0
#define    RTL8370_PORT8_QUEUE6_APR_METER_OFFSET    3
#define    RTL8370_PORT8_QUEUE6_APR_METER_MASK    0x38
#define    RTL8370_PORT8_QUEUE5_APR_METER_OFFSET    0
#define    RTL8370_PORT8_QUEUE5_APR_METER_MASK    0x7

#define    RTL8370_REG_SCHEDULE_PORT9_APR_METER_CTRL0    0x03d0
#define    RTL8370_PORT9_QUEUE4_APR_METER_OFFSET    12
#define    RTL8370_PORT9_QUEUE4_APR_METER_MASK    0x7000
#define    RTL8370_PORT9_QUEUE3_APR_METER_OFFSET    9
#define    RTL8370_PORT9_QUEUE3_APR_METER_MASK    0xE00
#define    RTL8370_PORT9_QUEUE2_APR_METER_OFFSET    6
#define    RTL8370_PORT9_QUEUE2_APR_METER_MASK    0x1C0
#define    RTL8370_PORT9_QUEUE1_APR_METER_OFFSET    3
#define    RTL8370_PORT9_QUEUE1_APR_METER_MASK    0x38
#define    RTL8370_PORT9_QUEUE0_APR_METER_OFFSET    0
#define    RTL8370_PORT9_QUEUE0_APR_METER_MASK    0x7

#define    RTL8370_REG_SCHEDULE_PORT9_APR_METER_CTRL1    0x03d1
#define    RTL8370_PORT9_QUEUE7_APR_METER_OFFSET    6
#define    RTL8370_PORT9_QUEUE7_APR_METER_MASK    0x1C0
#define    RTL8370_PORT9_QUEUE6_APR_METER_OFFSET    3
#define    RTL8370_PORT9_QUEUE6_APR_METER_MASK    0x38
#define    RTL8370_PORT9_QUEUE5_APR_METER_OFFSET    0
#define    RTL8370_PORT9_QUEUE5_APR_METER_MASK    0x7

#define    RTL8370_REG_SCHEDULE_PORT10_APR_METER_CTRL0    0x03d4
#define    RTL8370_PORT10_QUEUE4_APR_METER_OFFSET    12
#define    RTL8370_PORT10_QUEUE4_APR_METER_MASK    0x7000
#define    RTL8370_PORT10_QUEUE3_APR_METER_OFFSET    9
#define    RTL8370_PORT10_QUEUE3_APR_METER_MASK    0xE00
#define    RTL8370_PORT10_QUEUE2_APR_METER_OFFSET    6
#define    RTL8370_PORT10_QUEUE2_APR_METER_MASK    0x1C0
#define    RTL8370_PORT10_QUEUE1_APR_METER_OFFSET    3
#define    RTL8370_PORT10_QUEUE1_APR_METER_MASK    0x38
#define    RTL8370_PORT10_QUEUE0_APR_METER_OFFSET    0
#define    RTL8370_PORT10_QUEUE0_APR_METER_MASK    0x7

#define    RTL8370_REG_SCHEDULE_PORT10_APR_METER_CTRL1    0x03d5
#define    RTL8370_PORT10_QUEUE7_APR_METER_OFFSET    6
#define    RTL8370_PORT10_QUEUE7_APR_METER_MASK    0x1C0
#define    RTL8370_PORT10_QUEUE6_APR_METER_OFFSET    3
#define    RTL8370_PORT10_QUEUE6_APR_METER_MASK    0x38
#define    RTL8370_PORT10_QUEUE5_APR_METER_OFFSET    0
#define    RTL8370_PORT10_QUEUE5_APR_METER_MASK    0x7

#define    RTL8370_REG_SCHEDULE_PORT11_APR_METER_CTRL0    0x03d8
#define    RTL8370_PORT11_QUEUE4_APR_METER_OFFSET    12
#define    RTL8370_PORT11_QUEUE4_APR_METER_MASK    0x7000
#define    RTL8370_PORT11_QUEUE3_APR_METER_OFFSET    9
#define    RTL8370_PORT11_QUEUE3_APR_METER_MASK    0xE00
#define    RTL8370_PORT11_QUEUE2_APR_METER_OFFSET    6
#define    RTL8370_PORT11_QUEUE2_APR_METER_MASK    0x1C0
#define    RTL8370_PORT11_QUEUE1_APR_METER_OFFSET    3
#define    RTL8370_PORT11_QUEUE1_APR_METER_MASK    0x38
#define    RTL8370_PORT11_QUEUE0_APR_METER_OFFSET    0
#define    RTL8370_PORT11_QUEUE0_APR_METER_MASK    0x7

#define    RTL8370_REG_SCHEDULE_PORT11_APR_METER_CTRL1    0x03d9
#define    RTL8370_PORT11_QUEUE7_APR_METER_OFFSET    6
#define    RTL8370_PORT11_QUEUE7_APR_METER_MASK    0x1C0
#define    RTL8370_PORT11_QUEUE6_APR_METER_OFFSET    3
#define    RTL8370_PORT11_QUEUE6_APR_METER_MASK    0x38
#define    RTL8370_PORT11_QUEUE5_APR_METER_OFFSET    0
#define    RTL8370_PORT11_QUEUE5_APR_METER_MASK    0x7

#define    RTL8370_REG_SCHEDULE_PORT12_APR_METER_CTRL0    0x03dc
#define    RTL8370_PORT12_QUEUE4_APR_METER_OFFSET    12
#define    RTL8370_PORT12_QUEUE4_APR_METER_MASK    0x7000
#define    RTL8370_PORT12_QUEUE3_APR_METER_OFFSET    9
#define    RTL8370_PORT12_QUEUE3_APR_METER_MASK    0xE00
#define    RTL8370_PORT12_QUEUE2_APR_METER_OFFSET    6
#define    RTL8370_PORT12_QUEUE2_APR_METER_MASK    0x1C0
#define    RTL8370_PORT12_QUEUE1_APR_METER_OFFSET    3
#define    RTL8370_PORT12_QUEUE1_APR_METER_MASK    0x38
#define    RTL8370_PORT12_QUEUE0_APR_METER_OFFSET    0
#define    RTL8370_PORT12_QUEUE0_APR_METER_MASK    0x7

#define    RTL8370_REG_SCHEDULE_PORT12_APR_METER_CTRL1    0x03dd
#define    RTL8370_PORT12_QUEUE7_APR_METER_OFFSET    6
#define    RTL8370_PORT12_QUEUE7_APR_METER_MASK    0x1C0
#define    RTL8370_PORT12_QUEUE6_APR_METER_OFFSET    3
#define    RTL8370_PORT12_QUEUE6_APR_METER_MASK    0x38
#define    RTL8370_PORT12_QUEUE5_APR_METER_OFFSET    0
#define    RTL8370_PORT12_QUEUE5_APR_METER_MASK    0x7

#define    RTL8370_REG_SCHEDULE_PORT13_APR_METER_CTRL0    0x03e0
#define    RTL8370_PORT13_QUEUE4_APR_METER_OFFSET    12
#define    RTL8370_PORT13_QUEUE4_APR_METER_MASK    0x7000
#define    RTL8370_PORT13_QUEUE3_APR_METER_OFFSET    9
#define    RTL8370_PORT13_QUEUE3_APR_METER_MASK    0xE00
#define    RTL8370_PORT13_QUEUE2_APR_METER_OFFSET    6
#define    RTL8370_PORT13_QUEUE2_APR_METER_MASK    0x1C0
#define    RTL8370_PORT13_QUEUE1_APR_METER_OFFSET    3
#define    RTL8370_PORT13_QUEUE1_APR_METER_MASK    0x38
#define    RTL8370_PORT13_QUEUE0_APR_METER_OFFSET    0
#define    RTL8370_PORT13_QUEUE0_APR_METER_MASK    0x7

#define    RTL8370_REG_SCHEDULE_PORT13_APR_METER_CTRL1    0x03e1
#define    RTL8370_PORT13_QUEUE7_APR_METER_OFFSET    6
#define    RTL8370_PORT13_QUEUE7_APR_METER_MASK    0x1C0
#define    RTL8370_PORT13_QUEUE6_APR_METER_OFFSET    3
#define    RTL8370_PORT13_QUEUE6_APR_METER_MASK    0x38
#define    RTL8370_PORT13_QUEUE5_APR_METER_OFFSET    0
#define    RTL8370_PORT13_QUEUE5_APR_METER_MASK    0x7

#define    RTL8370_REG_SCHEDULE_PORT14_APR_METER_CTRL0    0x03e4
#define    RTL8370_PORT14_QUEUE4_APR_METER_OFFSET    12
#define    RTL8370_PORT14_QUEUE4_APR_METER_MASK    0x7000
#define    RTL8370_PORT14_QUEUE3_APR_METER_OFFSET    9
#define    RTL8370_PORT14_QUEUE3_APR_METER_MASK    0xE00
#define    RTL8370_PORT14_QUEUE2_APR_METER_OFFSET    6
#define    RTL8370_PORT14_QUEUE2_APR_METER_MASK    0x1C0
#define    RTL8370_PORT14_QUEUE1_APR_METER_OFFSET    3
#define    RTL8370_PORT14_QUEUE1_APR_METER_MASK    0x38
#define    RTL8370_PORT14_QUEUE0_APR_METER_OFFSET    0
#define    RTL8370_PORT14_QUEUE0_APR_METER_MASK    0x7

#define    RTL8370_REG_SCHEDULE_PORT14_APR_METER_CTRL1    0x03e5
#define    RTL8370_PORT14_QUEUE7_APR_METER_OFFSET    6
#define    RTL8370_PORT14_QUEUE7_APR_METER_MASK    0x1C0
#define    RTL8370_PORT14_QUEUE6_APR_METER_OFFSET    3
#define    RTL8370_PORT14_QUEUE6_APR_METER_MASK    0x38
#define    RTL8370_PORT14_QUEUE5_APR_METER_OFFSET    0
#define    RTL8370_PORT14_QUEUE5_APR_METER_MASK    0x7

#define    RTL8370_REG_SCHEDULE_PORT15_APR_METER_CTRL0    0x03e8
#define    RTL8370_PORT15_QUEUE4_APR_METER_OFFSET    12
#define    RTL8370_PORT15_QUEUE4_APR_METER_MASK    0x7000
#define    RTL8370_PORT15_QUEUE3_APR_METER_OFFSET    9
#define    RTL8370_PORT15_QUEUE3_APR_METER_MASK    0xE00
#define    RTL8370_PORT15_QUEUE2_APR_METER_OFFSET    6
#define    RTL8370_PORT15_QUEUE2_APR_METER_MASK    0x1C0
#define    RTL8370_PORT15_QUEUE1_APR_METER_OFFSET    3
#define    RTL8370_PORT15_QUEUE1_APR_METER_MASK    0x38
#define    RTL8370_PORT15_QUEUE0_APR_METER_OFFSET    0
#define    RTL8370_PORT15_QUEUE0_APR_METER_MASK    0x7

#define    RTL8370_REG_SCHEDULE_PORT15_APR_METER_CTRL1    0x03e9
#define    RTL8370_PORT15_QUEUE7_APR_METER_OFFSET    6
#define    RTL8370_PORT15_QUEUE7_APR_METER_MASK    0x1C0
#define    RTL8370_PORT15_QUEUE6_APR_METER_OFFSET    3
#define    RTL8370_PORT15_QUEUE6_APR_METER_MASK    0x38
#define    RTL8370_PORT15_QUEUE5_APR_METER_OFFSET    0
#define    RTL8370_PORT15_QUEUE5_APR_METER_MASK    0x7

#define    RTL8370_REG_LINE_RATE_1G_L    0x03ec

#define    RTL8370_REG_LINE_RATE_1G_H    0x03ed

#define    RTL8370_REG_LINE_RATE_100_L    0x03ee

#define    RTL8370_REG_LINE_RATE_100_H    0x03ef

#define    RTL8370_REG_LINE_RATE_10_L    0x03f0

#define    RTL8370_REG_LINE_RATE_10_H    0x03f1

#define    RTL8370_REG_BYPASS_LINE_RATE    0x03f7

/* (16'h0500) table_reg */

#define    RTL8370_REG_TABLE_ACCESS_CTRL    0x0500
#define    RTL8370_ACCESS_STATUS_OFFSET    12
#define    RTL8370_ACCESS_STATUS_MASK    0x1000
#define    RTL8370_ACCESS_METHOD_OFFSET    5
#define    RTL8370_ACCESS_METHOD_MASK    0x20
#define    RTL8370_COMMAND_TYPE_OFFSET    4
#define    RTL8370_COMMAND_TYPE_MASK    0x10
#define    RTL8370_TABLE_TYPE_OFFSET    0
#define    RTL8370_TABLE_TYPE_MASK    0x7

#define    RTL8370_REG_TABLE_ACCESS_ADDR    0x0501
#define    RTL8370_TABLE_ACCESS_ADDR_OFFSET    0
#define    RTL8370_TABLE_ACCESS_ADDR_MASK    0x3FFF

#define    RTL8370_REG_TABLE_LUT_ADDR    0x0502
#define    RTL8370_HIT_STATUS_OFFSET    14
#define    RTL8370_HIT_STATUS_MASK    0x4000
#define    RTL8370_TYPE_OFFSET    13
#define    RTL8370_TYPE_MASK    0x2000
#define    RTL8370_TABLE_LUT_ADDR_ADDRESS_OFFSET    0
#define    RTL8370_TABLE_LUT_ADDR_ADDRESS_MASK    0x1FFF

#define    RTL8370_REG_TABLE_ACCESS_DATA0    0x0503

#define    RTL8370_REG_TABLE_ACCESS_DATA1    0x0504

#define    RTL8370_REG_TABLE_ACCESS_DATA2    0x0505

#define    RTL8370_REG_TABLE_ACCESS_DATA3    0x0506

#define    RTL8370_REG_TABLE_ACCESS_DATA4    0x0507

#define    RTL8370_REG_TABLE_ACCESS_DATA5    0x0508

#define    RTL8370_REG_TABLE_ACCESS_DATA6    0x0509

#define    RTL8370_REG_TABLE_ACCESS_DATA7    0x050A

#define    RTL8370_REG_TABLE_ACCESS_DATA8    0x050B

#define    RTL8370_REG_TABLE_ACCESS_DATA9    0x050C

#define    RTL8370_REG_TABLE_ACCESS_DATA10    0x050D

#define    RTL8370_REG_TABLE_ACCESS_DATA11    0x050E

#define    RTL8370_REG_TABLE_ACCESS_DATA12    0x050F

#define    RTL8370_REG_TABLE_ACCESS_DATA13    0x0510

#define    RTL8370_REG_TABLE_ACCESS_DATA14    0x0511

#define    RTL8370_REG_TABLE_ACCESS_DATA15    0x0512

#define    RTL8370_REG_TABLE_ACCESS_DATA16    0x0513

#define    RTL8370_REG_TABLE_ACCESS_DATA17    0x0514

#define    RTL8370_REG_TABLE_ACCESS_DATA18    0x0515

#define    RTL8370_REG_TABLE_ACCESS_DATA19    0x0516

#define    RTL8370_REG_TABLE_ACCESS_DATA20    0x0517

#define    RTL8370_REG_TABLE_ACCESS_DATA21    0x0518

#define    RTL8370_REG_TABLE_ACCESS_DATA22    0x0519

#define    RTL8370_REG_TABLE_ACCESS_DATA23    0x051A

#define    RTL8370_REG_TABLE_ACCESS_DATA24    0x051B

#define    RTL8370_REG_TABLE_ACCESS_DATA25    0x051C

#define    RTL8370_REG_TABLE_ACCESS_DATA26    0x051D

#define    RTL8370_REG_TABLE_ACCESS_DATA27    0x051E

#define    RTL8370_REG_TABLE_ACCESS_DATA28    0x051F

#define    RTL8370_REG_TABLE_ACCESS_DATA29    0x0520

#define    RTL8370_REG_TABLE_ACCESS_DATA30    0x0521

#define    RTL8370_REG_TABLE_ACCESS_DATA31    0x0522

#define    RTL8370_REG_TABLE_ACCESS_DATA32    0x0523

#define    RTL8370_REG_TABLE_ACCESS_DATA33    0x0524

#define    RTL8370_REG_TABLE_ACCESS_DATA34    0x0525

/* (16'h0600) acl_reg */

#define    RTL8370_REG_ACL_RULE_TEMPLATE0_CRTL0    0x0600
#define    RTL8370_ACL_TEMPLATE0_FIELD1_OFFSET    8
#define    RTL8370_ACL_TEMPLATE0_FIELD1_MASK    0x3F00
#define    RTL8370_ACL_TEMPLATE0_FIELD0_OFFSET    0
#define    RTL8370_ACL_TEMPLATE0_FIELD0_MASK    0x3F

#define    RTL8370_REG_ACL_RULE_TEMPLATE0_CRTL1    0x0601
#define    RTL8370_ACL_TEMPLATE0_FIELD3_OFFSET    8
#define    RTL8370_ACL_TEMPLATE0_FIELD3_MASK    0x3F00
#define    RTL8370_ACL_TEMPLATE0_FIELD2_OFFSET    0
#define    RTL8370_ACL_TEMPLATE0_FIELD2_MASK    0x3F

#define    RTL8370_REG_ACL_RULE_TEMPLATE0_CRTL2    0x0602
#define    RTL8370_ACL_TEMPLATE0_FIELD5_OFFSET    8
#define    RTL8370_ACL_TEMPLATE0_FIELD5_MASK    0x3F00
#define    RTL8370_ACL_TEMPLATE0_FIELD4_OFFSET    0
#define    RTL8370_ACL_TEMPLATE0_FIELD4_MASK    0x3F

#define    RTL8370_REG_ACL_RULE_TEMPLATE0_CRTL3    0x0603
#define    RTL8370_ACL_RULE_TEMPLATE0_CRTL3_OFFSET    0
#define    RTL8370_ACL_RULE_TEMPLATE0_CRTL3_MASK    0x3F

#define    RTL8370_REG_ACL_RULE_TEMPLATE1_CRTL0    0x0604
#define    RTL8370_ACL_TEMPLATE1_FIELD1_OFFSET    8
#define    RTL8370_ACL_TEMPLATE1_FIELD1_MASK    0x3F00
#define    RTL8370_ACL_TEMPLATE1_FIELD0_OFFSET    0
#define    RTL8370_ACL_TEMPLATE1_FIELD0_MASK    0x3F

#define    RTL8370_REG_ACL_RULE_TEMPLATE1_CRTL1    0x0605
#define    RTL8370_ACL_TEMPLATE1_FIELD3_OFFSET    8
#define    RTL8370_ACL_TEMPLATE1_FIELD3_MASK    0x3F00
#define    RTL8370_ACL_TEMPLATE1_FIELD2_OFFSET    0
#define    RTL8370_ACL_TEMPLATE1_FIELD2_MASK    0x3F

#define    RTL8370_REG_ACL_RULE_TEMPLATE1_CRTL2    0x0606
#define    RTL8370_ACL_TEMPLATE1_FIELD5_OFFSET    8
#define    RTL8370_ACL_TEMPLATE1_FIELD5_MASK    0x3F00
#define    RTL8370_ACL_TEMPLATE1_FIELD4_OFFSET    0
#define    RTL8370_ACL_TEMPLATE1_FIELD4_MASK    0x3F

#define    RTL8370_REG_ACL_RULE_TEMPLATE1_CRTL3    0x0607
#define    RTL8370_ACL_RULE_TEMPLATE1_CRTL3_OFFSET    0
#define    RTL8370_ACL_RULE_TEMPLATE1_CRTL3_MASK    0x3F

#define    RTL8370_REG_ACL_RULE_TEMPLATE2_CRTL0    0x0608
#define    RTL8370_ACL_TEMPLATE2_FIELD1_OFFSET    8
#define    RTL8370_ACL_TEMPLATE2_FIELD1_MASK    0x3F00
#define    RTL8370_ACL_TEMPLATE2_FIELD0_OFFSET    0
#define    RTL8370_ACL_TEMPLATE2_FIELD0_MASK    0x3F

#define    RTL8370_REG_ACL_RULE_TEMPLATE2_CRTL1    0x0609
#define    RTL8370_ACL_TEMPLATE2_FIELD3_OFFSET    8
#define    RTL8370_ACL_TEMPLATE2_FIELD3_MASK    0x3F00
#define    RTL8370_ACL_TEMPLATE2_FIELD2_OFFSET    0
#define    RTL8370_ACL_TEMPLATE2_FIELD2_MASK    0x3F

#define    RTL8370_REG_ACL_RULE_TEMPLATE2_CRTL2    0x060a
#define    RTL8370_ACL_TEMPLATE2_FIELD5_OFFSET    8
#define    RTL8370_ACL_TEMPLATE2_FIELD5_MASK    0x3F00
#define    RTL8370_ACL_TEMPLATE2_FIELD4_OFFSET    0
#define    RTL8370_ACL_TEMPLATE2_FIELD4_MASK    0x3F

#define    RTL8370_REG_ACL_RULE_TEMPLATE2_CRTL3    0x060b
#define    RTL8370_ACL_RULE_TEMPLATE2_CRTL3_OFFSET    0
#define    RTL8370_ACL_RULE_TEMPLATE2_CRTL3_MASK    0x3F

#define    RTL8370_REG_ACL_RULE_TEMPLATE3_CRTL0    0x060c
#define    RTL8370_ACL_TEMPLATE3_FIELD1_OFFSET    8
#define    RTL8370_ACL_TEMPLATE3_FIELD1_MASK    0x3F00
#define    RTL8370_ACL_TEMPLATE3_FIELD0_OFFSET    0
#define    RTL8370_ACL_TEMPLATE3_FIELD0_MASK    0x3F

#define    RTL8370_REG_ACL_RULE_TEMPLATE3_CRTL1    0x060d
#define    RTL8370_ACL_TEMPLATE3_FIELD3_OFFSET    8
#define    RTL8370_ACL_TEMPLATE3_FIELD3_MASK    0x3F00
#define    RTL8370_ACL_TEMPLATE3_FIELD2_OFFSET    0
#define    RTL8370_ACL_TEMPLATE3_FIELD2_MASK    0x3F

#define    RTL8370_REG_ACL_RULE_TEMPLATE3_CRTL2    0x060e
#define    RTL8370_ACL_TEMPLATE3_FIELD5_OFFSET    8
#define    RTL8370_ACL_TEMPLATE3_FIELD5_MASK    0x3F00
#define    RTL8370_ACL_TEMPLATE3_FIELD4_OFFSET    0
#define    RTL8370_ACL_TEMPLATE3_FIELD4_MASK    0x3F

#define    RTL8370_REG_ACL_RULE_TEMPLATE3_CRTL3    0x060f
#define    RTL8370_ACL_RULE_TEMPLATE3_CRTL3_OFFSET    0
#define    RTL8370_ACL_RULE_TEMPLATE3_CRTL3_MASK    0x3F

#define    RTL8370_REG_ACL_RULE_TEMPLATE4_CRTL0    0x0610
#define    RTL8370_ACL_TEMPLATE4_FIELD1_OFFSET    8
#define    RTL8370_ACL_TEMPLATE4_FIELD1_MASK    0x3F00
#define    RTL8370_ACL_TEMPLATE4_FIELD0_OFFSET    0
#define    RTL8370_ACL_TEMPLATE4_FIELD0_MASK    0x3F

#define    RTL8370_REG_ACL_RULE_TEMPLATE4_CRTL1    0x0611
#define    RTL8370_ACL_TEMPLATE4_FIELD3_OFFSET    8
#define    RTL8370_ACL_TEMPLATE4_FIELD3_MASK    0x3F00
#define    RTL8370_ACL_TEMPLATE4_FIELD2_OFFSET    0
#define    RTL8370_ACL_TEMPLATE4_FIELD2_MASK    0x3F

#define    RTL8370_REG_ACL_RULE_TEMPLATE4_CRTL2    0x0612
#define    RTL8370_ACL_TEMPLATE4_FIELD5_OFFSET    8
#define    RTL8370_ACL_TEMPLATE4_FIELD5_MASK    0x3F00
#define    RTL8370_ACL_TEMPLATE4_FIELD4_OFFSET    0
#define    RTL8370_ACL_TEMPLATE4_FIELD4_MASK    0x3F

#define    RTL8370_REG_ACL_RULE_TEMPLATE4_CRTL3    0x0613
#define    RTL8370_ACL_RULE_TEMPLATE4_CRTL3_OFFSET    0
#define    RTL8370_ACL_RULE_TEMPLATE4_CRTL3_MASK    0x3F

#define    RTL8370_REG_ACL_RULE_TEMPLATE5_CRTL0    0x0614
#define    RTL8370_ACL_TEMPLATE5_FIELD1_OFFSET    8
#define    RTL8370_ACL_TEMPLATE5_FIELD1_MASK    0x3F00
#define    RTL8370_ACL_TEMPLATE5_FIELD0_OFFSET    0
#define    RTL8370_ACL_TEMPLATE5_FIELD0_MASK    0x3F

#define    RTL8370_REG_ACL_RULE_TEMPLATE5_CRTL1    0x0615
#define    RTL8370_ACL_TEMPLATE5_FIELD3_OFFSET    8
#define    RTL8370_ACL_TEMPLATE5_FIELD3_MASK    0x3F00
#define    RTL8370_ACL_TEMPLATE5_FIELD2_OFFSET    0
#define    RTL8370_ACL_TEMPLATE5_FIELD2_MASK    0x3F

#define    RTL8370_REG_ACL_RULE_TEMPLATE5_CRTL2    0x0616
#define    RTL8370_ACL_TEMPLATE5_FIELD5_OFFSET    8
#define    RTL8370_ACL_TEMPLATE5_FIELD5_MASK    0x3F00
#define    RTL8370_ACL_TEMPLATE5_FIELD4_OFFSET    0
#define    RTL8370_ACL_TEMPLATE5_FIELD4_MASK    0x3F

#define    RTL8370_REG_ACL_RULE_TEMPLATE5_CRTL3    0x0617
#define    RTL8370_ACL_RULE_TEMPLATE5_CRTL3_OFFSET    0
#define    RTL8370_ACL_RULE_TEMPLATE5_CRTL3_MASK    0x3F

#define    RTL8370_REG_ACL_RULE_TEMPLATE6_CRTL0    0x0618
#define    RTL8370_ACL_TEMPLATE6_FIELD1_OFFSET    8
#define    RTL8370_ACL_TEMPLATE6_FIELD1_MASK    0x3F00
#define    RTL8370_ACL_TEMPLATE6_FIELD0_OFFSET    0
#define    RTL8370_ACL_TEMPLATE6_FIELD0_MASK    0x3F

#define    RTL8370_REG_ACL_RULE_TEMPLATE6_CRTL1    0x0619
#define    RTL8370_ACL_TEMPLATE6_FIELD3_OFFSET    8
#define    RTL8370_ACL_TEMPLATE6_FIELD3_MASK    0x3F00
#define    RTL8370_ACL_TEMPLATE6_FIELD2_OFFSET    0
#define    RTL8370_ACL_TEMPLATE6_FIELD2_MASK    0x3F

#define    RTL8370_REG_ACL_RULE_TEMPLATE6_CRTL2    0x061a
#define    RTL8370_ACL_TEMPLATE6_FIELD5_OFFSET    8
#define    RTL8370_ACL_TEMPLATE6_FIELD5_MASK    0x3F00
#define    RTL8370_ACL_TEMPLATE6_FIELD4_OFFSET    0
#define    RTL8370_ACL_TEMPLATE6_FIELD4_MASK    0x3F

#define    RTL8370_REG_ACL_RULE_TEMPLATE6_CRTL3    0x061b
#define    RTL8370_ACL_RULE_TEMPLATE6_CRTL3_OFFSET    0
#define    RTL8370_ACL_RULE_TEMPLATE6_CRTL3_MASK    0x3F

#define    RTL8370_REG_ACL_RULE_TEMPLATE7_CRTL0    0x061c
#define    RTL8370_ACL_TEMPLATE7_FIELD1_OFFSET    8
#define    RTL8370_ACL_TEMPLATE7_FIELD1_MASK    0x3F00
#define    RTL8370_ACL_TEMPLATE7_FIELD0_OFFSET    0
#define    RTL8370_ACL_TEMPLATE7_FIELD0_MASK    0x3F

#define    RTL8370_REG_ACL_RULE_TEMPLATE7_CRTL1    0x061d
#define    RTL8370_ACL_TEMPLATE7_FIELD3_OFFSET    8
#define    RTL8370_ACL_TEMPLATE7_FIELD3_MASK    0x3F00
#define    RTL8370_ACL_TEMPLATE7_FIELD2_OFFSET    0
#define    RTL8370_ACL_TEMPLATE7_FIELD2_MASK    0x3F

#define    RTL8370_REG_ACL_RULE_TEMPLATE7_CRTL2    0x061e
#define    RTL8370_ACL_TEMPLATE7_FIELD5_OFFSET    8
#define    RTL8370_ACL_TEMPLATE7_FIELD5_MASK    0x3F00
#define    RTL8370_ACL_TEMPLATE7_FIELD4_OFFSET    0
#define    RTL8370_ACL_TEMPLATE7_FIELD4_MASK    0x3F

#define    RTL8370_REG_ACL_RULE_TEMPLATE7_CRTL3    0x061f
#define    RTL8370_ACL_RULE_TEMPLATE7_CRTL3_OFFSET    0
#define    RTL8370_ACL_RULE_TEMPLATE7_CRTL3_MASK    0x3F

#define    RTL8370_REG_ACL_RULE_TEMPLATE8_CRTL0    0x0620
#define    RTL8370_ACL_TEMPLATE8_FIELD1_OFFSET    8
#define    RTL8370_ACL_TEMPLATE8_FIELD1_MASK    0x3F00
#define    RTL8370_ACL_TEMPLATE8_FIELD0_OFFSET    0
#define    RTL8370_ACL_TEMPLATE8_FIELD0_MASK    0x3F

#define    RTL8370_REG_ACL_RULE_TEMPLATE8_CRTL1    0x0621
#define    RTL8370_ACL_TEMPLATE8_FIELD3_OFFSET    8
#define    RTL8370_ACL_TEMPLATE8_FIELD3_MASK    0x3F00
#define    RTL8370_ACL_TEMPLATE8_FIELD2_OFFSET    0
#define    RTL8370_ACL_TEMPLATE8_FIELD2_MASK    0x3F

#define    RTL8370_REG_ACL_RULE_TEMPLATE8_CRTL2    0x0622
#define    RTL8370_ACL_TEMPLATE8_FIELD5_OFFSET    8
#define    RTL8370_ACL_TEMPLATE8_FIELD5_MASK    0x3F00
#define    RTL8370_ACL_TEMPLATE8_FIELD4_OFFSET    0
#define    RTL8370_ACL_TEMPLATE8_FIELD4_MASK    0x3F

#define    RTL8370_REG_ACL_RULE_TEMPLATE8_CRTL3    0x0623
#define    RTL8370_ACL_RULE_TEMPLATE8_CRTL3_OFFSET    0
#define    RTL8370_ACL_RULE_TEMPLATE8_CRTL3_MASK    0x3F

#define    RTL8370_REG_ACL_RULE_TEMPLATE9_CRTL0    0x0624
#define    RTL8370_ACL_TEMPLATE9_FIELD1_OFFSET    8
#define    RTL8370_ACL_TEMPLATE9_FIELD1_MASK    0x3F00
#define    RTL8370_ACL_TEMPLATE9_FIELD0_OFFSET    0
#define    RTL8370_ACL_TEMPLATE9_FIELD0_MASK    0x3F

#define    RTL8370_REG_ACL_RULE_TEMPLATE9_CRTL1    0x0625
#define    RTL8370_ACL_TEMPLATE9_FIELD3_OFFSET    8
#define    RTL8370_ACL_TEMPLATE9_FIELD3_MASK    0x3F00
#define    RTL8370_ACL_TEMPLATE9_FIELD2_OFFSET    0
#define    RTL8370_ACL_TEMPLATE9_FIELD2_MASK    0x3F

#define    RTL8370_REG_ACL_RULE_TEMPLATE9_CRTL2    0x0626
#define    RTL8370_ACL_TEMPLATE9_FIELD5_OFFSET    8
#define    RTL8370_ACL_TEMPLATE9_FIELD5_MASK    0x3F00
#define    RTL8370_ACL_TEMPLATE9_FIELD4_OFFSET    0
#define    RTL8370_ACL_TEMPLATE9_FIELD4_MASK    0x3F

#define    RTL8370_REG_ACL_RULE_TEMPLATE9_CRTL3    0x0627
#define    RTL8370_ACL_RULE_TEMPLATE9_CRTL3_OFFSET    0
#define    RTL8370_ACL_RULE_TEMPLATE9_CRTL3_MASK    0x3F

#define    RTL8370_REG_ACL_ACTION_CTRL0    0x0628
#define    RTL8370_ACL_OP1_NOT_OFFSET    13
#define    RTL8370_ACL_OP1_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT1_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT1_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT1_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT1_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT1_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT1_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT1_SVID_OFFSET    9
#define    RTL8370_ACL_ACT1_SVID_MASK    0x200
#define    RTL8370_ACL_ACT1_CVID_OFFSET    8
#define    RTL8370_ACL_ACT1_CVID_MASK    0x100
#define    RTL8370_ACL_OP0_NOT_OFFSET    5
#define    RTL8370_ACL_OP0_NOT_MASK    0x20
#define    RTL8370_ACL_ACT0_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT0_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT0_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT0_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT0_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT0_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT0_SVID_OFFSET    1
#define    RTL8370_ACL_ACT0_SVID_MASK    0x2
#define    RTL8370_ACL_ACT0_CVID_OFFSET    0
#define    RTL8370_ACL_ACT0_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL1    0x0629
#define    RTL8370_ACL_OP3_NOT_OFFSET    13
#define    RTL8370_ACL_OP3_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT3_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT3_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT3_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT3_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT3_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT3_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT3_SVID_OFFSET    9
#define    RTL8370_ACL_ACT3_SVID_MASK    0x200
#define    RTL8370_ACL_ACT3_CVID_OFFSET    8
#define    RTL8370_ACL_ACT3_CVID_MASK    0x100
#define    RTL8370_ACL_OP2_NOT_OFFSET    5
#define    RTL8370_ACL_OP2_NOT_MASK    0x20
#define    RTL8370_ACL_ACT2_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT2_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT2_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT2_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT2_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT2_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT2_SVID_OFFSET    1
#define    RTL8370_ACL_ACT2_SVID_MASK    0x2
#define    RTL8370_ACL_ACT2_CVID_OFFSET    0
#define    RTL8370_ACL_ACT2_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL2    0x062a
#define    RTL8370_ACL_OP5_NOT_OFFSET    13
#define    RTL8370_ACL_OP5_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT5_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT5_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT5_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT5_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT5_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT5_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT5_SVID_OFFSET    9
#define    RTL8370_ACL_ACT5_SVID_MASK    0x200
#define    RTL8370_ACL_ACT5_CVID_OFFSET    8
#define    RTL8370_ACL_ACT5_CVID_MASK    0x100
#define    RTL8370_ACL_OP4_NOT_OFFSET    5
#define    RTL8370_ACL_OP4_NOT_MASK    0x20
#define    RTL8370_ACL_ACT4_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT4_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT4_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT4_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT4_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT4_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT4_SVID_OFFSET    1
#define    RTL8370_ACL_ACT4_SVID_MASK    0x2
#define    RTL8370_ACL_ACT4_CVID_OFFSET    0
#define    RTL8370_ACL_ACT4_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL3    0x062b
#define    RTL8370_ACL_OP7_NOT_OFFSET    13
#define    RTL8370_ACL_OP7_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT7_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT7_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT7_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT7_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT7_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT7_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT7_SVID_OFFSET    9
#define    RTL8370_ACL_ACT7_SVID_MASK    0x200
#define    RTL8370_ACL_ACT7_CVID_OFFSET    8
#define    RTL8370_ACL_ACT7_CVID_MASK    0x100
#define    RTL8370_ACL_OP6_NOT_OFFSET    5
#define    RTL8370_ACL_OP6_NOT_MASK    0x20
#define    RTL8370_ACL_ACT6_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT6_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT6_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT6_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT6_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT6_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT6_SVID_OFFSET    1
#define    RTL8370_ACL_ACT6_SVID_MASK    0x2
#define    RTL8370_ACL_ACT6_CVID_OFFSET    0
#define    RTL8370_ACL_ACT6_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL4    0x062c
#define    RTL8370_ACL_OP9_NOT_OFFSET    13
#define    RTL8370_ACL_OP9_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT9_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT9_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT9_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT9_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT9_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT9_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT9_SVID_OFFSET    9
#define    RTL8370_ACL_ACT9_SVID_MASK    0x200
#define    RTL8370_ACL_ACT9_CVID_OFFSET    8
#define    RTL8370_ACL_ACT9_CVID_MASK    0x100
#define    RTL8370_ACL_OP8_NOT_OFFSET    5
#define    RTL8370_ACL_OP8_NOT_MASK    0x20
#define    RTL8370_ACL_ACT8_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT8_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT8_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT8_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT8_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT8_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT8_SVID_OFFSET    1
#define    RTL8370_ACL_ACT8_SVID_MASK    0x2
#define    RTL8370_ACL_ACT8_CVID_OFFSET    0
#define    RTL8370_ACL_ACT8_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL5    0x062d
#define    RTL8370_ACL_OP11_NOT_OFFSET    13
#define    RTL8370_ACL_OP11_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT11_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT11_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT11_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT11_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT11_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT11_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT11_SVID_OFFSET    9
#define    RTL8370_ACL_ACT11_SVID_MASK    0x200
#define    RTL8370_ACL_ACT11_CVID_OFFSET    8
#define    RTL8370_ACL_ACT11_CVID_MASK    0x100
#define    RTL8370_ACL_OP10_NOT_OFFSET    5
#define    RTL8370_ACL_OP10_NOT_MASK    0x20
#define    RTL8370_ACL_ACT10_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT10_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT10_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT10_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT10_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT10_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT10_SVID_OFFSET    1
#define    RTL8370_ACL_ACT10_SVID_MASK    0x2
#define    RTL8370_ACL_ACT10_CVID_OFFSET    0
#define    RTL8370_ACL_ACT10_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL6    0x062e
#define    RTL8370_ACL_OP13_NOT_OFFSET    13
#define    RTL8370_ACL_OP13_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT13_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT13_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT13_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT13_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT13_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT13_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT13_SVID_OFFSET    9
#define    RTL8370_ACL_ACT13_SVID_MASK    0x200
#define    RTL8370_ACL_ACT13_CVID_OFFSET    8
#define    RTL8370_ACL_ACT13_CVID_MASK    0x100
#define    RTL8370_ACL_OP12_NOT_OFFSET    5
#define    RTL8370_ACL_OP12_NOT_MASK    0x20
#define    RTL8370_ACL_ACT12_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT12_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT12_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT12_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT12_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT12_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT12_SVID_OFFSET    1
#define    RTL8370_ACL_ACT12_SVID_MASK    0x2
#define    RTL8370_ACL_ACT12_CVID_OFFSET    0
#define    RTL8370_ACL_ACT12_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL7    0x062f
#define    RTL8370_ACL_OP15_NOT_OFFSET    13
#define    RTL8370_ACL_OP15_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT15_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT15_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT15_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT15_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT15_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT15_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT15_SVID_OFFSET    9
#define    RTL8370_ACL_ACT15_SVID_MASK    0x200
#define    RTL8370_ACL_ACT15_CVID_OFFSET    8
#define    RTL8370_ACL_ACT15_CVID_MASK    0x100
#define    RTL8370_ACL_OP14_NOT_OFFSET    5
#define    RTL8370_ACL_OP14_NOT_MASK    0x20
#define    RTL8370_ACL_ACT14_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT14_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT14_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT14_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT14_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT14_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT14_SVID_OFFSET    1
#define    RTL8370_ACL_ACT14_SVID_MASK    0x2
#define    RTL8370_ACL_ACT14_CVID_OFFSET    0
#define    RTL8370_ACL_ACT14_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL8    0x0630
#define    RTL8370_ACL_OP17_NOT_OFFSET    13
#define    RTL8370_ACL_OP17_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT17_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT17_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT17_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT17_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT17_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT17_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT17_SVID_OFFSET    9
#define    RTL8370_ACL_ACT17_SVID_MASK    0x200
#define    RTL8370_ACL_ACT17_CVID_OFFSET    8
#define    RTL8370_ACL_ACT17_CVID_MASK    0x100
#define    RTL8370_ACL_OP16_NOT_OFFSET    5
#define    RTL8370_ACL_OP16_NOT_MASK    0x20
#define    RTL8370_ACL_ACT16_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT16_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT16_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT16_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT16_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT16_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT16_SVID_OFFSET    1
#define    RTL8370_ACL_ACT16_SVID_MASK    0x2
#define    RTL8370_ACL_ACT16_CVID_OFFSET    0
#define    RTL8370_ACL_ACT16_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL9    0x0631
#define    RTL8370_ACL_OP19_NOT_OFFSET    13
#define    RTL8370_ACL_OP19_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT19_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT19_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT19_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT19_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT19_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT19_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT19_SVID_OFFSET    9
#define    RTL8370_ACL_ACT19_SVID_MASK    0x200
#define    RTL8370_ACL_ACT19_CVID_OFFSET    8
#define    RTL8370_ACL_ACT19_CVID_MASK    0x100
#define    RTL8370_ACL_OP18_NOT_OFFSET    5
#define    RTL8370_ACL_OP18_NOT_MASK    0x20
#define    RTL8370_ACL_ACT18_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT18_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT18_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT18_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT18_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT18_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT18_SVID_OFFSET    1
#define    RTL8370_ACL_ACT18_SVID_MASK    0x2
#define    RTL8370_ACL_ACT18_CVID_OFFSET    0
#define    RTL8370_ACL_ACT18_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL10    0x0632
#define    RTL8370_ACL_OP21_NOT_OFFSET    13
#define    RTL8370_ACL_OP21_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT21_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT21_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT21_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT21_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT21_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT21_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT21_SVID_OFFSET    9
#define    RTL8370_ACL_ACT21_SVID_MASK    0x200
#define    RTL8370_ACL_ACT21_CVID_OFFSET    8
#define    RTL8370_ACL_ACT21_CVID_MASK    0x100
#define    RTL8370_ACL_OP20_NOT_OFFSET    5
#define    RTL8370_ACL_OP20_NOT_MASK    0x20
#define    RTL8370_ACL_ACT20_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT20_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT20_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT20_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT20_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT20_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT20_SVID_OFFSET    1
#define    RTL8370_ACL_ACT20_SVID_MASK    0x2
#define    RTL8370_ACL_ACT20_CVID_OFFSET    0
#define    RTL8370_ACL_ACT20_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL11    0x0633
#define    RTL8370_ACL_OP23_NOT_OFFSET    13
#define    RTL8370_ACL_OP23_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT23_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT23_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT23_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT23_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT23_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT23_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT23_SVID_OFFSET    9
#define    RTL8370_ACL_ACT23_SVID_MASK    0x200
#define    RTL8370_ACL_ACT23_CVID_OFFSET    8
#define    RTL8370_ACL_ACT23_CVID_MASK    0x100
#define    RTL8370_ACL_OP22_NOT_OFFSET    5
#define    RTL8370_ACL_OP22_NOT_MASK    0x20
#define    RTL8370_ACL_ACT22_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT22_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT22_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT22_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT22_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT22_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT22_SVID_OFFSET    1
#define    RTL8370_ACL_ACT22_SVID_MASK    0x2
#define    RTL8370_ACL_ACT22_CVID_OFFSET    0
#define    RTL8370_ACL_ACT22_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL12    0x0634
#define    RTL8370_ACL_OP25_NOT_OFFSET    13
#define    RTL8370_ACL_OP25_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT25_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT25_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT25_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT25_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT25_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT25_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT25_SVID_OFFSET    9
#define    RTL8370_ACL_ACT25_SVID_MASK    0x200
#define    RTL8370_ACL_ACT25_CVID_OFFSET    8
#define    RTL8370_ACL_ACT25_CVID_MASK    0x100
#define    RTL8370_ACL_OP24_NOT_OFFSET    5
#define    RTL8370_ACL_OP24_NOT_MASK    0x20
#define    RTL8370_ACL_ACT24_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT24_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT24_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT24_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT24_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT24_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT24_SVID_OFFSET    1
#define    RTL8370_ACL_ACT24_SVID_MASK    0x2
#define    RTL8370_ACL_ACT24_CVID_OFFSET    0
#define    RTL8370_ACL_ACT24_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL13    0x0635
#define    RTL8370_ACL_OP27_NOT_OFFSET    13
#define    RTL8370_ACL_OP27_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT27_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT27_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT27_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT27_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT27_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT27_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT27_SVID_OFFSET    9
#define    RTL8370_ACL_ACT27_SVID_MASK    0x200
#define    RTL8370_ACL_ACT27_CVID_OFFSET    8
#define    RTL8370_ACL_ACT27_CVID_MASK    0x100
#define    RTL8370_ACL_OP26_NOT_OFFSET    5
#define    RTL8370_ACL_OP26_NOT_MASK    0x20
#define    RTL8370_ACL_ACT26_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT26_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT26_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT26_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT26_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT26_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT26_SVID_OFFSET    1
#define    RTL8370_ACL_ACT26_SVID_MASK    0x2
#define    RTL8370_ACL_ACT26_CVID_OFFSET    0
#define    RTL8370_ACL_ACT26_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL14    0x0636
#define    RTL8370_ACL_OP29_NOT_OFFSET    13
#define    RTL8370_ACL_OP29_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT29_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT29_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT29_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT29_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT29_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT29_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT29_SVID_OFFSET    9
#define    RTL8370_ACL_ACT29_SVID_MASK    0x200
#define    RTL8370_ACL_ACT29_CVID_OFFSET    8
#define    RTL8370_ACL_ACT29_CVID_MASK    0x100
#define    RTL8370_ACL_OP28_NOT_OFFSET    5
#define    RTL8370_ACL_OP28_NOT_MASK    0x20
#define    RTL8370_ACL_ACT28_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT28_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT28_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT28_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT28_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT28_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT28_SVID_OFFSET    1
#define    RTL8370_ACL_ACT28_SVID_MASK    0x2
#define    RTL8370_ACL_ACT28_CVID_OFFSET    0
#define    RTL8370_ACL_ACT28_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL15    0x0637
#define    RTL8370_ACL_OP31_NOT_OFFSET    13
#define    RTL8370_ACL_OP31_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT31_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT31_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT31_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT31_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT31_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT31_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT31_SVID_OFFSET    9
#define    RTL8370_ACL_ACT31_SVID_MASK    0x200
#define    RTL8370_ACL_ACT31_CVID_OFFSET    8
#define    RTL8370_ACL_ACT31_CVID_MASK    0x100
#define    RTL8370_ACL_OP30_NOT_OFFSET    5
#define    RTL8370_ACL_OP30_NOT_MASK    0x20
#define    RTL8370_ACL_ACT30_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT30_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT30_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT30_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT30_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT30_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT30_SVID_OFFSET    1
#define    RTL8370_ACL_ACT30_SVID_MASK    0x2
#define    RTL8370_ACL_ACT30_CVID_OFFSET    0
#define    RTL8370_ACL_ACT30_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL16    0x0638
#define    RTL8370_ACL_OP33_NOT_OFFSET    13
#define    RTL8370_ACL_OP33_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT33_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT33_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT33_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT33_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT33_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT33_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT33_SVID_OFFSET    9
#define    RTL8370_ACL_ACT33_SVID_MASK    0x200
#define    RTL8370_ACL_ACT33_CVID_OFFSET    8
#define    RTL8370_ACL_ACT33_CVID_MASK    0x100
#define    RTL8370_ACL_OP32_NOT_OFFSET    5
#define    RTL8370_ACL_OP32_NOT_MASK    0x20
#define    RTL8370_ACL_ACT32_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT32_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT32_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT32_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT32_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT32_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT32_SVID_OFFSET    1
#define    RTL8370_ACL_ACT32_SVID_MASK    0x2
#define    RTL8370_ACL_ACT32_CVID_OFFSET    0
#define    RTL8370_ACL_ACT32_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL17    0x0639
#define    RTL8370_ACL_OP35_NOT_OFFSET    13
#define    RTL8370_ACL_OP35_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT35_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT35_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT35_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT35_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT35_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT35_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT35_SVID_OFFSET    9
#define    RTL8370_ACL_ACT35_SVID_MASK    0x200
#define    RTL8370_ACL_ACT35_CVID_OFFSET    8
#define    RTL8370_ACL_ACT35_CVID_MASK    0x100
#define    RTL8370_ACL_OP34_NOT_OFFSET    5
#define    RTL8370_ACL_OP34_NOT_MASK    0x20
#define    RTL8370_ACL_ACT34_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT34_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT34_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT34_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT34_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT34_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT34_SVID_OFFSET    1
#define    RTL8370_ACL_ACT34_SVID_MASK    0x2
#define    RTL8370_ACL_ACT34_CVID_OFFSET    0
#define    RTL8370_ACL_ACT34_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL18    0x063a
#define    RTL8370_ACL_OP37_NOT_OFFSET    13
#define    RTL8370_ACL_OP37_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT37_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT37_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT37_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT37_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT37_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT37_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT37_SVID_OFFSET    9
#define    RTL8370_ACL_ACT37_SVID_MASK    0x200
#define    RTL8370_ACL_ACT37_CVID_OFFSET    8
#define    RTL8370_ACL_ACT37_CVID_MASK    0x100
#define    RTL8370_ACL_OP36_NOT_OFFSET    5
#define    RTL8370_ACL_OP36_NOT_MASK    0x20
#define    RTL8370_ACL_ACT36_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT36_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT36_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT36_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT36_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT36_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT36_SVID_OFFSET    1
#define    RTL8370_ACL_ACT36_SVID_MASK    0x2
#define    RTL8370_ACL_ACT36_CVID_OFFSET    0
#define    RTL8370_ACL_ACT36_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL19    0x063b
#define    RTL8370_ACL_OP39_NOT_OFFSET    13
#define    RTL8370_ACL_OP39_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT39_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT39_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT39_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT39_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT39_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT39_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT39_SVID_OFFSET    9
#define    RTL8370_ACL_ACT39_SVID_MASK    0x200
#define    RTL8370_ACL_ACT39_CVID_OFFSET    8
#define    RTL8370_ACL_ACT39_CVID_MASK    0x100
#define    RTL8370_ACL_OP38_NOT_OFFSET    5
#define    RTL8370_ACL_OP38_NOT_MASK    0x20
#define    RTL8370_ACL_ACT38_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT38_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT38_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT38_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT38_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT38_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT38_SVID_OFFSET    1
#define    RTL8370_ACL_ACT38_SVID_MASK    0x2
#define    RTL8370_ACL_ACT38_CVID_OFFSET    0
#define    RTL8370_ACL_ACT38_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL20    0x063c
#define    RTL8370_ACL_OP41_NOT_OFFSET    13
#define    RTL8370_ACL_OP41_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT41_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT41_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT41_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT41_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT41_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT41_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT41_SVID_OFFSET    9
#define    RTL8370_ACL_ACT41_SVID_MASK    0x200
#define    RTL8370_ACL_ACT41_CVID_OFFSET    8
#define    RTL8370_ACL_ACT41_CVID_MASK    0x100
#define    RTL8370_ACL_OP40_NOT_OFFSET    5
#define    RTL8370_ACL_OP40_NOT_MASK    0x20
#define    RTL8370_ACL_ACT40_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT40_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT40_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT40_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT40_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT40_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT40_SVID_OFFSET    1
#define    RTL8370_ACL_ACT40_SVID_MASK    0x2
#define    RTL8370_ACL_ACT40_CVID_OFFSET    0
#define    RTL8370_ACL_ACT40_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL21    0x063d
#define    RTL8370_ACL_OP43_NOT_OFFSET    13
#define    RTL8370_ACL_OP43_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT43_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT43_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT43_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT43_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT43_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT43_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT43_SVID_OFFSET    9
#define    RTL8370_ACL_ACT43_SVID_MASK    0x200
#define    RTL8370_ACL_ACT43_CVID_OFFSET    8
#define    RTL8370_ACL_ACT43_CVID_MASK    0x100
#define    RTL8370_ACL_OP42_NOT_OFFSET    5
#define    RTL8370_ACL_OP42_NOT_MASK    0x20
#define    RTL8370_ACL_ACT42_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT42_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT42_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT42_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT42_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT42_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT42_SVID_OFFSET    1
#define    RTL8370_ACL_ACT42_SVID_MASK    0x2
#define    RTL8370_ACL_ACT42_CVID_OFFSET    0
#define    RTL8370_ACL_ACT42_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL22    0x063e
#define    RTL8370_ACL_OP45_NOT_OFFSET    13
#define    RTL8370_ACL_OP45_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT45_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT45_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT45_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT45_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT45_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT45_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT45_SVID_OFFSET    9
#define    RTL8370_ACL_ACT45_SVID_MASK    0x200
#define    RTL8370_ACL_ACT45_CVID_OFFSET    8
#define    RTL8370_ACL_ACT45_CVID_MASK    0x100
#define    RTL8370_ACL_OP44_NOT_OFFSET    5
#define    RTL8370_ACL_OP44_NOT_MASK    0x20
#define    RTL8370_ACL_ACT44_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT44_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT44_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT44_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT44_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT44_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT44_SVID_OFFSET    1
#define    RTL8370_ACL_ACT44_SVID_MASK    0x2
#define    RTL8370_ACL_ACT44_CVID_OFFSET    0
#define    RTL8370_ACL_ACT44_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL23    0x063f
#define    RTL8370_ACL_OP47_NOT_OFFSET    13
#define    RTL8370_ACL_OP47_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT47_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT47_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT47_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT47_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT47_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT47_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT47_SVID_OFFSET    9
#define    RTL8370_ACL_ACT47_SVID_MASK    0x200
#define    RTL8370_ACL_ACT47_CVID_OFFSET    8
#define    RTL8370_ACL_ACT47_CVID_MASK    0x100
#define    RTL8370_ACL_OP46_NOT_OFFSET    5
#define    RTL8370_ACL_OP46_NOT_MASK    0x20
#define    RTL8370_ACL_ACT46_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT46_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT46_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT46_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT46_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT46_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT46_SVID_OFFSET    1
#define    RTL8370_ACL_ACT46_SVID_MASK    0x2
#define    RTL8370_ACL_ACT46_CVID_OFFSET    0
#define    RTL8370_ACL_ACT46_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL24    0x0640
#define    RTL8370_ACL_OP49_NOT_OFFSET    13
#define    RTL8370_ACL_OP49_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT49_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT49_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT49_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT49_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT49_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT49_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT49_SVID_OFFSET    9
#define    RTL8370_ACL_ACT49_SVID_MASK    0x200
#define    RTL8370_ACL_ACT49_CVID_OFFSET    8
#define    RTL8370_ACL_ACT49_CVID_MASK    0x100
#define    RTL8370_ACL_OP48_NOT_OFFSET    5
#define    RTL8370_ACL_OP48_NOT_MASK    0x20
#define    RTL8370_ACL_ACT48_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT48_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT48_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT48_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT48_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT48_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT48_SVID_OFFSET    1
#define    RTL8370_ACL_ACT48_SVID_MASK    0x2
#define    RTL8370_ACL_ACT48_CVID_OFFSET    0
#define    RTL8370_ACL_ACT48_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL25    0x0641
#define    RTL8370_ACL_OP51_NOT_OFFSET    13
#define    RTL8370_ACL_OP51_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT51_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT51_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT51_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT51_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT51_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT51_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT51_SVID_OFFSET    9
#define    RTL8370_ACL_ACT51_SVID_MASK    0x200
#define    RTL8370_ACL_ACT51_CVID_OFFSET    8
#define    RTL8370_ACL_ACT51_CVID_MASK    0x100
#define    RTL8370_ACL_OP50_NOT_OFFSET    5
#define    RTL8370_ACL_OP50_NOT_MASK    0x20
#define    RTL8370_ACL_ACT50_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT50_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT50_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT50_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT50_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT50_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT50_SVID_OFFSET    1
#define    RTL8370_ACL_ACT50_SVID_MASK    0x2
#define    RTL8370_ACL_ACT50_CVID_OFFSET    0
#define    RTL8370_ACL_ACT50_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL26    0x0642
#define    RTL8370_ACL_OP53_NOT_OFFSET    13
#define    RTL8370_ACL_OP53_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT53_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT53_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT53_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT53_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT53_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT53_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT53_SVID_OFFSET    9
#define    RTL8370_ACL_ACT53_SVID_MASK    0x200
#define    RTL8370_ACL_ACT53_CVID_OFFSET    8
#define    RTL8370_ACL_ACT53_CVID_MASK    0x100
#define    RTL8370_ACL_OP52_NOT_OFFSET    5
#define    RTL8370_ACL_OP52_NOT_MASK    0x20
#define    RTL8370_ACL_ACT52_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT52_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT52_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT52_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT52_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT52_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT52_SVID_OFFSET    1
#define    RTL8370_ACL_ACT52_SVID_MASK    0x2
#define    RTL8370_ACL_ACT52_CVID_OFFSET    0
#define    RTL8370_ACL_ACT52_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL27    0x0643
#define    RTL8370_ACL_OP55_NOT_OFFSET    13
#define    RTL8370_ACL_OP55_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT55_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT55_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT55_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT55_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT55_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT55_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT55_SVID_OFFSET    9
#define    RTL8370_ACL_ACT55_SVID_MASK    0x200
#define    RTL8370_ACL_ACT55_CVID_OFFSET    8
#define    RTL8370_ACL_ACT55_CVID_MASK    0x100
#define    RTL8370_ACL_OP54_NOT_OFFSET    5
#define    RTL8370_ACL_OP54_NOT_MASK    0x20
#define    RTL8370_ACL_ACT54_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT54_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT54_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT54_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT54_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT54_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT54_SVID_OFFSET    1
#define    RTL8370_ACL_ACT54_SVID_MASK    0x2
#define    RTL8370_ACL_ACT54_CVID_OFFSET    0
#define    RTL8370_ACL_ACT54_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL28    0x0644
#define    RTL8370_ACL_OP57_NOT_OFFSET    13
#define    RTL8370_ACL_OP57_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT57_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT57_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT57_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT57_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT57_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT57_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT57_SVID_OFFSET    9
#define    RTL8370_ACL_ACT57_SVID_MASK    0x200
#define    RTL8370_ACL_ACT57_CVID_OFFSET    8
#define    RTL8370_ACL_ACT57_CVID_MASK    0x100
#define    RTL8370_ACL_OP56_NOT_OFFSET    5
#define    RTL8370_ACL_OP56_NOT_MASK    0x20
#define    RTL8370_ACL_ACT56_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT56_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT56_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT56_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT56_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT56_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT56_SVID_OFFSET    1
#define    RTL8370_ACL_ACT56_SVID_MASK    0x2
#define    RTL8370_ACL_ACT56_CVID_OFFSET    0
#define    RTL8370_ACL_ACT56_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL29    0x0645
#define    RTL8370_ACL_OP59_NOT_OFFSET    13
#define    RTL8370_ACL_OP59_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT59_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT59_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT59_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT59_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT59_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT59_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT59_SVID_OFFSET    9
#define    RTL8370_ACL_ACT59_SVID_MASK    0x200
#define    RTL8370_ACL_ACT59_CVID_OFFSET    8
#define    RTL8370_ACL_ACT59_CVID_MASK    0x100
#define    RTL8370_ACL_OP58_NOT_OFFSET    5
#define    RTL8370_ACL_OP58_NOT_MASK    0x20
#define    RTL8370_ACL_ACT58_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT58_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT58_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT58_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT58_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT58_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT58_SVID_OFFSET    1
#define    RTL8370_ACL_ACT58_SVID_MASK    0x2
#define    RTL8370_ACL_ACT58_CVID_OFFSET    0
#define    RTL8370_ACL_ACT58_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL30    0x0646
#define    RTL8370_ACL_OP61_NOT_OFFSET    13
#define    RTL8370_ACL_OP61_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT61_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT61_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT61_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT61_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT61_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT61_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT61_SVID_OFFSET    9
#define    RTL8370_ACL_ACT61_SVID_MASK    0x200
#define    RTL8370_ACL_ACT61_CVID_OFFSET    8
#define    RTL8370_ACL_ACT61_CVID_MASK    0x100
#define    RTL8370_ACL_OP60_NOT_OFFSET    5
#define    RTL8370_ACL_OP60_NOT_MASK    0x20
#define    RTL8370_ACL_ACT60_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT60_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT60_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT60_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT60_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT60_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT60_SVID_OFFSET    1
#define    RTL8370_ACL_ACT60_SVID_MASK    0x2
#define    RTL8370_ACL_ACT60_CVID_OFFSET    0
#define    RTL8370_ACL_ACT60_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL31    0x0647
#define    RTL8370_ACL_OP63_NOT_OFFSET    13
#define    RTL8370_ACL_OP63_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT63_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT63_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT63_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT63_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT63_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT63_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT63_SVID_OFFSET    9
#define    RTL8370_ACL_ACT63_SVID_MASK    0x200
#define    RTL8370_ACL_ACT63_CVID_OFFSET    8
#define    RTL8370_ACL_ACT63_CVID_MASK    0x100
#define    RTL8370_ACL_OP62_NOT_OFFSET    5
#define    RTL8370_ACL_OP62_NOT_MASK    0x20
#define    RTL8370_ACL_ACT62_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT62_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT62_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT62_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT62_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT62_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT62_SVID_OFFSET    1
#define    RTL8370_ACL_ACT62_SVID_MASK    0x2
#define    RTL8370_ACL_ACT62_CVID_OFFSET    0
#define    RTL8370_ACL_ACT62_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL32    0x0648
#define    RTL8370_ACL_OP65_NOT_OFFSET    13
#define    RTL8370_ACL_OP65_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT65_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT65_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT65_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT65_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT65_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT65_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT65_SVID_OFFSET    9
#define    RTL8370_ACL_ACT65_SVID_MASK    0x200
#define    RTL8370_ACL_ACT65_CVID_OFFSET    8
#define    RTL8370_ACL_ACT65_CVID_MASK    0x100
#define    RTL8370_ACL_OP64_NOT_OFFSET    5
#define    RTL8370_ACL_OP64_NOT_MASK    0x20
#define    RTL8370_ACL_ACT64_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT64_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT64_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT64_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT64_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT64_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT64_SVID_OFFSET    1
#define    RTL8370_ACL_ACT64_SVID_MASK    0x2
#define    RTL8370_ACL_ACT64_CVID_OFFSET    0
#define    RTL8370_ACL_ACT64_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL33    0x0649
#define    RTL8370_ACL_OP67_NOT_OFFSET    13
#define    RTL8370_ACL_OP67_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT67_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT67_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT67_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT67_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT67_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT67_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT67_SVID_OFFSET    9
#define    RTL8370_ACL_ACT67_SVID_MASK    0x200
#define    RTL8370_ACL_ACT67_CVID_OFFSET    8
#define    RTL8370_ACL_ACT67_CVID_MASK    0x100
#define    RTL8370_ACL_OP66_NOT_OFFSET    5
#define    RTL8370_ACL_OP66_NOT_MASK    0x20
#define    RTL8370_ACL_ACT66_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT66_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT66_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT66_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT66_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT66_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT66_SVID_OFFSET    1
#define    RTL8370_ACL_ACT66_SVID_MASK    0x2
#define    RTL8370_ACL_ACT66_CVID_OFFSET    0
#define    RTL8370_ACL_ACT66_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL34    0x064a
#define    RTL8370_ACL_OP69_NOT_OFFSET    13
#define    RTL8370_ACL_OP69_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT69_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT69_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT69_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT69_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT69_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT69_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT69_SVID_OFFSET    9
#define    RTL8370_ACL_ACT69_SVID_MASK    0x200
#define    RTL8370_ACL_ACT69_CVID_OFFSET    8
#define    RTL8370_ACL_ACT69_CVID_MASK    0x100
#define    RTL8370_ACL_OP68_NOT_OFFSET    5
#define    RTL8370_ACL_OP68_NOT_MASK    0x20
#define    RTL8370_ACL_ACT68_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT68_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT68_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT68_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT68_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT68_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT68_SVID_OFFSET    1
#define    RTL8370_ACL_ACT68_SVID_MASK    0x2
#define    RTL8370_ACL_ACT68_CVID_OFFSET    0
#define    RTL8370_ACL_ACT68_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL35    0x064b
#define    RTL8370_ACL_OP71_NOT_OFFSET    13
#define    RTL8370_ACL_OP71_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT71_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT71_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT71_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT71_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT71_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT71_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT71_SVID_OFFSET    9
#define    RTL8370_ACL_ACT71_SVID_MASK    0x200
#define    RTL8370_ACL_ACT71_CVID_OFFSET    8
#define    RTL8370_ACL_ACT71_CVID_MASK    0x100
#define    RTL8370_ACL_OP70_NOT_OFFSET    5
#define    RTL8370_ACL_OP70_NOT_MASK    0x20
#define    RTL8370_ACL_ACT70_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT70_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT70_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT70_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT70_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT70_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT70_SVID_OFFSET    1
#define    RTL8370_ACL_ACT70_SVID_MASK    0x2
#define    RTL8370_ACL_ACT70_CVID_OFFSET    0
#define    RTL8370_ACL_ACT70_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL36    0x064c
#define    RTL8370_ACL_OP73_NOT_OFFSET    13
#define    RTL8370_ACL_OP73_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT73_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT73_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT73_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT73_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT73_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT73_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT73_SVID_OFFSET    9
#define    RTL8370_ACL_ACT73_SVID_MASK    0x200
#define    RTL8370_ACL_ACT73_CVID_OFFSET    8
#define    RTL8370_ACL_ACT73_CVID_MASK    0x100
#define    RTL8370_ACL_OP72_NOT_OFFSET    5
#define    RTL8370_ACL_OP72_NOT_MASK    0x20
#define    RTL8370_ACL_ACT72_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT72_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT72_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT72_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT72_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT72_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT72_SVID_OFFSET    1
#define    RTL8370_ACL_ACT72_SVID_MASK    0x2
#define    RTL8370_ACL_ACT72_CVID_OFFSET    0
#define    RTL8370_ACL_ACT72_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL37    0x064d
#define    RTL8370_ACL_OP75_NOT_OFFSET    13
#define    RTL8370_ACL_OP75_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT75_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT75_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT75_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT75_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT75_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT75_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT75_SVID_OFFSET    9
#define    RTL8370_ACL_ACT75_SVID_MASK    0x200
#define    RTL8370_ACL_ACT75_CVID_OFFSET    8
#define    RTL8370_ACL_ACT75_CVID_MASK    0x100
#define    RTL8370_ACL_OP74_NOT_OFFSET    5
#define    RTL8370_ACL_OP74_NOT_MASK    0x20
#define    RTL8370_ACL_ACT74_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT74_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT74_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT74_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT74_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT74_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT74_SVID_OFFSET    1
#define    RTL8370_ACL_ACT74_SVID_MASK    0x2
#define    RTL8370_ACL_ACT74_CVID_OFFSET    0
#define    RTL8370_ACL_ACT74_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL38    0x064e
#define    RTL8370_ACL_OP77_NOT_OFFSET    13
#define    RTL8370_ACL_OP77_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT77_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT77_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT77_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT77_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT77_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT77_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT77_SVID_OFFSET    9
#define    RTL8370_ACL_ACT77_SVID_MASK    0x200
#define    RTL8370_ACL_ACT77_CVID_OFFSET    8
#define    RTL8370_ACL_ACT77_CVID_MASK    0x100
#define    RTL8370_ACL_OP76_NOT_OFFSET    5
#define    RTL8370_ACL_OP76_NOT_MASK    0x20
#define    RTL8370_ACL_ACT76_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT76_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT76_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT76_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT76_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT76_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT76_SVID_OFFSET    1
#define    RTL8370_ACL_ACT76_SVID_MASK    0x2
#define    RTL8370_ACL_ACT76_CVID_OFFSET    0
#define    RTL8370_ACL_ACT76_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL39    0x064f
#define    RTL8370_ACL_OP79_NOT_OFFSET    13
#define    RTL8370_ACL_OP79_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT79_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT79_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT79_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT79_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT79_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT79_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT79_SVID_OFFSET    9
#define    RTL8370_ACL_ACT79_SVID_MASK    0x200
#define    RTL8370_ACL_ACT79_CVID_OFFSET    8
#define    RTL8370_ACL_ACT79_CVID_MASK    0x100
#define    RTL8370_ACL_OP78_NOT_OFFSET    5
#define    RTL8370_ACL_OP78_NOT_MASK    0x20
#define    RTL8370_ACL_ACT78_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT78_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT78_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT78_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT78_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT78_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT78_SVID_OFFSET    1
#define    RTL8370_ACL_ACT78_SVID_MASK    0x2
#define    RTL8370_ACL_ACT78_CVID_OFFSET    0
#define    RTL8370_ACL_ACT78_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL40    0x0650
#define    RTL8370_ACL_OP81_NOT_OFFSET    13
#define    RTL8370_ACL_OP81_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT81_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT81_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT81_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT81_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT81_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT81_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT81_SVID_OFFSET    9
#define    RTL8370_ACL_ACT81_SVID_MASK    0x200
#define    RTL8370_ACL_ACT81_CVID_OFFSET    8
#define    RTL8370_ACL_ACT81_CVID_MASK    0x100
#define    RTL8370_ACL_OP80_NOT_OFFSET    5
#define    RTL8370_ACL_OP80_NOT_MASK    0x20
#define    RTL8370_ACL_ACT80_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT80_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT80_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT80_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT80_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT80_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT80_SVID_OFFSET    1
#define    RTL8370_ACL_ACT80_SVID_MASK    0x2
#define    RTL8370_ACL_ACT80_CVID_OFFSET    0
#define    RTL8370_ACL_ACT80_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL41    0x0651
#define    RTL8370_ACL_OP83_NOT_OFFSET    13
#define    RTL8370_ACL_OP83_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT83_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT83_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT83_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT83_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT83_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT83_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT83_SVID_OFFSET    9
#define    RTL8370_ACL_ACT83_SVID_MASK    0x200
#define    RTL8370_ACL_ACT83_CVID_OFFSET    8
#define    RTL8370_ACL_ACT83_CVID_MASK    0x100
#define    RTL8370_ACL_OP82_NOT_OFFSET    5
#define    RTL8370_ACL_OP82_NOT_MASK    0x20
#define    RTL8370_ACL_ACT82_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT82_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT82_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT82_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT82_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT82_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT82_SVID_OFFSET    1
#define    RTL8370_ACL_ACT82_SVID_MASK    0x2
#define    RTL8370_ACL_ACT82_CVID_OFFSET    0
#define    RTL8370_ACL_ACT82_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL42    0x0652
#define    RTL8370_ACL_OP85_NOT_OFFSET    13
#define    RTL8370_ACL_OP85_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT85_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT85_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT85_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT85_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT85_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT85_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT85_SVID_OFFSET    9
#define    RTL8370_ACL_ACT85_SVID_MASK    0x200
#define    RTL8370_ACL_ACT85_CVID_OFFSET    8
#define    RTL8370_ACL_ACT85_CVID_MASK    0x100
#define    RTL8370_ACL_OP84_NOT_OFFSET    5
#define    RTL8370_ACL_OP84_NOT_MASK    0x20
#define    RTL8370_ACL_ACT84_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT84_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT84_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT84_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT84_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT84_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT84_SVID_OFFSET    1
#define    RTL8370_ACL_ACT84_SVID_MASK    0x2
#define    RTL8370_ACL_ACT84_CVID_OFFSET    0
#define    RTL8370_ACL_ACT84_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL43    0x0653
#define    RTL8370_ACL_OP87_NOT_OFFSET    13
#define    RTL8370_ACL_OP87_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT87_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT87_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT87_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT87_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT87_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT87_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT87_SVID_OFFSET    9
#define    RTL8370_ACL_ACT87_SVID_MASK    0x200
#define    RTL8370_ACL_ACT87_CVID_OFFSET    8
#define    RTL8370_ACL_ACT87_CVID_MASK    0x100
#define    RTL8370_ACL_OP86_NOT_OFFSET    5
#define    RTL8370_ACL_OP86_NOT_MASK    0x20
#define    RTL8370_ACL_ACT86_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT86_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT86_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT86_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT86_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT86_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT86_SVID_OFFSET    1
#define    RTL8370_ACL_ACT86_SVID_MASK    0x2
#define    RTL8370_ACL_ACT86_CVID_OFFSET    0
#define    RTL8370_ACL_ACT86_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL44    0x0654
#define    RTL8370_ACL_OP89_NOT_OFFSET    13
#define    RTL8370_ACL_OP89_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT89_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT89_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT89_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT89_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT89_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT89_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT89_SVID_OFFSET    9
#define    RTL8370_ACL_ACT89_SVID_MASK    0x200
#define    RTL8370_ACL_ACT89_CVID_OFFSET    8
#define    RTL8370_ACL_ACT89_CVID_MASK    0x100
#define    RTL8370_ACL_OP88_NOT_OFFSET    5
#define    RTL8370_ACL_OP88_NOT_MASK    0x20
#define    RTL8370_ACL_ACT88_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT88_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT88_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT88_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT88_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT88_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT88_SVID_OFFSET    1
#define    RTL8370_ACL_ACT88_SVID_MASK    0x2
#define    RTL8370_ACL_ACT88_CVID_OFFSET    0
#define    RTL8370_ACL_ACT88_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL45    0x0655
#define    RTL8370_ACL_OP91_NOT_OFFSET    13
#define    RTL8370_ACL_OP91_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT91_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT91_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT91_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT91_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT91_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT91_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT91_SVID_OFFSET    9
#define    RTL8370_ACL_ACT91_SVID_MASK    0x200
#define    RTL8370_ACL_ACT91_CVID_OFFSET    8
#define    RTL8370_ACL_ACT91_CVID_MASK    0x100
#define    RTL8370_ACL_OP90_NOT_OFFSET    5
#define    RTL8370_ACL_OP90_NOT_MASK    0x20
#define    RTL8370_ACL_ACT90_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT90_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT90_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT90_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT90_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT90_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT90_SVID_OFFSET    1
#define    RTL8370_ACL_ACT90_SVID_MASK    0x2
#define    RTL8370_ACL_ACT90_CVID_OFFSET    0
#define    RTL8370_ACL_ACT90_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL46    0x0656
#define    RTL8370_ACL_OP93_NOT_OFFSET    13
#define    RTL8370_ACL_OP93_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT93_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT93_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT93_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT93_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT93_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT93_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT93_SVID_OFFSET    9
#define    RTL8370_ACL_ACT93_SVID_MASK    0x200
#define    RTL8370_ACL_ACT93_CVID_OFFSET    8
#define    RTL8370_ACL_ACT93_CVID_MASK    0x100
#define    RTL8370_ACL_OP92_NOT_OFFSET    5
#define    RTL8370_ACL_OP92_NOT_MASK    0x20
#define    RTL8370_ACL_ACT92_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT92_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT92_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT92_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT92_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT92_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT92_SVID_OFFSET    1
#define    RTL8370_ACL_ACT92_SVID_MASK    0x2
#define    RTL8370_ACL_ACT92_CVID_OFFSET    0
#define    RTL8370_ACL_ACT92_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL47    0x0657
#define    RTL8370_ACL_OP95_NOT_OFFSET    13
#define    RTL8370_ACL_OP95_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT95_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT95_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT95_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT95_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT95_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT95_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT95_SVID_OFFSET    9
#define    RTL8370_ACL_ACT95_SVID_MASK    0x200
#define    RTL8370_ACL_ACT95_CVID_OFFSET    8
#define    RTL8370_ACL_ACT95_CVID_MASK    0x100
#define    RTL8370_ACL_OP94_NOT_OFFSET    5
#define    RTL8370_ACL_OP94_NOT_MASK    0x20
#define    RTL8370_ACL_ACT94_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT94_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT94_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT94_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT94_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT94_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT94_SVID_OFFSET    1
#define    RTL8370_ACL_ACT94_SVID_MASK    0x2
#define    RTL8370_ACL_ACT94_CVID_OFFSET    0
#define    RTL8370_ACL_ACT94_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL48    0x0658
#define    RTL8370_ACL_OP97_NOT_OFFSET    13
#define    RTL8370_ACL_OP97_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT97_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT97_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT97_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT97_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT97_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT97_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT97_SVID_OFFSET    9
#define    RTL8370_ACL_ACT97_SVID_MASK    0x200
#define    RTL8370_ACL_ACT97_CVID_OFFSET    8
#define    RTL8370_ACL_ACT97_CVID_MASK    0x100
#define    RTL8370_ACL_OP96_NOT_OFFSET    5
#define    RTL8370_ACL_OP96_NOT_MASK    0x20
#define    RTL8370_ACL_ACT96_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT96_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT96_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT96_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT96_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT96_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT96_SVID_OFFSET    1
#define    RTL8370_ACL_ACT96_SVID_MASK    0x2
#define    RTL8370_ACL_ACT96_CVID_OFFSET    0
#define    RTL8370_ACL_ACT96_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL49    0x0659
#define    RTL8370_ACL_OP99_NOT_OFFSET    13
#define    RTL8370_ACL_OP99_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT99_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT99_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT99_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT99_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT99_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT99_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT99_SVID_OFFSET    9
#define    RTL8370_ACL_ACT99_SVID_MASK    0x200
#define    RTL8370_ACL_ACT99_CVID_OFFSET    8
#define    RTL8370_ACL_ACT99_CVID_MASK    0x100
#define    RTL8370_ACL_OP98_NOT_OFFSET    5
#define    RTL8370_ACL_OP98_NOT_MASK    0x20
#define    RTL8370_ACL_ACT98_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT98_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT98_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT98_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT98_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT98_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT98_SVID_OFFSET    1
#define    RTL8370_ACL_ACT98_SVID_MASK    0x2
#define    RTL8370_ACL_ACT98_CVID_OFFSET    0
#define    RTL8370_ACL_ACT98_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL50    0x065a
#define    RTL8370_ACL_OP101_NOT_OFFSET    13
#define    RTL8370_ACL_OP101_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT101_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT101_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT101_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT101_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT101_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT101_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT101_SVID_OFFSET    9
#define    RTL8370_ACL_ACT101_SVID_MASK    0x200
#define    RTL8370_ACL_ACT101_CVID_OFFSET    8
#define    RTL8370_ACL_ACT101_CVID_MASK    0x100
#define    RTL8370_ACL_OP100_NOT_OFFSET    5
#define    RTL8370_ACL_OP100_NOT_MASK    0x20
#define    RTL8370_ACL_ACT100_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT100_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT100_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT100_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT100_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT100_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT100_SVID_OFFSET    1
#define    RTL8370_ACL_ACT100_SVID_MASK    0x2
#define    RTL8370_ACL_ACT100_CVID_OFFSET    0
#define    RTL8370_ACL_ACT100_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL51    0x065b
#define    RTL8370_ACL_OP103_NOT_OFFSET    13
#define    RTL8370_ACL_OP103_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT103_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT103_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT103_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT103_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT103_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT103_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT103_SVID_OFFSET    9
#define    RTL8370_ACL_ACT103_SVID_MASK    0x200
#define    RTL8370_ACL_ACT103_CVID_OFFSET    8
#define    RTL8370_ACL_ACT103_CVID_MASK    0x100
#define    RTL8370_ACL_OP102_NOT_OFFSET    5
#define    RTL8370_ACL_OP102_NOT_MASK    0x20
#define    RTL8370_ACL_ACT102_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT102_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT102_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT102_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT102_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT102_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT102_SVID_OFFSET    1
#define    RTL8370_ACL_ACT102_SVID_MASK    0x2
#define    RTL8370_ACL_ACT102_CVID_OFFSET    0
#define    RTL8370_ACL_ACT102_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL52    0x065c
#define    RTL8370_ACL_OP105_NOT_OFFSET    13
#define    RTL8370_ACL_OP105_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT105_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT105_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT105_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT105_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT105_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT105_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT105_SVID_OFFSET    9
#define    RTL8370_ACL_ACT105_SVID_MASK    0x200
#define    RTL8370_ACL_ACT105_CVID_OFFSET    8
#define    RTL8370_ACL_ACT105_CVID_MASK    0x100
#define    RTL8370_ACL_OP104_NOT_OFFSET    5
#define    RTL8370_ACL_OP104_NOT_MASK    0x20
#define    RTL8370_ACL_ACT104_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT104_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT104_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT104_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT104_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT104_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT104_SVID_OFFSET    1
#define    RTL8370_ACL_ACT104_SVID_MASK    0x2
#define    RTL8370_ACL_ACT104_CVID_OFFSET    0
#define    RTL8370_ACL_ACT104_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL53    0x065d
#define    RTL8370_ACL_OP107_NOT_OFFSET    13
#define    RTL8370_ACL_OP107_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT107_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT107_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT107_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT107_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT107_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT107_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT107_SVID_OFFSET    9
#define    RTL8370_ACL_ACT107_SVID_MASK    0x200
#define    RTL8370_ACL_ACT107_CVID_OFFSET    8
#define    RTL8370_ACL_ACT107_CVID_MASK    0x100
#define    RTL8370_ACL_OP106_NOT_OFFSET    5
#define    RTL8370_ACL_OP106_NOT_MASK    0x20
#define    RTL8370_ACL_ACT106_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT106_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT106_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT106_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT106_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT106_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT106_SVID_OFFSET    1
#define    RTL8370_ACL_ACT106_SVID_MASK    0x2
#define    RTL8370_ACL_ACT106_CVID_OFFSET    0
#define    RTL8370_ACL_ACT106_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL54    0x065e
#define    RTL8370_ACL_OP109_NOT_OFFSET    13
#define    RTL8370_ACL_OP109_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT109_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT109_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT109_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT109_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT109_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT109_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT109_SVID_OFFSET    9
#define    RTL8370_ACL_ACT109_SVID_MASK    0x200
#define    RTL8370_ACL_ACT109_CVID_OFFSET    8
#define    RTL8370_ACL_ACT109_CVID_MASK    0x100
#define    RTL8370_ACL_OP108_NOT_OFFSET    5
#define    RTL8370_ACL_OP108_NOT_MASK    0x20
#define    RTL8370_ACL_ACT108_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT108_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT108_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT108_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT108_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT108_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT108_SVID_OFFSET    1
#define    RTL8370_ACL_ACT108_SVID_MASK    0x2
#define    RTL8370_ACL_ACT108_CVID_OFFSET    0
#define    RTL8370_ACL_ACT108_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL55    0x065f
#define    RTL8370_ACL_OP111_NOT_OFFSET    13
#define    RTL8370_ACL_OP111_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT111_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT111_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT111_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT111_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT111_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT111_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT111_SVID_OFFSET    9
#define    RTL8370_ACL_ACT111_SVID_MASK    0x200
#define    RTL8370_ACL_ACT111_CVID_OFFSET    8
#define    RTL8370_ACL_ACT111_CVID_MASK    0x100
#define    RTL8370_ACL_OP110_NOT_OFFSET    5
#define    RTL8370_ACL_OP110_NOT_MASK    0x20
#define    RTL8370_ACL_ACT110_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT110_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT110_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT110_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT110_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT110_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT110_SVID_OFFSET    1
#define    RTL8370_ACL_ACT110_SVID_MASK    0x2
#define    RTL8370_ACL_ACT110_CVID_OFFSET    0
#define    RTL8370_ACL_ACT110_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL56    0x0660
#define    RTL8370_ACL_OP113_NOT_OFFSET    13
#define    RTL8370_ACL_OP113_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT113_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT113_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT113_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT113_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT113_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT113_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT113_SVID_OFFSET    9
#define    RTL8370_ACL_ACT113_SVID_MASK    0x200
#define    RTL8370_ACL_ACT113_CVID_OFFSET    8
#define    RTL8370_ACL_ACT113_CVID_MASK    0x100
#define    RTL8370_ACL_OP112_NOT_OFFSET    5
#define    RTL8370_ACL_OP112_NOT_MASK    0x20
#define    RTL8370_ACL_ACT112_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT112_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT112_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT112_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT112_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT112_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT112_SVID_OFFSET    1
#define    RTL8370_ACL_ACT112_SVID_MASK    0x2
#define    RTL8370_ACL_ACT112_CVID_OFFSET    0
#define    RTL8370_ACL_ACT112_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL57    0x0661
#define    RTL8370_ACL_OP115_NOT_OFFSET    13
#define    RTL8370_ACL_OP115_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT115_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT115_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT115_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT115_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT115_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT115_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT115_SVID_OFFSET    9
#define    RTL8370_ACL_ACT115_SVID_MASK    0x200
#define    RTL8370_ACL_ACT115_CVID_OFFSET    8
#define    RTL8370_ACL_ACT115_CVID_MASK    0x100
#define    RTL8370_ACL_OP114_NOT_OFFSET    5
#define    RTL8370_ACL_OP114_NOT_MASK    0x20
#define    RTL8370_ACL_ACT114_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT114_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT114_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT114_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT114_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT114_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT114_SVID_OFFSET    1
#define    RTL8370_ACL_ACT114_SVID_MASK    0x2
#define    RTL8370_ACL_ACT114_CVID_OFFSET    0
#define    RTL8370_ACL_ACT114_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL58    0x0662
#define    RTL8370_ACL_OP117_NOT_OFFSET    13
#define    RTL8370_ACL_OP117_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT117_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT117_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT117_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT117_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT117_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT117_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT117_SVID_OFFSET    9
#define    RTL8370_ACL_ACT117_SVID_MASK    0x200
#define    RTL8370_ACL_ACT117_CVID_OFFSET    8
#define    RTL8370_ACL_ACT117_CVID_MASK    0x100
#define    RTL8370_ACL_OP116_NOT_OFFSET    5
#define    RTL8370_ACL_OP116_NOT_MASK    0x20
#define    RTL8370_ACL_ACT116_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT116_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT116_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT116_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT116_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT116_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT116_SVID_OFFSET    1
#define    RTL8370_ACL_ACT116_SVID_MASK    0x2
#define    RTL8370_ACL_ACT116_CVID_OFFSET    0
#define    RTL8370_ACL_ACT116_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL59    0x0663
#define    RTL8370_ACL_OP119_NOT_OFFSET    13
#define    RTL8370_ACL_OP119_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT119_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT119_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT119_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT119_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT119_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT119_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT119_SVID_OFFSET    9
#define    RTL8370_ACL_ACT119_SVID_MASK    0x200
#define    RTL8370_ACL_ACT119_CVID_OFFSET    8
#define    RTL8370_ACL_ACT119_CVID_MASK    0x100
#define    RTL8370_ACL_OP118_NOT_OFFSET    5
#define    RTL8370_ACL_OP118_NOT_MASK    0x20
#define    RTL8370_ACL_ACT118_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT118_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT118_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT118_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT118_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT118_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT118_SVID_OFFSET    1
#define    RTL8370_ACL_ACT118_SVID_MASK    0x2
#define    RTL8370_ACL_ACT118_CVID_OFFSET    0
#define    RTL8370_ACL_ACT118_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL60    0x0664
#define    RTL8370_ACL_OP121_NOT_OFFSET    13
#define    RTL8370_ACL_OP121_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT121_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT121_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT121_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT121_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT121_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT121_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT121_SVID_OFFSET    9
#define    RTL8370_ACL_ACT121_SVID_MASK    0x200
#define    RTL8370_ACL_ACT121_CVID_OFFSET    8
#define    RTL8370_ACL_ACT121_CVID_MASK    0x100
#define    RTL8370_ACL_OP120_NOT_OFFSET    5
#define    RTL8370_ACL_OP120_NOT_MASK    0x20
#define    RTL8370_ACL_ACT120_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT120_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT120_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT120_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT120_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT120_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT120_SVID_OFFSET    1
#define    RTL8370_ACL_ACT120_SVID_MASK    0x2
#define    RTL8370_ACL_ACT120_CVID_OFFSET    0
#define    RTL8370_ACL_ACT120_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL61    0x0665
#define    RTL8370_ACL_OP123_NOT_OFFSET    13
#define    RTL8370_ACL_OP123_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT123_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT123_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT123_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT123_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT123_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT123_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT123_SVID_OFFSET    9
#define    RTL8370_ACL_ACT123_SVID_MASK    0x200
#define    RTL8370_ACL_ACT123_CVID_OFFSET    8
#define    RTL8370_ACL_ACT123_CVID_MASK    0x100
#define    RTL8370_ACL_OP122_NOT_OFFSET    5
#define    RTL8370_ACL_OP122_NOT_MASK    0x20
#define    RTL8370_ACL_ACT122_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT122_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT122_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT122_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT122_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT122_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT122_SVID_OFFSET    1
#define    RTL8370_ACL_ACT122_SVID_MASK    0x2
#define    RTL8370_ACL_ACT122_CVID_OFFSET    0
#define    RTL8370_ACL_ACT122_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL62    0x0666
#define    RTL8370_ACL_OP125_NOT_OFFSET    13
#define    RTL8370_ACL_OP125_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT125_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT125_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT125_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT125_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT125_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT125_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT125_SVID_OFFSET    9
#define    RTL8370_ACL_ACT125_SVID_MASK    0x200
#define    RTL8370_ACL_ACT125_CVID_OFFSET    8
#define    RTL8370_ACL_ACT125_CVID_MASK    0x100
#define    RTL8370_ACL_OP124_NOT_OFFSET    5
#define    RTL8370_ACL_OP124_NOT_MASK    0x20
#define    RTL8370_ACL_ACT124_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT124_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT124_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT124_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT124_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT124_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT124_SVID_OFFSET    1
#define    RTL8370_ACL_ACT124_SVID_MASK    0x2
#define    RTL8370_ACL_ACT124_CVID_OFFSET    0
#define    RTL8370_ACL_ACT124_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ACTION_CTRL63    0x0667
#define    RTL8370_ACL_OP127_NOT_OFFSET    13
#define    RTL8370_ACL_OP127_NOT_MASK    0x2000
#define    RTL8370_ACL_ACT127_FORWARD_OFFSET    12
#define    RTL8370_ACL_ACT127_FORWARD_MASK    0x1000
#define    RTL8370_ACL_ACT127_POLICING_OFFSET    11
#define    RTL8370_ACL_ACT127_POLICING_MASK    0x800
#define    RTL8370_ACL_ACT127_PRIORITY_OFFSET    10
#define    RTL8370_ACL_ACT127_PRIORITY_MASK    0x400
#define    RTL8370_ACL_ACT127_SVID_OFFSET    9
#define    RTL8370_ACL_ACT127_SVID_MASK    0x200
#define    RTL8370_ACL_ACT127_CVID_OFFSET    8
#define    RTL8370_ACL_ACT127_CVID_MASK    0x100
#define    RTL8370_ACL_OP126_NOT_OFFSET    5
#define    RTL8370_ACL_OP126_NOT_MASK    0x20
#define    RTL8370_ACL_ACT126_FORWARD_OFFSET    4
#define    RTL8370_ACL_ACT126_FORWARD_MASK    0x10
#define    RTL8370_ACL_ACT126_POLICING_OFFSET    3
#define    RTL8370_ACL_ACT126_POLICING_MASK    0x8
#define    RTL8370_ACL_ACT126_PRIORITY_OFFSET    2
#define    RTL8370_ACL_ACT126_PRIORITY_MASK    0x4
#define    RTL8370_ACL_ACT126_SVID_OFFSET    1
#define    RTL8370_ACL_ACT126_SVID_MASK    0x2
#define    RTL8370_ACL_ACT126_CVID_OFFSET    0
#define    RTL8370_ACL_ACT126_CVID_MASK    0x1

#define    RTL8370_REG_ACL_ENABLE    0x0668
#define    RTL8370_ACL_PORT15_ENABLE_OFFSET    15
#define    RTL8370_ACL_PORT15_ENABLE_MASK    0x8000
#define    RTL8370_ACL_PORT14_ENABLE_OFFSET    14
#define    RTL8370_ACL_PORT14_ENABLE_MASK    0x4000
#define    RTL8370_ACL_PORT13_ENABLE_OFFSET    13
#define    RTL8370_ACL_PORT13_ENABLE_MASK    0x2000
#define    RTL8370_ACL_PORT12_ENABLE_OFFSET    12
#define    RTL8370_ACL_PORT12_ENABLE_MASK    0x1000
#define    RTL8370_ACL_PORT11_ENABLE_OFFSET    11
#define    RTL8370_ACL_PORT11_ENABLE_MASK    0x800
#define    RTL8370_ACL_PORT10_ENABLE_OFFSET    10
#define    RTL8370_ACL_PORT10_ENABLE_MASK    0x400
#define    RTL8370_ACL_PORT9_ENABLE_OFFSET    9
#define    RTL8370_ACL_PORT9_ENABLE_MASK    0x200
#define    RTL8370_ACL_PORT8_ENABLE_OFFSET    8
#define    RTL8370_ACL_PORT8_ENABLE_MASK    0x100
#define    RTL8370_ACL_PORT7_ENABLE_OFFSET    7
#define    RTL8370_ACL_PORT7_ENABLE_MASK    0x80
#define    RTL8370_ACL_PORT6_ENABLE_OFFSET    6
#define    RTL8370_ACL_PORT6_ENABLE_MASK    0x40
#define    RTL8370_ACL_PORT5_ENABLE_OFFSET    5
#define    RTL8370_ACL_PORT5_ENABLE_MASK    0x20
#define    RTL8370_ACL_PORT4_ENABLE_OFFSET    4
#define    RTL8370_ACL_PORT4_ENABLE_MASK    0x10
#define    RTL8370_ACL_PORT3_ENABLE_OFFSET    3
#define    RTL8370_ACL_PORT3_ENABLE_MASK    0x8
#define    RTL8370_ACL_PORT2_ENABLE_OFFSET    2
#define    RTL8370_ACL_PORT2_ENABLE_MASK    0x4
#define    RTL8370_ACL_PORT1_ENABLE_OFFSET    1
#define    RTL8370_ACL_PORT1_ENABLE_MASK    0x2
#define    RTL8370_ACL_PORT0_ENABLE_OFFSET    0
#define    RTL8370_ACL_PORT0_ENABLE_MASK    0x1

#define    RTL8370_REG_ACL_UNMATCH_PERMIT    0x0669
#define    RTL8370_ACL_PORT15_PERMIT_OFFSET    15
#define    RTL8370_ACL_PORT15_PERMIT_MASK    0x8000
#define    RTL8370_ACL_PORT14_PERMIT_OFFSET    14
#define    RTL8370_ACL_PORT14_PERMIT_MASK    0x4000
#define    RTL8370_ACL_PORT13_PERMIT_OFFSET    13
#define    RTL8370_ACL_PORT13_PERMIT_MASK    0x2000
#define    RTL8370_ACL_PORT12_PERMIT_OFFSET    12
#define    RTL8370_ACL_PORT12_PERMIT_MASK    0x1000
#define    RTL8370_ACL_PORT11_PERMIT_OFFSET    11
#define    RTL8370_ACL_PORT11_PERMIT_MASK    0x800
#define    RTL8370_ACL_PORT10_PERMIT_OFFSET    10
#define    RTL8370_ACL_PORT10_PERMIT_MASK    0x400
#define    RTL8370_ACL_PORT9_PERMIT_OFFSET    9
#define    RTL8370_ACL_PORT9_PERMIT_MASK    0x200
#define    RTL8370_ACL_PORT8_PERMIT_OFFSET    8
#define    RTL8370_ACL_PORT8_PERMIT_MASK    0x100
#define    RTL8370_ACL_PORT7_PERMIT_OFFSET    7
#define    RTL8370_ACL_PORT7_PERMIT_MASK    0x80
#define    RTL8370_ACL_PORT6_PERMIT_OFFSET    6
#define    RTL8370_ACL_PORT6_PERMIT_MASK    0x40
#define    RTL8370_ACL_PORT5_PERMIT_OFFSET    5
#define    RTL8370_ACL_PORT5_PERMIT_MASK    0x20
#define    RTL8370_ACL_PORT4_PERMIT_OFFSET    4
#define    RTL8370_ACL_PORT4_PERMIT_MASK    0x10
#define    RTL8370_ACL_PORT3_PERMIT_OFFSET    3
#define    RTL8370_ACL_PORT3_PERMIT_MASK    0x8
#define    RTL8370_ACL_PORT2_PERMIT_OFFSET    2
#define    RTL8370_ACL_PORT2_PERMIT_MASK    0x4
#define    RTL8370_ACL_PORT1_PERMIT_OFFSET    1
#define    RTL8370_ACL_PORT1_PERMIT_MASK    0x2
#define    RTL8370_ACL_PORT0_PERMIT_OFFSET    0
#define    RTL8370_ACL_PORT0_PERMIT_MASK    0x1

/* (16'h0700) cvlan_reg */

#define    RTL8370_REG_VLAN_PVID_CTRL0    0x0700
#define    RTL8370_PORT1_VIDX_OFFSET    8
#define    RTL8370_PORT1_VIDX_MASK    0x1F00
#define    RTL8370_PORT0_VIDX_OFFSET    0
#define    RTL8370_PORT0_VIDX_MASK    0x1F

#define    RTL8370_REG_VLAN_PVID_CTRL1    0x0701
#define    RTL8370_PORT3_VIDX_OFFSET    8
#define    RTL8370_PORT3_VIDX_MASK    0x1F00
#define    RTL8370_PORT2_VIDX_OFFSET    0
#define    RTL8370_PORT2_VIDX_MASK    0x1F

#define    RTL8370_REG_VLAN_PVID_CTRL2    0x0702
#define    RTL8370_PORT5_VIDX_OFFSET    8
#define    RTL8370_PORT5_VIDX_MASK    0x1F00
#define    RTL8370_PORT4_VIDX_OFFSET    0
#define    RTL8370_PORT4_VIDX_MASK    0x1F

#define    RTL8370_REG_VLAN_PVID_CTRL3    0x0703
#define    RTL8370_PORT7_VIDX_OFFSET    8
#define    RTL8370_PORT7_VIDX_MASK    0x1F00
#define    RTL8370_PORT6_VIDX_OFFSET    0
#define    RTL8370_PORT6_VIDX_MASK    0x1F

#define    RTL8370_REG_VLAN_PVID_CTRL4    0x0704
#define    RTL8370_PORT9_VIDX_OFFSET    8
#define    RTL8370_PORT9_VIDX_MASK    0x1F00
#define    RTL8370_PORT8_VIDX_OFFSET    0
#define    RTL8370_PORT8_VIDX_MASK    0x1F

#define    RTL8370_REG_VLAN_PVID_CTRL5    0x0705
#define    RTL8370_PORT11_VIDX_OFFSET    8
#define    RTL8370_PORT11_VIDX_MASK    0x1F00
#define    RTL8370_PORT10_VIDX_OFFSET    0
#define    RTL8370_PORT10_VIDX_MASK    0x1F

#define    RTL8370_REG_VLAN_PVID_CTRL6    0x0706
#define    RTL8370_PORT13_VIDX_OFFSET    8
#define    RTL8370_PORT13_VIDX_MASK    0x1F00
#define    RTL8370_PORT12_VIDX_OFFSET    0
#define    RTL8370_PORT12_VIDX_MASK    0x1F

#define    RTL8370_REG_VLAN_PVID_CTRL7    0x0707
#define    RTL8370_PORT15_VIDX_OFFSET    8
#define    RTL8370_PORT15_VIDX_MASK    0x1F00
#define    RTL8370_PORT14_VIDX_OFFSET    0
#define    RTL8370_PORT14_VIDX_MASK    0x1F

#define    RTL8370_REG_VLAN_PPB0_VALID    0x0708

#define    RTL8370_REG_VLAN_PPB0_CTRL0    0x0709
#define    RTL8370_PPB0_PORT2_INDEX_OFFSET    10
#define    RTL8370_PPB0_PORT2_INDEX_MASK    0x7C00
#define    RTL8370_PPB0_PORT1_INDEX_OFFSET    5
#define    RTL8370_PPB0_PORT1_INDEX_MASK    0x3E0
#define    RTL8370_PPB0_PORT0_INDEX_OFFSET    0
#define    RTL8370_PPB0_PORT0_INDEX_MASK    0x1F

#define    RTL8370_REG_VLAN_PPB0_CTRL1    0x070a
#define    RTL8370_PPB0_PORT5_INDEX_OFFSET    10
#define    RTL8370_PPB0_PORT5_INDEX_MASK    0x7C00
#define    RTL8370_PPB0_PORT4_INDEX_OFFSET    5
#define    RTL8370_PPB0_PORT4_INDEX_MASK    0x3E0
#define    RTL8370_PPB0_PORT3_INDEX_OFFSET    0
#define    RTL8370_PPB0_PORT3_INDEX_MASK    0x1F

#define    RTL8370_REG_VLAN_PPB0_CTRL2    0x070b
#define    RTL8370_PPB0_PORT8_INDEX_OFFSET    10
#define    RTL8370_PPB0_PORT8_INDEX_MASK    0x7C00
#define    RTL8370_PPB0_PORT7_INDEX_OFFSET    5
#define    RTL8370_PPB0_PORT7_INDEX_MASK    0x3E0
#define    RTL8370_PPB0_PORT6_INDEX_OFFSET    0
#define    RTL8370_PPB0_PORT6_INDEX_MASK    0x1F

#define    RTL8370_REG_VLAN_PPB0_CTRL3    0x070c
#define    RTL8370_PPB0_PORT11_INDEX_OFFSET    10
#define    RTL8370_PPB0_PORT11_INDEX_MASK    0x7C00
#define    RTL8370_PPB0_PORT10_INDEX_OFFSET    5
#define    RTL8370_PPB0_PORT10_INDEX_MASK    0x3E0
#define    RTL8370_PPB0_PORT9_INDEX_OFFSET    0
#define    RTL8370_PPB0_PORT9_INDEX_MASK    0x1F

#define    RTL8370_REG_VLAN_PPB0_CTRL4    0x070d
#define    RTL8370_PPB0_PORT14_INDEX_OFFSET    10
#define    RTL8370_PPB0_PORT14_INDEX_MASK    0x7C00
#define    RTL8370_PPB0_PORT13_INDEX_OFFSET    5
#define    RTL8370_PPB0_PORT13_INDEX_MASK    0x3E0
#define    RTL8370_PPB0_PORT12_INDEX_OFFSET    0
#define    RTL8370_PPB0_PORT12_INDEX_MASK    0x1F

#define    RTL8370_REG_VLAN_PPB0_CTRL5    0x070e
#define    RTL8370_PPB0_FRAME_TYPE_OFFSET    5
#define    RTL8370_PPB0_FRAME_TYPE_MASK    0x60
#define    RTL8370_PPB0_PORT15_INDEX_OFFSET    0
#define    RTL8370_PPB0_PORT15_INDEX_MASK    0x1F

#define    RTL8370_REG_VLAN_PPB0_CTRL6    0x070f

#define    RTL8370_REG_VLAN_PPB1_VALID    0x0710

#define    RTL8370_REG_VLAN_PPB1_CTRL0    0x0711
#define    RTL8370_PPB1_PORT2_INDEX_OFFSET    10
#define    RTL8370_PPB1_PORT2_INDEX_MASK    0x7C00
#define    RTL8370_PPB1_PORT1_INDEX_OFFSET    5
#define    RTL8370_PPB1_PORT1_INDEX_MASK    0x3E0
#define    RTL8370_PPB1_PORT0_INDEX_OFFSET    0
#define    RTL8370_PPB1_PORT0_INDEX_MASK    0x1F

#define    RTL8370_REG_VLAN_PPB1_CTRL1    0x0712
#define    RTL8370_PPB1_PORT5_INDEX_OFFSET    10
#define    RTL8370_PPB1_PORT5_INDEX_MASK    0x7C00
#define    RTL8370_PPB1_PORT4_INDEX_OFFSET    5
#define    RTL8370_PPB1_PORT4_INDEX_MASK    0x3E0
#define    RTL8370_PPB1_PORT3_INDEX_OFFSET    0
#define    RTL8370_PPB1_PORT3_INDEX_MASK    0x1F

#define    RTL8370_REG_VLAN_PPB1_CTRL2    0x0713
#define    RTL8370_PPB1_PORT8_INDEX_OFFSET    10
#define    RTL8370_PPB1_PORT8_INDEX_MASK    0x7C00
#define    RTL8370_PPB1_PORT7_INDEX_OFFSET    5
#define    RTL8370_PPB1_PORT7_INDEX_MASK    0x3E0
#define    RTL8370_PPB1_PORT6_INDEX_OFFSET    0
#define    RTL8370_PPB1_PORT6_INDEX_MASK    0x1F

#define    RTL8370_REG_VLAN_PPB1_CTRL3    0x0714
#define    RTL8370_PPB1_PORT11_INDEX_OFFSET    10
#define    RTL8370_PPB1_PORT11_INDEX_MASK    0x7C00
#define    RTL8370_PPB1_PORT10_INDEX_OFFSET    5
#define    RTL8370_PPB1_PORT10_INDEX_MASK    0x3E0
#define    RTL8370_PPB1_PORT9_INDEX_OFFSET    0
#define    RTL8370_PPB1_PORT9_INDEX_MASK    0x1F

#define    RTL8370_REG_VLAN_PPB1_CTRL4    0x0715
#define    RTL8370_PPB1_PORT14_INDEX_OFFSET    10
#define    RTL8370_PPB1_PORT14_INDEX_MASK    0x7C00
#define    RTL8370_PPB1_PORT13_INDEX_OFFSET    5
#define    RTL8370_PPB1_PORT13_INDEX_MASK    0x3E0
#define    RTL8370_PPB1_PORT12_INDEX_OFFSET    0
#define    RTL8370_PPB1_PORT12_INDEX_MASK    0x1F

#define    RTL8370_REG_VLAN_PPB1_CTRL5    0x0716
#define    RTL8370_PPB1_FRAME_TYPE_OFFSET    5
#define    RTL8370_PPB1_FRAME_TYPE_MASK    0x60
#define    RTL8370_PPB1_PORT15_INDEX_OFFSET    0
#define    RTL8370_PPB1_PORT15_INDEX_MASK    0x1F

#define    RTL8370_REG_VLAN_PPB1_CTRL6    0x0717

#define    RTL8370_REG_VLAN_PPB2_VALID    0x0718

#define    RTL8370_REG_VLAN_PPB2_CTRL0    0x0719
#define    RTL8370_PPB2_PORT2_INDEX_OFFSET    10
#define    RTL8370_PPB2_PORT2_INDEX_MASK    0x7C00
#define    RTL8370_PPB2_PORT1_INDEX_OFFSET    5
#define    RTL8370_PPB2_PORT1_INDEX_MASK    0x3E0
#define    RTL8370_PPB2_PORT0_INDEX_OFFSET    0
#define    RTL8370_PPB2_PORT0_INDEX_MASK    0x1F

#define    RTL8370_REG_VLAN_PPB2_CTRL1    0x071a
#define    RTL8370_PPB2_PORT5_INDEX_OFFSET    10
#define    RTL8370_PPB2_PORT5_INDEX_MASK    0x7C00
#define    RTL8370_PPB2_PORT4_INDEX_OFFSET    5
#define    RTL8370_PPB2_PORT4_INDEX_MASK    0x3E0
#define    RTL8370_PPB2_PORT3_INDEX_OFFSET    0
#define    RTL8370_PPB2_PORT3_INDEX_MASK    0x1F

#define    RTL8370_REG_VLAN_PPB2_CTRL2    0x071b
#define    RTL8370_PPB2_PORT8_INDEX_OFFSET    10
#define    RTL8370_PPB2_PORT8_INDEX_MASK    0x7C00
#define    RTL8370_PPB2_PORT7_INDEX_OFFSET    5
#define    RTL8370_PPB2_PORT7_INDEX_MASK    0x3E0
#define    RTL8370_PPB2_PORT6_INDEX_OFFSET    0
#define    RTL8370_PPB2_PORT6_INDEX_MASK    0x1F

#define    RTL8370_REG_VLAN_PPB2_CTRL3    0x071c
#define    RTL8370_PPB2_PORT11_INDEX_OFFSET    10
#define    RTL8370_PPB2_PORT11_INDEX_MASK    0x7C00
#define    RTL8370_PPB2_PORT10_INDEX_OFFSET    5
#define    RTL8370_PPB2_PORT10_INDEX_MASK    0x3E0
#define    RTL8370_PPB2_PORT9_INDEX_OFFSET    0
#define    RTL8370_PPB2_PORT9_INDEX_MASK    0x1F

#define    RTL8370_REG_VLAN_PPB2_CTRL4    0x071d
#define    RTL8370_PPB2_PORT14_INDEX_OFFSET    10
#define    RTL8370_PPB2_PORT14_INDEX_MASK    0x7C00
#define    RTL8370_PPB2_PORT13_INDEX_OFFSET    5
#define    RTL8370_PPB2_PORT13_INDEX_MASK    0x3E0
#define    RTL8370_PPB2_PORT12_INDEX_OFFSET    0
#define    RTL8370_PPB2_PORT12_INDEX_MASK    0x1F

#define    RTL8370_REG_VLAN_PPB2_CTRL5    0x071e
#define    RTL8370_PPB2_FRAME_TYPE_OFFSET    5
#define    RTL8370_PPB2_FRAME_TYPE_MASK    0x60
#define    RTL8370_PPB2_PORT15_INDEX_OFFSET    0
#define    RTL8370_PPB2_PORT15_INDEX_MASK    0x1F

#define    RTL8370_REG_VLAN_PPB2_CTRL6    0x071f

#define    RTL8370_REG_VLAN_PPB3_VALID    0x0720

#define    RTL8370_REG_VLAN_PPB3_CTRL0    0x0721
#define    RTL8370_PPB3_PORT2_INDEX_OFFSET    10
#define    RTL8370_PPB3_PORT2_INDEX_MASK    0x7C00
#define    RTL8370_PPB3_PORT1_INDEX_OFFSET    5
#define    RTL8370_PPB3_PORT1_INDEX_MASK    0x3E0
#define    RTL8370_PPB3_PORT0_INDEX_OFFSET    0
#define    RTL8370_PPB3_PORT0_INDEX_MASK    0x1F

#define    RTL8370_REG_VLAN_PPB3_CTRL1    0x0722
#define    RTL8370_PPB3_PORT5_INDEX_OFFSET    10
#define    RTL8370_PPB3_PORT5_INDEX_MASK    0x7C00
#define    RTL8370_PPB3_PORT4_INDEX_OFFSET    5
#define    RTL8370_PPB3_PORT4_INDEX_MASK    0x3E0
#define    RTL8370_PPB3_PORT3_INDEX_OFFSET    0
#define    RTL8370_PPB3_PORT3_INDEX_MASK    0x1F

#define    RTL8370_REG_VLAN_PPB3_CTRL2    0x0723
#define    RTL8370_PPB3_PORT8_INDEX_OFFSET    10
#define    RTL8370_PPB3_PORT8_INDEX_MASK    0x7C00
#define    RTL8370_PPB3_PORT7_INDEX_OFFSET    5
#define    RTL8370_PPB3_PORT7_INDEX_MASK    0x3E0
#define    RTL8370_PPB3_PORT6_INDEX_OFFSET    0
#define    RTL8370_PPB3_PORT6_INDEX_MASK    0x1F

#define    RTL8370_REG_VLAN_PPB3_CTRL3    0x0724
#define    RTL8370_PPB3_PORT11_INDEX_OFFSET    10
#define    RTL8370_PPB3_PORT11_INDEX_MASK    0x7C00
#define    RTL8370_PPB3_PORT10_INDEX_OFFSET    5
#define    RTL8370_PPB3_PORT10_INDEX_MASK    0x3E0
#define    RTL8370_PPB3_PORT9_INDEX_OFFSET    0
#define    RTL8370_PPB3_PORT9_INDEX_MASK    0x1F

#define    RTL8370_REG_VLAN_PPB3_CTRL4    0x0725
#define    RTL8370_PPB3_PORT14_INDEX_OFFSET    10
#define    RTL8370_PPB3_PORT14_INDEX_MASK    0x7C00
#define    RTL8370_PPB3_PORT13_INDEX_OFFSET    5
#define    RTL8370_PPB3_PORT13_INDEX_MASK    0x3E0
#define    RTL8370_PPB3_PORT12_INDEX_OFFSET    0
#define    RTL8370_PPB3_PORT12_INDEX_MASK    0x1F

#define    RTL8370_REG_VLAN_PPB3_CTRL5    0x0726
#define    RTL8370_PPB3_FRAME_TYPE_OFFSET    5
#define    RTL8370_PPB3_FRAME_TYPE_MASK    0x60
#define    RTL8370_PPB3_PORT15_INDEX_OFFSET    0
#define    RTL8370_PPB3_PORT15_INDEX_MASK    0x1F

#define    RTL8370_REG_VLAN_PPB3_CTRL6    0x0727

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION0_CTRL0    0x0728

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION0_CTRL1    0x0729
#define    RTL8370_VLAN_MEMBER_CONFIGURATION0_CTRL1_MSTI_OFFSET    12
#define    RTL8370_VLAN_MEMBER_CONFIGURATION0_CTRL1_MSTI_MASK    0xF000
#define    RTL8370_VLAN_MEMBER_CONFIGURATION0_CTRL1_FID_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION0_CTRL1_FID_MASK    0xFFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION0_CTRL2    0x072a
#define    RTL8370_VLAN_MEMBER_CONFIGURATION0_CTRL2_METERIDX_OFFSET    6
#define    RTL8370_VLAN_MEMBER_CONFIGURATION0_CTRL2_METERIDX_MASK    0x3FC0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION0_CTRL2_ENVLANPOL_OFFSET    5
#define    RTL8370_VLAN_MEMBER_CONFIGURATION0_CTRL2_ENVLANPOL_MASK    0x20
#define    RTL8370_VLAN_MEMBER_CONFIGURATION0_CTRL2_VBPRI_OFFSET    2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION0_CTRL2_VBPRI_MASK    0x1C
#define    RTL8370_VLAN_MEMBER_CONFIGURATION0_CTRL2_VBPEN_OFFSET    1
#define    RTL8370_VLAN_MEMBER_CONFIGURATION0_CTRL2_VBPEN_MASK    0x2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION0_CTRL2_LUREP_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION0_CTRL2_LUREP_MASK    0x1

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION0_CTRL3    0x072b
#define    RTL8370_VLAN_MEMBER_CONFIGURATION0_CTRL3_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION0_CTRL3_MASK    0x1FFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION1_CTRL0    0x072c

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION1_CTRL1    0x072d
#define    RTL8370_VLAN_MEMBER_CONFIGURATION1_CTRL1_MSTI_OFFSET    12
#define    RTL8370_VLAN_MEMBER_CONFIGURATION1_CTRL1_MSTI_MASK    0xF000
#define    RTL8370_VLAN_MEMBER_CONFIGURATION1_CTRL1_FID_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION1_CTRL1_FID_MASK    0xFFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION1_CTRL2    0x072e
#define    RTL8370_VLAN_MEMBER_CONFIGURATION1_CTRL2_METERIDX_OFFSET    6
#define    RTL8370_VLAN_MEMBER_CONFIGURATION1_CTRL2_METERIDX_MASK    0x3FC0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION1_CTRL2_ENVLANPOL_OFFSET    5
#define    RTL8370_VLAN_MEMBER_CONFIGURATION1_CTRL2_ENVLANPOL_MASK    0x20
#define    RTL8370_VLAN_MEMBER_CONFIGURATION1_CTRL2_VBPRI_OFFSET    2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION1_CTRL2_VBPRI_MASK    0x1C
#define    RTL8370_VLAN_MEMBER_CONFIGURATION1_CTRL2_VBPEN_OFFSET    1
#define    RTL8370_VLAN_MEMBER_CONFIGURATION1_CTRL2_VBPEN_MASK    0x2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION1_CTRL2_LUREP_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION1_CTRL2_LUREP_MASK    0x1

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION1_CTRL3    0x072f
#define    RTL8370_VLAN_MEMBER_CONFIGURATION1_CTRL3_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION1_CTRL3_MASK    0x1FFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION2_CTRL0    0x0730

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION2_CTRL1    0x0731
#define    RTL8370_VLAN_MEMBER_CONFIGURATION2_CTRL1_MSTI_OFFSET    12
#define    RTL8370_VLAN_MEMBER_CONFIGURATION2_CTRL1_MSTI_MASK    0xF000
#define    RTL8370_VLAN_MEMBER_CONFIGURATION2_CTRL1_FID_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION2_CTRL1_FID_MASK    0xFFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION2_CTRL2    0x0732
#define    RTL8370_VLAN_MEMBER_CONFIGURATION2_CTRL2_METERIDX_OFFSET    6
#define    RTL8370_VLAN_MEMBER_CONFIGURATION2_CTRL2_METERIDX_MASK    0x3FC0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION2_CTRL2_ENVLANPOL_OFFSET    5
#define    RTL8370_VLAN_MEMBER_CONFIGURATION2_CTRL2_ENVLANPOL_MASK    0x20
#define    RTL8370_VLAN_MEMBER_CONFIGURATION2_CTRL2_VBPRI_OFFSET    2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION2_CTRL2_VBPRI_MASK    0x1C
#define    RTL8370_VLAN_MEMBER_CONFIGURATION2_CTRL2_VBPEN_OFFSET    1
#define    RTL8370_VLAN_MEMBER_CONFIGURATION2_CTRL2_VBPEN_MASK    0x2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION2_CTRL2_LUREP_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION2_CTRL2_LUREP_MASK    0x1

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION2_CTRL3    0x0733
#define    RTL8370_VLAN_MEMBER_CONFIGURATION2_CTRL3_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION2_CTRL3_MASK    0x1FFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION3_CTRL0    0x0734

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION3_CTRL1    0x0735
#define    RTL8370_VLAN_MEMBER_CONFIGURATION3_CTRL1_MSTI_OFFSET    12
#define    RTL8370_VLAN_MEMBER_CONFIGURATION3_CTRL1_MSTI_MASK    0xF000
#define    RTL8370_VLAN_MEMBER_CONFIGURATION3_CTRL1_FID_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION3_CTRL1_FID_MASK    0xFFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION3_CTRL2    0x0736
#define    RTL8370_VLAN_MEMBER_CONFIGURATION3_CTRL2_METERIDX_OFFSET    6
#define    RTL8370_VLAN_MEMBER_CONFIGURATION3_CTRL2_METERIDX_MASK    0x3FC0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION3_CTRL2_ENVLANPOL_OFFSET    5
#define    RTL8370_VLAN_MEMBER_CONFIGURATION3_CTRL2_ENVLANPOL_MASK    0x20
#define    RTL8370_VLAN_MEMBER_CONFIGURATION3_CTRL2_VBPRI_OFFSET    2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION3_CTRL2_VBPRI_MASK    0x1C
#define    RTL8370_VLAN_MEMBER_CONFIGURATION3_CTRL2_VBPEN_OFFSET    1
#define    RTL8370_VLAN_MEMBER_CONFIGURATION3_CTRL2_VBPEN_MASK    0x2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION3_CTRL2_LUREP_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION3_CTRL2_LUREP_MASK    0x1

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION3_CTRL3    0x0737
#define    RTL8370_VLAN_MEMBER_CONFIGURATION3_CTRL3_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION3_CTRL3_MASK    0x1FFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION4_CTRL0    0x0738

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION4_CTRL1    0x0739
#define    RTL8370_VLAN_MEMBER_CONFIGURATION4_CTRL1_MSTI_OFFSET    12
#define    RTL8370_VLAN_MEMBER_CONFIGURATION4_CTRL1_MSTI_MASK    0xF000
#define    RTL8370_VLAN_MEMBER_CONFIGURATION4_CTRL1_FID_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION4_CTRL1_FID_MASK    0xFFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION4_CTRL2    0x073a
#define    RTL8370_VLAN_MEMBER_CONFIGURATION4_CTRL2_METERIDX_OFFSET    6
#define    RTL8370_VLAN_MEMBER_CONFIGURATION4_CTRL2_METERIDX_MASK    0x3FC0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION4_CTRL2_ENVLANPOL_OFFSET    5
#define    RTL8370_VLAN_MEMBER_CONFIGURATION4_CTRL2_ENVLANPOL_MASK    0x20
#define    RTL8370_VLAN_MEMBER_CONFIGURATION4_CTRL2_VBPRI_OFFSET    2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION4_CTRL2_VBPRI_MASK    0x1C
#define    RTL8370_VLAN_MEMBER_CONFIGURATION4_CTRL2_VBPEN_OFFSET    1
#define    RTL8370_VLAN_MEMBER_CONFIGURATION4_CTRL2_VBPEN_MASK    0x2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION4_CTRL2_LUREP_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION4_CTRL2_LUREP_MASK    0x1

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION4_CTRL3    0x073b
#define    RTL8370_VLAN_MEMBER_CONFIGURATION4_CTRL3_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION4_CTRL3_MASK    0x1FFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION5_CTRL0    0x073c

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION5_CTRL1    0x073d
#define    RTL8370_VLAN_MEMBER_CONFIGURATION5_CTRL1_MSTI_OFFSET    12
#define    RTL8370_VLAN_MEMBER_CONFIGURATION5_CTRL1_MSTI_MASK    0xF000
#define    RTL8370_VLAN_MEMBER_CONFIGURATION5_CTRL1_FID_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION5_CTRL1_FID_MASK    0xFFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION5_CTRL2    0x073e
#define    RTL8370_VLAN_MEMBER_CONFIGURATION5_CTRL2_METERIDX_OFFSET    6
#define    RTL8370_VLAN_MEMBER_CONFIGURATION5_CTRL2_METERIDX_MASK    0x3FC0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION5_CTRL2_ENVLANPOL_OFFSET    5
#define    RTL8370_VLAN_MEMBER_CONFIGURATION5_CTRL2_ENVLANPOL_MASK    0x20
#define    RTL8370_VLAN_MEMBER_CONFIGURATION5_CTRL2_VBPRI_OFFSET    2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION5_CTRL2_VBPRI_MASK    0x1C
#define    RTL8370_VLAN_MEMBER_CONFIGURATION5_CTRL2_VBPEN_OFFSET    1
#define    RTL8370_VLAN_MEMBER_CONFIGURATION5_CTRL2_VBPEN_MASK    0x2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION5_CTRL2_LUREP_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION5_CTRL2_LUREP_MASK    0x1

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION5_CTRL3    0x073f
#define    RTL8370_VLAN_MEMBER_CONFIGURATION5_CTRL3_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION5_CTRL3_MASK    0x1FFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION6_CTRL0    0x0740

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION6_CTRL1    0x0741
#define    RTL8370_VLAN_MEMBER_CONFIGURATION6_CTRL1_MSTI_OFFSET    12
#define    RTL8370_VLAN_MEMBER_CONFIGURATION6_CTRL1_MSTI_MASK    0xF000
#define    RTL8370_VLAN_MEMBER_CONFIGURATION6_CTRL1_FID_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION6_CTRL1_FID_MASK    0xFFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION6_CTRL2    0x0742
#define    RTL8370_VLAN_MEMBER_CONFIGURATION6_CTRL2_METERIDX_OFFSET    6
#define    RTL8370_VLAN_MEMBER_CONFIGURATION6_CTRL2_METERIDX_MASK    0x3FC0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION6_CTRL2_ENVLANPOL_OFFSET    5
#define    RTL8370_VLAN_MEMBER_CONFIGURATION6_CTRL2_ENVLANPOL_MASK    0x20
#define    RTL8370_VLAN_MEMBER_CONFIGURATION6_CTRL2_VBPRI_OFFSET    2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION6_CTRL2_VBPRI_MASK    0x1C
#define    RTL8370_VLAN_MEMBER_CONFIGURATION6_CTRL2_VBPEN_OFFSET    1
#define    RTL8370_VLAN_MEMBER_CONFIGURATION6_CTRL2_VBPEN_MASK    0x2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION6_CTRL2_LUREP_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION6_CTRL2_LUREP_MASK    0x1

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION6_CTRL3    0x0743
#define    RTL8370_VLAN_MEMBER_CONFIGURATION6_CTRL3_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION6_CTRL3_MASK    0x1FFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION7_CTRL0    0x0744

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION7_CTRL1    0x0745
#define    RTL8370_VLAN_MEMBER_CONFIGURATION7_CTRL1_MSTI_OFFSET    12
#define    RTL8370_VLAN_MEMBER_CONFIGURATION7_CTRL1_MSTI_MASK    0xF000
#define    RTL8370_VLAN_MEMBER_CONFIGURATION7_CTRL1_FID_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION7_CTRL1_FID_MASK    0xFFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION7_CTRL2    0x0746
#define    RTL8370_VLAN_MEMBER_CONFIGURATION7_CTRL2_METERIDX_OFFSET    6
#define    RTL8370_VLAN_MEMBER_CONFIGURATION7_CTRL2_METERIDX_MASK    0x3FC0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION7_CTRL2_ENVLANPOL_OFFSET    5
#define    RTL8370_VLAN_MEMBER_CONFIGURATION7_CTRL2_ENVLANPOL_MASK    0x20
#define    RTL8370_VLAN_MEMBER_CONFIGURATION7_CTRL2_VBPRI_OFFSET    2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION7_CTRL2_VBPRI_MASK    0x1C
#define    RTL8370_VLAN_MEMBER_CONFIGURATION7_CTRL2_VBPEN_OFFSET    1
#define    RTL8370_VLAN_MEMBER_CONFIGURATION7_CTRL2_VBPEN_MASK    0x2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION7_CTRL2_LUREP_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION7_CTRL2_LUREP_MASK    0x1

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION7_CTRL3    0x0747
#define    RTL8370_VLAN_MEMBER_CONFIGURATION7_CTRL3_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION7_CTRL3_MASK    0x1FFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION8_CTRL0    0x0748

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION8_CTRL1    0x0749
#define    RTL8370_VLAN_MEMBER_CONFIGURATION8_CTRL1_MSTI_OFFSET    12
#define    RTL8370_VLAN_MEMBER_CONFIGURATION8_CTRL1_MSTI_MASK    0xF000
#define    RTL8370_VLAN_MEMBER_CONFIGURATION8_CTRL1_FID_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION8_CTRL1_FID_MASK    0xFFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION8_CTRL2    0x074a
#define    RTL8370_VLAN_MEMBER_CONFIGURATION8_CTRL2_METERIDX_OFFSET    6
#define    RTL8370_VLAN_MEMBER_CONFIGURATION8_CTRL2_METERIDX_MASK    0x3FC0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION8_CTRL2_ENVLANPOL_OFFSET    5
#define    RTL8370_VLAN_MEMBER_CONFIGURATION8_CTRL2_ENVLANPOL_MASK    0x20
#define    RTL8370_VLAN_MEMBER_CONFIGURATION8_CTRL2_VBPRI_OFFSET    2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION8_CTRL2_VBPRI_MASK    0x1C
#define    RTL8370_VLAN_MEMBER_CONFIGURATION8_CTRL2_VBPEN_OFFSET    1
#define    RTL8370_VLAN_MEMBER_CONFIGURATION8_CTRL2_VBPEN_MASK    0x2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION8_CTRL2_LUREP_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION8_CTRL2_LUREP_MASK    0x1

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION8_CTRL3    0x074b
#define    RTL8370_VLAN_MEMBER_CONFIGURATION8_CTRL3_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION8_CTRL3_MASK    0x1FFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION9_CTRL0    0x074c

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION9_CTRL1    0x074d
#define    RTL8370_VLAN_MEMBER_CONFIGURATION9_CTRL1_MSTI_OFFSET    12
#define    RTL8370_VLAN_MEMBER_CONFIGURATION9_CTRL1_MSTI_MASK    0xF000
#define    RTL8370_VLAN_MEMBER_CONFIGURATION9_CTRL1_FID_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION9_CTRL1_FID_MASK    0xFFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION9_CTRL2    0x074e
#define    RTL8370_VLAN_MEMBER_CONFIGURATION9_CTRL2_METERIDX_OFFSET    6
#define    RTL8370_VLAN_MEMBER_CONFIGURATION9_CTRL2_METERIDX_MASK    0x3FC0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION9_CTRL2_ENVLANPOL_OFFSET    5
#define    RTL8370_VLAN_MEMBER_CONFIGURATION9_CTRL2_ENVLANPOL_MASK    0x20
#define    RTL8370_VLAN_MEMBER_CONFIGURATION9_CTRL2_VBPRI_OFFSET    2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION9_CTRL2_VBPRI_MASK    0x1C
#define    RTL8370_VLAN_MEMBER_CONFIGURATION9_CTRL2_VBPEN_OFFSET    1
#define    RTL8370_VLAN_MEMBER_CONFIGURATION9_CTRL2_VBPEN_MASK    0x2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION9_CTRL2_LUREP_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION9_CTRL2_LUREP_MASK    0x1

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION9_CTRL3    0x074f
#define    RTL8370_VLAN_MEMBER_CONFIGURATION9_CTRL3_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION9_CTRL3_MASK    0x1FFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION10_CTRL0    0x0750

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION10_CTRL1    0x0751
#define    RTL8370_VLAN_MEMBER_CONFIGURATION10_CTRL1_MSTI_OFFSET    12
#define    RTL8370_VLAN_MEMBER_CONFIGURATION10_CTRL1_MSTI_MASK    0xF000
#define    RTL8370_VLAN_MEMBER_CONFIGURATION10_CTRL1_FID_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION10_CTRL1_FID_MASK    0xFFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION10_CTRL2    0x0752
#define    RTL8370_VLAN_MEMBER_CONFIGURATION10_CTRL2_METERIDX_OFFSET    6
#define    RTL8370_VLAN_MEMBER_CONFIGURATION10_CTRL2_METERIDX_MASK    0x3FC0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION10_CTRL2_ENVLANPOL_OFFSET    5
#define    RTL8370_VLAN_MEMBER_CONFIGURATION10_CTRL2_ENVLANPOL_MASK    0x20
#define    RTL8370_VLAN_MEMBER_CONFIGURATION10_CTRL2_VBPRI_OFFSET    2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION10_CTRL2_VBPRI_MASK    0x1C
#define    RTL8370_VLAN_MEMBER_CONFIGURATION10_CTRL2_VBPEN_OFFSET    1
#define    RTL8370_VLAN_MEMBER_CONFIGURATION10_CTRL2_VBPEN_MASK    0x2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION10_CTRL2_LUREP_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION10_CTRL2_LUREP_MASK    0x1

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION10_CTRL3    0x0753
#define    RTL8370_VLAN_MEMBER_CONFIGURATION10_CTRL3_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION10_CTRL3_MASK    0x1FFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION11_CTRL0    0x0754

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION11_CTRL1    0x0755
#define    RTL8370_VLAN_MEMBER_CONFIGURATION11_CTRL1_MSTI_OFFSET    12
#define    RTL8370_VLAN_MEMBER_CONFIGURATION11_CTRL1_MSTI_MASK    0xF000
#define    RTL8370_VLAN_MEMBER_CONFIGURATION11_CTRL1_FID_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION11_CTRL1_FID_MASK    0xFFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION11_CTRL2    0x0756
#define    RTL8370_VLAN_MEMBER_CONFIGURATION11_CTRL2_METERIDX_OFFSET    6
#define    RTL8370_VLAN_MEMBER_CONFIGURATION11_CTRL2_METERIDX_MASK    0x3FC0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION11_CTRL2_ENVLANPOL_OFFSET    5
#define    RTL8370_VLAN_MEMBER_CONFIGURATION11_CTRL2_ENVLANPOL_MASK    0x20
#define    RTL8370_VLAN_MEMBER_CONFIGURATION11_CTRL2_VBPRI_OFFSET    2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION11_CTRL2_VBPRI_MASK    0x1C
#define    RTL8370_VLAN_MEMBER_CONFIGURATION11_CTRL2_VBPEN_OFFSET    1
#define    RTL8370_VLAN_MEMBER_CONFIGURATION11_CTRL2_VBPEN_MASK    0x2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION11_CTRL2_LUREP_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION11_CTRL2_LUREP_MASK    0x1

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION11_CTRL3    0x0757
#define    RTL8370_VLAN_MEMBER_CONFIGURATION11_CTRL3_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION11_CTRL3_MASK    0x1FFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION12_CTRL0    0x0758

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION12_CTRL1    0x0759
#define    RTL8370_VLAN_MEMBER_CONFIGURATION12_CTRL1_MSTI_OFFSET    12
#define    RTL8370_VLAN_MEMBER_CONFIGURATION12_CTRL1_MSTI_MASK    0xF000
#define    RTL8370_VLAN_MEMBER_CONFIGURATION12_CTRL1_FID_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION12_CTRL1_FID_MASK    0xFFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION12_CTRL2    0x075a
#define    RTL8370_VLAN_MEMBER_CONFIGURATION12_CTRL2_METERIDX_OFFSET    6
#define    RTL8370_VLAN_MEMBER_CONFIGURATION12_CTRL2_METERIDX_MASK    0x3FC0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION12_CTRL2_ENVLANPOL_OFFSET    5
#define    RTL8370_VLAN_MEMBER_CONFIGURATION12_CTRL2_ENVLANPOL_MASK    0x20
#define    RTL8370_VLAN_MEMBER_CONFIGURATION12_CTRL2_VBPRI_OFFSET    2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION12_CTRL2_VBPRI_MASK    0x1C
#define    RTL8370_VLAN_MEMBER_CONFIGURATION12_CTRL2_VBPEN_OFFSET    1
#define    RTL8370_VLAN_MEMBER_CONFIGURATION12_CTRL2_VBPEN_MASK    0x2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION12_CTRL2_LUREP_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION12_CTRL2_LUREP_MASK    0x1

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION12_CTRL3    0x075b
#define    RTL8370_VLAN_MEMBER_CONFIGURATION12_CTRL3_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION12_CTRL3_MASK    0x1FFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION13_CTRL0    0x075c

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION13_CTRL1    0x075d
#define    RTL8370_VLAN_MEMBER_CONFIGURATION13_CTRL1_MSTI_OFFSET    12
#define    RTL8370_VLAN_MEMBER_CONFIGURATION13_CTRL1_MSTI_MASK    0xF000
#define    RTL8370_VLAN_MEMBER_CONFIGURATION13_CTRL1_FID_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION13_CTRL1_FID_MASK    0xFFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION13_CTRL2    0x075e
#define    RTL8370_VLAN_MEMBER_CONFIGURATION13_CTRL2_METERIDX_OFFSET    6
#define    RTL8370_VLAN_MEMBER_CONFIGURATION13_CTRL2_METERIDX_MASK    0x3FC0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION13_CTRL2_ENVLANPOL_OFFSET    5
#define    RTL8370_VLAN_MEMBER_CONFIGURATION13_CTRL2_ENVLANPOL_MASK    0x20
#define    RTL8370_VLAN_MEMBER_CONFIGURATION13_CTRL2_VBPRI_OFFSET    2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION13_CTRL2_VBPRI_MASK    0x1C
#define    RTL8370_VLAN_MEMBER_CONFIGURATION13_CTRL2_VBPEN_OFFSET    1
#define    RTL8370_VLAN_MEMBER_CONFIGURATION13_CTRL2_VBPEN_MASK    0x2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION13_CTRL2_LUREP_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION13_CTRL2_LUREP_MASK    0x1

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION13_CTRL3    0x075f
#define    RTL8370_VLAN_MEMBER_CONFIGURATION13_CTRL3_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION13_CTRL3_MASK    0x1FFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION14_CTRL0    0x0760

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION14_CTRL1    0x0761
#define    RTL8370_VLAN_MEMBER_CONFIGURATION14_CTRL1_MSTI_OFFSET    12
#define    RTL8370_VLAN_MEMBER_CONFIGURATION14_CTRL1_MSTI_MASK    0xF000
#define    RTL8370_VLAN_MEMBER_CONFIGURATION14_CTRL1_FID_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION14_CTRL1_FID_MASK    0xFFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION14_CTRL2    0x0762
#define    RTL8370_VLAN_MEMBER_CONFIGURATION14_CTRL2_METERIDX_OFFSET    6
#define    RTL8370_VLAN_MEMBER_CONFIGURATION14_CTRL2_METERIDX_MASK    0x3FC0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION14_CTRL2_ENVLANPOL_OFFSET    5
#define    RTL8370_VLAN_MEMBER_CONFIGURATION14_CTRL2_ENVLANPOL_MASK    0x20
#define    RTL8370_VLAN_MEMBER_CONFIGURATION14_CTRL2_VBPRI_OFFSET    2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION14_CTRL2_VBPRI_MASK    0x1C
#define    RTL8370_VLAN_MEMBER_CONFIGURATION14_CTRL2_VBPEN_OFFSET    1
#define    RTL8370_VLAN_MEMBER_CONFIGURATION14_CTRL2_VBPEN_MASK    0x2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION14_CTRL2_LUREP_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION14_CTRL2_LUREP_MASK    0x1

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION14_CTRL3    0x0763
#define    RTL8370_VLAN_MEMBER_CONFIGURATION14_CTRL3_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION14_CTRL3_MASK    0x1FFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION15_CTRL0    0x0764

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION15_CTRL1    0x0765
#define    RTL8370_VLAN_MEMBER_CONFIGURATION15_CTRL1_MSTI_OFFSET    12
#define    RTL8370_VLAN_MEMBER_CONFIGURATION15_CTRL1_MSTI_MASK    0xF000
#define    RTL8370_VLAN_MEMBER_CONFIGURATION15_CTRL1_FID_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION15_CTRL1_FID_MASK    0xFFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION15_CTRL2    0x0766
#define    RTL8370_VLAN_MEMBER_CONFIGURATION15_CTRL2_METERIDX_OFFSET    6
#define    RTL8370_VLAN_MEMBER_CONFIGURATION15_CTRL2_METERIDX_MASK    0x3FC0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION15_CTRL2_ENVLANPOL_OFFSET    5
#define    RTL8370_VLAN_MEMBER_CONFIGURATION15_CTRL2_ENVLANPOL_MASK    0x20
#define    RTL8370_VLAN_MEMBER_CONFIGURATION15_CTRL2_VBPRI_OFFSET    2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION15_CTRL2_VBPRI_MASK    0x1C
#define    RTL8370_VLAN_MEMBER_CONFIGURATION15_CTRL2_VBPEN_OFFSET    1
#define    RTL8370_VLAN_MEMBER_CONFIGURATION15_CTRL2_VBPEN_MASK    0x2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION15_CTRL2_LUREP_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION15_CTRL2_LUREP_MASK    0x1

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION15_CTRL3    0x0767
#define    RTL8370_VLAN_MEMBER_CONFIGURATION15_CTRL3_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION15_CTRL3_MASK    0x1FFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION16_CTRL0    0x0768

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION16_CTRL1    0x0769
#define    RTL8370_VLAN_MEMBER_CONFIGURATION16_CTRL1_MSTI_OFFSET    12
#define    RTL8370_VLAN_MEMBER_CONFIGURATION16_CTRL1_MSTI_MASK    0xF000
#define    RTL8370_VLAN_MEMBER_CONFIGURATION16_CTRL1_FID_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION16_CTRL1_FID_MASK    0xFFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION16_CTRL2    0x076a
#define    RTL8370_VLAN_MEMBER_CONFIGURATION16_CTRL2_METERIDX_OFFSET    6
#define    RTL8370_VLAN_MEMBER_CONFIGURATION16_CTRL2_METERIDX_MASK    0x3FC0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION16_CTRL2_ENVLANPOL_OFFSET    5
#define    RTL8370_VLAN_MEMBER_CONFIGURATION16_CTRL2_ENVLANPOL_MASK    0x20
#define    RTL8370_VLAN_MEMBER_CONFIGURATION16_CTRL2_VBPRI_OFFSET    2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION16_CTRL2_VBPRI_MASK    0x1C
#define    RTL8370_VLAN_MEMBER_CONFIGURATION16_CTRL2_VBPEN_OFFSET    1
#define    RTL8370_VLAN_MEMBER_CONFIGURATION16_CTRL2_VBPEN_MASK    0x2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION16_CTRL2_LUREP_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION16_CTRL2_LUREP_MASK    0x1

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION16_CTRL3    0x076b
#define    RTL8370_VLAN_MEMBER_CONFIGURATION16_CTRL3_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION16_CTRL3_MASK    0x1FFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION17_CTRL0    0x076c

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION17_CTRL1    0x076d
#define    RTL8370_VLAN_MEMBER_CONFIGURATION17_CTRL1_MSTI_OFFSET    12
#define    RTL8370_VLAN_MEMBER_CONFIGURATION17_CTRL1_MSTI_MASK    0xF000
#define    RTL8370_VLAN_MEMBER_CONFIGURATION17_CTRL1_FID_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION17_CTRL1_FID_MASK    0xFFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION17_CTRL2    0x076e
#define    RTL8370_VLAN_MEMBER_CONFIGURATION17_CTRL2_METERIDX_OFFSET    6
#define    RTL8370_VLAN_MEMBER_CONFIGURATION17_CTRL2_METERIDX_MASK    0x3FC0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION17_CTRL2_ENVLANPOL_OFFSET    5
#define    RTL8370_VLAN_MEMBER_CONFIGURATION17_CTRL2_ENVLANPOL_MASK    0x20
#define    RTL8370_VLAN_MEMBER_CONFIGURATION17_CTRL2_VBPRI_OFFSET    2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION17_CTRL2_VBPRI_MASK    0x1C
#define    RTL8370_VLAN_MEMBER_CONFIGURATION17_CTRL2_VBPEN_OFFSET    1
#define    RTL8370_VLAN_MEMBER_CONFIGURATION17_CTRL2_VBPEN_MASK    0x2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION17_CTRL2_LUREP_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION17_CTRL2_LUREP_MASK    0x1

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION17_CTRL3    0x076f
#define    RTL8370_VLAN_MEMBER_CONFIGURATION17_CTRL3_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION17_CTRL3_MASK    0x1FFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION18_CTRL0    0x0770

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION18_CTRL1    0x0771
#define    RTL8370_VLAN_MEMBER_CONFIGURATION18_CTRL1_MSTI_OFFSET    12
#define    RTL8370_VLAN_MEMBER_CONFIGURATION18_CTRL1_MSTI_MASK    0xF000
#define    RTL8370_VLAN_MEMBER_CONFIGURATION18_CTRL1_FID_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION18_CTRL1_FID_MASK    0xFFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION18_CTRL2    0x0772
#define    RTL8370_VLAN_MEMBER_CONFIGURATION18_CTRL2_METERIDX_OFFSET    6
#define    RTL8370_VLAN_MEMBER_CONFIGURATION18_CTRL2_METERIDX_MASK    0x3FC0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION18_CTRL2_ENVLANPOL_OFFSET    5
#define    RTL8370_VLAN_MEMBER_CONFIGURATION18_CTRL2_ENVLANPOL_MASK    0x20
#define    RTL8370_VLAN_MEMBER_CONFIGURATION18_CTRL2_VBPRI_OFFSET    2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION18_CTRL2_VBPRI_MASK    0x1C
#define    RTL8370_VLAN_MEMBER_CONFIGURATION18_CTRL2_VBPEN_OFFSET    1
#define    RTL8370_VLAN_MEMBER_CONFIGURATION18_CTRL2_VBPEN_MASK    0x2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION18_CTRL2_LUREP_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION18_CTRL2_LUREP_MASK    0x1

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION18_CTRL3    0x0773
#define    RTL8370_VLAN_MEMBER_CONFIGURATION18_CTRL3_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION18_CTRL3_MASK    0x1FFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION19_CTRL0    0x0774

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION19_CTRL1    0x0775
#define    RTL8370_VLAN_MEMBER_CONFIGURATION19_CTRL1_MSTI_OFFSET    12
#define    RTL8370_VLAN_MEMBER_CONFIGURATION19_CTRL1_MSTI_MASK    0xF000
#define    RTL8370_VLAN_MEMBER_CONFIGURATION19_CTRL1_FID_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION19_CTRL1_FID_MASK    0xFFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION19_CTRL2    0x0776
#define    RTL8370_VLAN_MEMBER_CONFIGURATION19_CTRL2_METERIDX_OFFSET    6
#define    RTL8370_VLAN_MEMBER_CONFIGURATION19_CTRL2_METERIDX_MASK    0x3FC0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION19_CTRL2_ENVLANPOL_OFFSET    5
#define    RTL8370_VLAN_MEMBER_CONFIGURATION19_CTRL2_ENVLANPOL_MASK    0x20
#define    RTL8370_VLAN_MEMBER_CONFIGURATION19_CTRL2_VBPRI_OFFSET    2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION19_CTRL2_VBPRI_MASK    0x1C
#define    RTL8370_VLAN_MEMBER_CONFIGURATION19_CTRL2_VBPEN_OFFSET    1
#define    RTL8370_VLAN_MEMBER_CONFIGURATION19_CTRL2_VBPEN_MASK    0x2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION19_CTRL2_LUREP_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION19_CTRL2_LUREP_MASK    0x1

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION19_CTRL3    0x0777
#define    RTL8370_VLAN_MEMBER_CONFIGURATION19_CTRL3_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION19_CTRL3_MASK    0x1FFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION20_CTRL0    0x0778

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION20_CTRL1    0x0779
#define    RTL8370_VLAN_MEMBER_CONFIGURATION20_CTRL1_MSTI_OFFSET    12
#define    RTL8370_VLAN_MEMBER_CONFIGURATION20_CTRL1_MSTI_MASK    0xF000
#define    RTL8370_VLAN_MEMBER_CONFIGURATION20_CTRL1_FID_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION20_CTRL1_FID_MASK    0xFFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION20_CTRL2    0x077a
#define    RTL8370_VLAN_MEMBER_CONFIGURATION20_CTRL2_METERIDX_OFFSET    6
#define    RTL8370_VLAN_MEMBER_CONFIGURATION20_CTRL2_METERIDX_MASK    0x3FC0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION20_CTRL2_ENVLANPOL_OFFSET    5
#define    RTL8370_VLAN_MEMBER_CONFIGURATION20_CTRL2_ENVLANPOL_MASK    0x20
#define    RTL8370_VLAN_MEMBER_CONFIGURATION20_CTRL2_VBPRI_OFFSET    2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION20_CTRL2_VBPRI_MASK    0x1C
#define    RTL8370_VLAN_MEMBER_CONFIGURATION20_CTRL2_VBPEN_OFFSET    1
#define    RTL8370_VLAN_MEMBER_CONFIGURATION20_CTRL2_VBPEN_MASK    0x2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION20_CTRL2_LUREP_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION20_CTRL2_LUREP_MASK    0x1

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION20_CTRL3    0x077b
#define    RTL8370_VLAN_MEMBER_CONFIGURATION20_CTRL3_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION20_CTRL3_MASK    0x1FFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION21_CTRL0    0x077c

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION21_CTRL1    0x077d
#define    RTL8370_VLAN_MEMBER_CONFIGURATION21_CTRL1_MSTI_OFFSET    12
#define    RTL8370_VLAN_MEMBER_CONFIGURATION21_CTRL1_MSTI_MASK    0xF000
#define    RTL8370_VLAN_MEMBER_CONFIGURATION21_CTRL1_FID_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION21_CTRL1_FID_MASK    0xFFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION21_CTRL2    0x077e
#define    RTL8370_VLAN_MEMBER_CONFIGURATION21_CTRL2_METERIDX_OFFSET    6
#define    RTL8370_VLAN_MEMBER_CONFIGURATION21_CTRL2_METERIDX_MASK    0x3FC0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION21_CTRL2_ENVLANPOL_OFFSET    5
#define    RTL8370_VLAN_MEMBER_CONFIGURATION21_CTRL2_ENVLANPOL_MASK    0x20
#define    RTL8370_VLAN_MEMBER_CONFIGURATION21_CTRL2_VBPRI_OFFSET    2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION21_CTRL2_VBPRI_MASK    0x1C
#define    RTL8370_VLAN_MEMBER_CONFIGURATION21_CTRL2_VBPEN_OFFSET    1
#define    RTL8370_VLAN_MEMBER_CONFIGURATION21_CTRL2_VBPEN_MASK    0x2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION21_CTRL2_LUREP_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION21_CTRL2_LUREP_MASK    0x1

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION21_CTRL3    0x077f
#define    RTL8370_VLAN_MEMBER_CONFIGURATION21_CTRL3_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION21_CTRL3_MASK    0x1FFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION22_CTRL0    0x0780

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION22_CTRL1    0x0781
#define    RTL8370_VLAN_MEMBER_CONFIGURATION22_CTRL1_MSTI_OFFSET    12
#define    RTL8370_VLAN_MEMBER_CONFIGURATION22_CTRL1_MSTI_MASK    0xF000
#define    RTL8370_VLAN_MEMBER_CONFIGURATION22_CTRL1_FID_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION22_CTRL1_FID_MASK    0xFFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION22_CTRL2    0x0782
#define    RTL8370_VLAN_MEMBER_CONFIGURATION22_CTRL2_METERIDX_OFFSET    6
#define    RTL8370_VLAN_MEMBER_CONFIGURATION22_CTRL2_METERIDX_MASK    0x3FC0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION22_CTRL2_ENVLANPOL_OFFSET    5
#define    RTL8370_VLAN_MEMBER_CONFIGURATION22_CTRL2_ENVLANPOL_MASK    0x20
#define    RTL8370_VLAN_MEMBER_CONFIGURATION22_CTRL2_VBPRI_OFFSET    2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION22_CTRL2_VBPRI_MASK    0x1C
#define    RTL8370_VLAN_MEMBER_CONFIGURATION22_CTRL2_VBPEN_OFFSET    1
#define    RTL8370_VLAN_MEMBER_CONFIGURATION22_CTRL2_VBPEN_MASK    0x2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION22_CTRL2_LUREP_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION22_CTRL2_LUREP_MASK    0x1

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION22_CTRL3    0x0783
#define    RTL8370_VLAN_MEMBER_CONFIGURATION22_CTRL3_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION22_CTRL3_MASK    0x1FFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION23_CTRL0    0x0784

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION23_CTRL1    0x0785
#define    RTL8370_VLAN_MEMBER_CONFIGURATION23_CTRL1_MSTI_OFFSET    12
#define    RTL8370_VLAN_MEMBER_CONFIGURATION23_CTRL1_MSTI_MASK    0xF000
#define    RTL8370_VLAN_MEMBER_CONFIGURATION23_CTRL1_FID_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION23_CTRL1_FID_MASK    0xFFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION23_CTRL2    0x0786
#define    RTL8370_VLAN_MEMBER_CONFIGURATION23_CTRL2_METERIDX_OFFSET    6
#define    RTL8370_VLAN_MEMBER_CONFIGURATION23_CTRL2_METERIDX_MASK    0x3FC0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION23_CTRL2_ENVLANPOL_OFFSET    5
#define    RTL8370_VLAN_MEMBER_CONFIGURATION23_CTRL2_ENVLANPOL_MASK    0x20
#define    RTL8370_VLAN_MEMBER_CONFIGURATION23_CTRL2_VBPRI_OFFSET    2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION23_CTRL2_VBPRI_MASK    0x1C
#define    RTL8370_VLAN_MEMBER_CONFIGURATION23_CTRL2_VBPEN_OFFSET    1
#define    RTL8370_VLAN_MEMBER_CONFIGURATION23_CTRL2_VBPEN_MASK    0x2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION23_CTRL2_LUREP_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION23_CTRL2_LUREP_MASK    0x1

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION23_CTRL3    0x0787
#define    RTL8370_VLAN_MEMBER_CONFIGURATION23_CTRL3_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION23_CTRL3_MASK    0x1FFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION24_CTRL0    0x0788

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION24_CTRL1    0x0789
#define    RTL8370_VLAN_MEMBER_CONFIGURATION24_CTRL1_MSTI_OFFSET    12
#define    RTL8370_VLAN_MEMBER_CONFIGURATION24_CTRL1_MSTI_MASK    0xF000
#define    RTL8370_VLAN_MEMBER_CONFIGURATION24_CTRL1_FID_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION24_CTRL1_FID_MASK    0xFFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION24_CTRL2    0x078a
#define    RTL8370_VLAN_MEMBER_CONFIGURATION24_CTRL2_METERIDX_OFFSET    6
#define    RTL8370_VLAN_MEMBER_CONFIGURATION24_CTRL2_METERIDX_MASK    0x3FC0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION24_CTRL2_ENVLANPOL_OFFSET    5
#define    RTL8370_VLAN_MEMBER_CONFIGURATION24_CTRL2_ENVLANPOL_MASK    0x20
#define    RTL8370_VLAN_MEMBER_CONFIGURATION24_CTRL2_VBPRI_OFFSET    2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION24_CTRL2_VBPRI_MASK    0x1C
#define    RTL8370_VLAN_MEMBER_CONFIGURATION24_CTRL2_VBPEN_OFFSET    1
#define    RTL8370_VLAN_MEMBER_CONFIGURATION24_CTRL2_VBPEN_MASK    0x2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION24_CTRL2_LUREP_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION24_CTRL2_LUREP_MASK    0x1

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION24_CTRL3    0x078b
#define    RTL8370_VLAN_MEMBER_CONFIGURATION24_CTRL3_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION24_CTRL3_MASK    0x1FFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION25_CTRL0    0x078c

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION25_CTRL1    0x078d
#define    RTL8370_VLAN_MEMBER_CONFIGURATION25_CTRL1_MSTI_OFFSET    12
#define    RTL8370_VLAN_MEMBER_CONFIGURATION25_CTRL1_MSTI_MASK    0xF000
#define    RTL8370_VLAN_MEMBER_CONFIGURATION25_CTRL1_FID_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION25_CTRL1_FID_MASK    0xFFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION25_CTRL2    0x078e
#define    RTL8370_VLAN_MEMBER_CONFIGURATION25_CTRL2_METERIDX_OFFSET    6
#define    RTL8370_VLAN_MEMBER_CONFIGURATION25_CTRL2_METERIDX_MASK    0x3FC0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION25_CTRL2_ENVLANPOL_OFFSET    5
#define    RTL8370_VLAN_MEMBER_CONFIGURATION25_CTRL2_ENVLANPOL_MASK    0x20
#define    RTL8370_VLAN_MEMBER_CONFIGURATION25_CTRL2_VBPRI_OFFSET    2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION25_CTRL2_VBPRI_MASK    0x1C
#define    RTL8370_VLAN_MEMBER_CONFIGURATION25_CTRL2_VBPEN_OFFSET    1
#define    RTL8370_VLAN_MEMBER_CONFIGURATION25_CTRL2_VBPEN_MASK    0x2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION25_CTRL2_LUREP_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION25_CTRL2_LUREP_MASK    0x1

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION25_CTRL3    0x078f
#define    RTL8370_VLAN_MEMBER_CONFIGURATION25_CTRL3_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION25_CTRL3_MASK    0x1FFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION26_CTRL0    0x0790

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION26_CTRL1    0x0791
#define    RTL8370_VLAN_MEMBER_CONFIGURATION26_CTRL1_MSTI_OFFSET    12
#define    RTL8370_VLAN_MEMBER_CONFIGURATION26_CTRL1_MSTI_MASK    0xF000
#define    RTL8370_VLAN_MEMBER_CONFIGURATION26_CTRL1_FID_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION26_CTRL1_FID_MASK    0xFFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION26_CTRL2    0x0792
#define    RTL8370_VLAN_MEMBER_CONFIGURATION26_CTRL2_METERIDX_OFFSET    6
#define    RTL8370_VLAN_MEMBER_CONFIGURATION26_CTRL2_METERIDX_MASK    0x3FC0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION26_CTRL2_ENVLANPOL_OFFSET    5
#define    RTL8370_VLAN_MEMBER_CONFIGURATION26_CTRL2_ENVLANPOL_MASK    0x20
#define    RTL8370_VLAN_MEMBER_CONFIGURATION26_CTRL2_VBPRI_OFFSET    2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION26_CTRL2_VBPRI_MASK    0x1C
#define    RTL8370_VLAN_MEMBER_CONFIGURATION26_CTRL2_VBPEN_OFFSET    1
#define    RTL8370_VLAN_MEMBER_CONFIGURATION26_CTRL2_VBPEN_MASK    0x2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION26_CTRL2_LUREP_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION26_CTRL2_LUREP_MASK    0x1

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION26_CTRL3    0x0793
#define    RTL8370_VLAN_MEMBER_CONFIGURATION26_CTRL3_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION26_CTRL3_MASK    0x1FFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION27_CTRL0    0x0794

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION27_CTRL1    0x0795
#define    RTL8370_VLAN_MEMBER_CONFIGURATION27_CTRL1_MSTI_OFFSET    12
#define    RTL8370_VLAN_MEMBER_CONFIGURATION27_CTRL1_MSTI_MASK    0xF000
#define    RTL8370_VLAN_MEMBER_CONFIGURATION27_CTRL1_FID_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION27_CTRL1_FID_MASK    0xFFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION27_CTRL2    0x0796
#define    RTL8370_VLAN_MEMBER_CONFIGURATION27_CTRL2_METERIDX_OFFSET    6
#define    RTL8370_VLAN_MEMBER_CONFIGURATION27_CTRL2_METERIDX_MASK    0x3FC0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION27_CTRL2_ENVLANPOL_OFFSET    5
#define    RTL8370_VLAN_MEMBER_CONFIGURATION27_CTRL2_ENVLANPOL_MASK    0x20
#define    RTL8370_VLAN_MEMBER_CONFIGURATION27_CTRL2_VBPRI_OFFSET    2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION27_CTRL2_VBPRI_MASK    0x1C
#define    RTL8370_VLAN_MEMBER_CONFIGURATION27_CTRL2_VBPEN_OFFSET    1
#define    RTL8370_VLAN_MEMBER_CONFIGURATION27_CTRL2_VBPEN_MASK    0x2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION27_CTRL2_LUREP_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION27_CTRL2_LUREP_MASK    0x1

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION27_CTRL3    0x0797
#define    RTL8370_VLAN_MEMBER_CONFIGURATION27_CTRL3_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION27_CTRL3_MASK    0x1FFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION28_CTRL0    0x0798

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION28_CTRL1    0x0799
#define    RTL8370_VLAN_MEMBER_CONFIGURATION28_CTRL1_MSTI_OFFSET    12
#define    RTL8370_VLAN_MEMBER_CONFIGURATION28_CTRL1_MSTI_MASK    0xF000
#define    RTL8370_VLAN_MEMBER_CONFIGURATION28_CTRL1_FID_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION28_CTRL1_FID_MASK    0xFFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION28_CTRL2    0x079a
#define    RTL8370_VLAN_MEMBER_CONFIGURATION28_CTRL2_METERIDX_OFFSET    6
#define    RTL8370_VLAN_MEMBER_CONFIGURATION28_CTRL2_METERIDX_MASK    0x3FC0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION28_CTRL2_ENVLANPOL_OFFSET    5
#define    RTL8370_VLAN_MEMBER_CONFIGURATION28_CTRL2_ENVLANPOL_MASK    0x20
#define    RTL8370_VLAN_MEMBER_CONFIGURATION28_CTRL2_VBPRI_OFFSET    2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION28_CTRL2_VBPRI_MASK    0x1C
#define    RTL8370_VLAN_MEMBER_CONFIGURATION28_CTRL2_VBPEN_OFFSET    1
#define    RTL8370_VLAN_MEMBER_CONFIGURATION28_CTRL2_VBPEN_MASK    0x2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION28_CTRL2_LUREP_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION28_CTRL2_LUREP_MASK    0x1

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION28_CTRL3    0x079b
#define    RTL8370_VLAN_MEMBER_CONFIGURATION28_CTRL3_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION28_CTRL3_MASK    0x1FFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION29_CTRL0    0x079c

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION29_CTRL1    0x079d
#define    RTL8370_VLAN_MEMBER_CONFIGURATION29_CTRL1_MSTI_OFFSET    12
#define    RTL8370_VLAN_MEMBER_CONFIGURATION29_CTRL1_MSTI_MASK    0xF000
#define    RTL8370_VLAN_MEMBER_CONFIGURATION29_CTRL1_FID_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION29_CTRL1_FID_MASK    0xFFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION29_CTRL2    0x079e
#define    RTL8370_VLAN_MEMBER_CONFIGURATION29_CTRL2_METERIDX_OFFSET    6
#define    RTL8370_VLAN_MEMBER_CONFIGURATION29_CTRL2_METERIDX_MASK    0x3FC0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION29_CTRL2_ENVLANPOL_OFFSET    5
#define    RTL8370_VLAN_MEMBER_CONFIGURATION29_CTRL2_ENVLANPOL_MASK    0x20
#define    RTL8370_VLAN_MEMBER_CONFIGURATION29_CTRL2_VBPRI_OFFSET    2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION29_CTRL2_VBPRI_MASK    0x1C
#define    RTL8370_VLAN_MEMBER_CONFIGURATION29_CTRL2_VBPEN_OFFSET    1
#define    RTL8370_VLAN_MEMBER_CONFIGURATION29_CTRL2_VBPEN_MASK    0x2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION29_CTRL2_LUREP_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION29_CTRL2_LUREP_MASK    0x1

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION29_CTRL3    0x079f
#define    RTL8370_VLAN_MEMBER_CONFIGURATION29_CTRL3_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION29_CTRL3_MASK    0x1FFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION30_CTRL0    0x07a0

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION30_CTRL1    0x07a1
#define    RTL8370_VLAN_MEMBER_CONFIGURATION30_CTRL1_MSTI_OFFSET    12
#define    RTL8370_VLAN_MEMBER_CONFIGURATION30_CTRL1_MSTI_MASK    0xF000
#define    RTL8370_VLAN_MEMBER_CONFIGURATION30_CTRL1_FID_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION30_CTRL1_FID_MASK    0xFFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION30_CTRL2    0x07a2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION30_CTRL2_METERIDX_OFFSET    6
#define    RTL8370_VLAN_MEMBER_CONFIGURATION30_CTRL2_METERIDX_MASK    0x3FC0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION30_CTRL2_ENVLANPOL_OFFSET    5
#define    RTL8370_VLAN_MEMBER_CONFIGURATION30_CTRL2_ENVLANPOL_MASK    0x20
#define    RTL8370_VLAN_MEMBER_CONFIGURATION30_CTRL2_VBPRI_OFFSET    2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION30_CTRL2_VBPRI_MASK    0x1C
#define    RTL8370_VLAN_MEMBER_CONFIGURATION30_CTRL2_VBPEN_OFFSET    1
#define    RTL8370_VLAN_MEMBER_CONFIGURATION30_CTRL2_VBPEN_MASK    0x2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION30_CTRL2_LUREP_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION30_CTRL2_LUREP_MASK    0x1

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION30_CTRL3    0x07a3
#define    RTL8370_VLAN_MEMBER_CONFIGURATION30_CTRL3_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION30_CTRL3_MASK    0x1FFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION31_CTRL0    0x07a4

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION31_CTRL1    0x07a5
#define    RTL8370_VLAN_MEMBER_CONFIGURATION31_CTRL1_MSTI_OFFSET    12
#define    RTL8370_VLAN_MEMBER_CONFIGURATION31_CTRL1_MSTI_MASK    0xF000
#define    RTL8370_VLAN_MEMBER_CONFIGURATION31_CTRL1_FID_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION31_CTRL1_FID_MASK    0xFFF

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION31_CTRL2    0x07a6
#define    RTL8370_VLAN_MEMBER_CONFIGURATION31_CTRL2_METERIDX_OFFSET    6
#define    RTL8370_VLAN_MEMBER_CONFIGURATION31_CTRL2_METERIDX_MASK    0x3FC0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION31_CTRL2_ENVLANPOL_OFFSET    5
#define    RTL8370_VLAN_MEMBER_CONFIGURATION31_CTRL2_ENVLANPOL_MASK    0x20
#define    RTL8370_VLAN_MEMBER_CONFIGURATION31_CTRL2_VBPRI_OFFSET    2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION31_CTRL2_VBPRI_MASK    0x1C
#define    RTL8370_VLAN_MEMBER_CONFIGURATION31_CTRL2_VBPEN_OFFSET    1
#define    RTL8370_VLAN_MEMBER_CONFIGURATION31_CTRL2_VBPEN_MASK    0x2
#define    RTL8370_VLAN_MEMBER_CONFIGURATION31_CTRL2_LUREP_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION31_CTRL2_LUREP_MASK    0x1

#define    RTL8370_REG_VLAN_MEMBER_CONFIGURATION31_CTRL3    0x07a7
#define    RTL8370_VLAN_MEMBER_CONFIGURATION31_CTRL3_OFFSET    0
#define    RTL8370_VLAN_MEMBER_CONFIGURATION31_CTRL3_MASK    0x1FFF

#define    RTL8370_REG_VLAN_CTRL    0x07a8
#define    RTL8370_VLAN_CTRL_OFFSET    0
#define    RTL8370_VLAN_CTRL_MASK    0x1

#define    RTL8370_REG_VLAN_INGRESS    0x07a9

#define    RTL8370_REG_VLAN_ACCEPT_FRAME_TYPE_CTRL0    0x07aa
#define    RTL8370_VLAN_PORT7_FRAME_TYPE_OFFSET    14
#define    RTL8370_VLAN_PORT7_FRAME_TYPE_MASK    0xC000
#define    RTL8370_VLAN_PORT6_FRAME_TYPE_OFFSET    12
#define    RTL8370_VLAN_PORT6_FRAME_TYPE_MASK    0x3000
#define    RTL8370_VLAN_PORT5_FRAME_TYPE_OFFSET    10
#define    RTL8370_VLAN_PORT5_FRAME_TYPE_MASK    0xC00
#define    RTL8370_VLAN_PORT4_FRAME_TYPE_OFFSET    8
#define    RTL8370_VLAN_PORT4_FRAME_TYPE_MASK    0x300
#define    RTL8370_VLAN_PORT3_FRAME_TYPE_OFFSET    6
#define    RTL8370_VLAN_PORT3_FRAME_TYPE_MASK    0xC0
#define    RTL8370_VLAN_PORT2_FRAME_TYPE_OFFSET    4
#define    RTL8370_VLAN_PORT2_FRAME_TYPE_MASK    0x30
#define    RTL8370_VLAN_PORT1_FRAME_TYPE_OFFSET    2
#define    RTL8370_VLAN_PORT1_FRAME_TYPE_MASK    0xC
#define    RTL8370_VLAN_PORT0_FRAME_TYPE_OFFSET    0
#define    RTL8370_VLAN_PORT0_FRAME_TYPE_MASK    0x3

#define    RTL8370_REG_VLAN_ACCEPT_FRAME_TYPE_CTRL1    0x07ab
#define    RTL8370_VLAN_PORT15_FRAME_TYPE_OFFSET    14
#define    RTL8370_VLAN_PORT15_FRAME_TYPE_MASK    0xC000
#define    RTL8370_VLAN_PORT14_FRAME_TYPE_OFFSET    12
#define    RTL8370_VLAN_PORT14_FRAME_TYPE_MASK    0x3000
#define    RTL8370_VLAN_PORT13_FRAME_TYPE_OFFSET    10
#define    RTL8370_VLAN_PORT13_FRAME_TYPE_MASK    0xC00
#define    RTL8370_VLAN_PORT12_FRAME_TYPE_OFFSET    8
#define    RTL8370_VLAN_PORT12_FRAME_TYPE_MASK    0x300
#define    RTL8370_VLAN_PORT11_FRAME_TYPE_OFFSET    6
#define    RTL8370_VLAN_PORT11_FRAME_TYPE_MASK    0xC0
#define    RTL8370_VLAN_PORT10_FRAME_TYPE_OFFSET    4
#define    RTL8370_VLAN_PORT10_FRAME_TYPE_MASK    0x30
#define    RTL8370_VLAN_PORT9_FRAME_TYPE_OFFSET    2
#define    RTL8370_VLAN_PORT9_FRAME_TYPE_MASK    0xC
#define    RTL8370_VLAN_PORT8_FRAME_TYPE_OFFSET    0
#define    RTL8370_VLAN_PORT8_FRAME_TYPE_MASK    0x3

#define    RTL8370_REG_PORT_PBFIDEN    0x07ac

#define    RTL8370_REG_PORT0_PBFID    0x07ad
#define    RTL8370_PORT0_PBFID_OFFSET    0
#define    RTL8370_PORT0_PBFID_MASK    0xFFF

#define    RTL8370_REG_PORT1_PBFID    0x07ae
#define    RTL8370_PORT1_PBFID_OFFSET    0
#define    RTL8370_PORT1_PBFID_MASK    0xFFF

#define    RTL8370_REG_PORT2_PBFID    0x07af
#define    RTL8370_PORT2_PBFID_OFFSET    0
#define    RTL8370_PORT2_PBFID_MASK    0xFFF

#define    RTL8370_REG_PORT3_PBFID    0x07b0
#define    RTL8370_PORT3_PBFID_OFFSET    0
#define    RTL8370_PORT3_PBFID_MASK    0xFFF

#define    RTL8370_REG_PORT4_PBFID    0x07b1
#define    RTL8370_PORT4_PBFID_OFFSET    0
#define    RTL8370_PORT4_PBFID_MASK    0xFFF

#define    RTL8370_REG_PORT5_PBFID    0x07b2
#define    RTL8370_PORT5_PBFID_OFFSET    0
#define    RTL8370_PORT5_PBFID_MASK    0xFFF

#define    RTL8370_REG_PORT6_PBFID    0x07b3
#define    RTL8370_PORT6_PBFID_OFFSET    0
#define    RTL8370_PORT6_PBFID_MASK    0xFFF

#define    RTL8370_REG_PORT7_PBFID    0x07b4
#define    RTL8370_PORT7_PBFID_OFFSET    0
#define    RTL8370_PORT7_PBFID_MASK    0xFFF

#define    RTL8370_REG_PORT8_PBFID    0x07b5
#define    RTL8370_PORT8_PBFID_OFFSET    0
#define    RTL8370_PORT8_PBFID_MASK    0xFFF

#define    RTL8370_REG_PORT9_PBFID    0x07b6
#define    RTL8370_PORT9_PBFID_OFFSET    0
#define    RTL8370_PORT9_PBFID_MASK    0xFFF

#define    RTL8370_REG_PORT10_PBFID    0x07b7
#define    RTL8370_PORT10_PBFID_OFFSET    0
#define    RTL8370_PORT10_PBFID_MASK    0xFFF

#define    RTL8370_REG_PORT11_PBFID    0x07b8
#define    RTL8370_PORT11_PBFID_OFFSET    0
#define    RTL8370_PORT11_PBFID_MASK    0xFFF

#define    RTL8370_REG_PORT12_PBFID    0x07b9
#define    RTL8370_PORT12_PBFID_OFFSET    0
#define    RTL8370_PORT12_PBFID_MASK    0xFFF

#define    RTL8370_REG_PORT13_PBFID    0x07ba
#define    RTL8370_PORT13_PBFID_OFFSET    0
#define    RTL8370_PORT13_PBFID_MASK    0xFFF

#define    RTL8370_REG_PORT14_PBFID    0x07bb
#define    RTL8370_PORT14_PBFID_OFFSET    0
#define    RTL8370_PORT14_PBFID_MASK    0xFFF

#define    RTL8370_REG_PORT15_PBFID    0x07bc
#define    RTL8370_PORT15_PBFID_OFFSET    0
#define    RTL8370_PORT15_PBFID_MASK    0xFFF

/* (16'h0800) dpm_reg */

#define    RTL8370_REG_RMA_CTRL00    0x0800
#define    RTL8370_RMA_CTRL00_OPERATION_OFFSET    7
#define    RTL8370_RMA_CTRL00_OPERATION_MASK    0x180
#define    RTL8370_RMA_CTRL00_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8370_RMA_CTRL00_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8370_RMA_CTRL00_TRAP_PRIORITY_OFFSET    3
#define    RTL8370_RMA_CTRL00_TRAP_PRIORITY_MASK    0x38
#define    RTL8370_RMA_CTRL00_KEEP_FORMAT_OFFSET    2
#define    RTL8370_RMA_CTRL00_KEEP_FORMAT_MASK    0x4
#define    RTL8370_RMA_CTRL00_VLAN_LEAKY_OFFSET    1
#define    RTL8370_RMA_CTRL00_VLAN_LEAKY_MASK    0x2
#define    RTL8370_RMA_CTRL00_PORTISO_LEAKY_OFFSET    0
#define    RTL8370_RMA_CTRL00_PORTISO_LEAKY_MASK    0x1

#define    RTL8370_REG_RMA_CTRL01    0x0801
#define    RTL8370_RMA_CTRL01_OPERATION_OFFSET    7
#define    RTL8370_RMA_CTRL01_OPERATION_MASK    0x180
#define    RTL8370_RMA_CTRL01_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8370_RMA_CTRL01_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8370_RMA_CTRL01_TRAP_PRIORITY_OFFSET    3
#define    RTL8370_RMA_CTRL01_TRAP_PRIORITY_MASK    0x38
#define    RTL8370_RMA_CTRL01_KEEP_FORMAT_OFFSET    2
#define    RTL8370_RMA_CTRL01_KEEP_FORMAT_MASK    0x4
#define    RTL8370_RMA_CTRL01_VLAN_LEAKY_OFFSET    1
#define    RTL8370_RMA_CTRL01_VLAN_LEAKY_MASK    0x2
#define    RTL8370_RMA_CTRL01_PORTISO_LEAKY_OFFSET    0
#define    RTL8370_RMA_CTRL01_PORTISO_LEAKY_MASK    0x1

#define    RTL8370_REG_RMA_CTRL02    0x0802
#define    RTL8370_RMA_CTRL02_OPERATION_OFFSET    7
#define    RTL8370_RMA_CTRL02_OPERATION_MASK    0x180
#define    RTL8370_RMA_CTRL02_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8370_RMA_CTRL02_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8370_RMA_CTRL02_TRAP_PRIORITY_OFFSET    3
#define    RTL8370_RMA_CTRL02_TRAP_PRIORITY_MASK    0x38
#define    RTL8370_RMA_CTRL02_KEEP_FORMAT_OFFSET    2
#define    RTL8370_RMA_CTRL02_KEEP_FORMAT_MASK    0x4
#define    RTL8370_RMA_CTRL02_VLAN_LEAKY_OFFSET    1
#define    RTL8370_RMA_CTRL02_VLAN_LEAKY_MASK    0x2
#define    RTL8370_RMA_CTRL02_PORTISO_LEAKY_OFFSET    0
#define    RTL8370_RMA_CTRL02_PORTISO_LEAKY_MASK    0x1

#define    RTL8370_REG_RMA_CTRL03    0x0803
#define    RTL8370_RMA_CTRL03_OPERATION_OFFSET    7
#define    RTL8370_RMA_CTRL03_OPERATION_MASK    0x180
#define    RTL8370_RMA_CTRL03_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8370_RMA_CTRL03_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8370_RMA_CTRL03_TRAP_PRIORITY_OFFSET    3
#define    RTL8370_RMA_CTRL03_TRAP_PRIORITY_MASK    0x38
#define    RTL8370_RMA_CTRL03_KEEP_FORMAT_OFFSET    2
#define    RTL8370_RMA_CTRL03_KEEP_FORMAT_MASK    0x4
#define    RTL8370_RMA_CTRL03_VLAN_LEAKY_OFFSET    1
#define    RTL8370_RMA_CTRL03_VLAN_LEAKY_MASK    0x2
#define    RTL8370_RMA_CTRL03_PORTISO_LEAKY_OFFSET    0
#define    RTL8370_RMA_CTRL03_PORTISO_LEAKY_MASK    0x1

#define    RTL8370_REG_RMA_CTRL04    0x0804
#define    RTL8370_RMA_CTRL04_OPERATION_OFFSET    7
#define    RTL8370_RMA_CTRL04_OPERATION_MASK    0x180
#define    RTL8370_RMA_CTRL04_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8370_RMA_CTRL04_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8370_RMA_CTRL04_TRAP_PRIORITY_OFFSET    3
#define    RTL8370_RMA_CTRL04_TRAP_PRIORITY_MASK    0x38
#define    RTL8370_RMA_CTRL04_KEEP_FORMAT_OFFSET    2
#define    RTL8370_RMA_CTRL04_KEEP_FORMAT_MASK    0x4
#define    RTL8370_RMA_CTRL04_VLAN_LEAKY_OFFSET    1
#define    RTL8370_RMA_CTRL04_VLAN_LEAKY_MASK    0x2
#define    RTL8370_RMA_CTRL04_PORTISO_LEAKY_OFFSET    0
#define    RTL8370_RMA_CTRL04_PORTISO_LEAKY_MASK    0x1

#define    RTL8370_REG_RMA_CTRL05    0x0805
#define    RTL8370_RMA_CTRL05_OPERATION_OFFSET    7
#define    RTL8370_RMA_CTRL05_OPERATION_MASK    0x180
#define    RTL8370_RMA_CTRL05_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8370_RMA_CTRL05_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8370_RMA_CTRL05_TRAP_PRIORITY_OFFSET    3
#define    RTL8370_RMA_CTRL05_TRAP_PRIORITY_MASK    0x38
#define    RTL8370_RMA_CTRL05_KEEP_FORMAT_OFFSET    2
#define    RTL8370_RMA_CTRL05_KEEP_FORMAT_MASK    0x4
#define    RTL8370_RMA_CTRL05_VLAN_LEAKY_OFFSET    1
#define    RTL8370_RMA_CTRL05_VLAN_LEAKY_MASK    0x2
#define    RTL8370_RMA_CTRL05_PORTISO_LEAKY_OFFSET    0
#define    RTL8370_RMA_CTRL05_PORTISO_LEAKY_MASK    0x1

#define    RTL8370_REG_RMA_CTRL06    0x0806
#define    RTL8370_RMA_CTRL06_OPERATION_OFFSET    7
#define    RTL8370_RMA_CTRL06_OPERATION_MASK    0x180
#define    RTL8370_RMA_CTRL06_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8370_RMA_CTRL06_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8370_RMA_CTRL06_TRAP_PRIORITY_OFFSET    3
#define    RTL8370_RMA_CTRL06_TRAP_PRIORITY_MASK    0x38
#define    RTL8370_RMA_CTRL06_KEEP_FORMAT_OFFSET    2
#define    RTL8370_RMA_CTRL06_KEEP_FORMAT_MASK    0x4
#define    RTL8370_RMA_CTRL06_VLAN_LEAKY_OFFSET    1
#define    RTL8370_RMA_CTRL06_VLAN_LEAKY_MASK    0x2
#define    RTL8370_RMA_CTRL06_PORTISO_LEAKY_OFFSET    0
#define    RTL8370_RMA_CTRL06_PORTISO_LEAKY_MASK    0x1

#define    RTL8370_REG_RMA_CTRL07    0x0807
#define    RTL8370_RMA_CTRL07_OPERATION_OFFSET    7
#define    RTL8370_RMA_CTRL07_OPERATION_MASK    0x180
#define    RTL8370_RMA_CTRL07_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8370_RMA_CTRL07_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8370_RMA_CTRL07_TRAP_PRIORITY_OFFSET    3
#define    RTL8370_RMA_CTRL07_TRAP_PRIORITY_MASK    0x38
#define    RTL8370_RMA_CTRL07_KEEP_FORMAT_OFFSET    2
#define    RTL8370_RMA_CTRL07_KEEP_FORMAT_MASK    0x4
#define    RTL8370_RMA_CTRL07_VLAN_LEAKY_OFFSET    1
#define    RTL8370_RMA_CTRL07_VLAN_LEAKY_MASK    0x2
#define    RTL8370_RMA_CTRL07_PORTISO_LEAKY_OFFSET    0
#define    RTL8370_RMA_CTRL07_PORTISO_LEAKY_MASK    0x1

#define    RTL8370_REG_RMA_CTRL08    0x0808
#define    RTL8370_RMA_CTRL08_OPERATION_OFFSET    7
#define    RTL8370_RMA_CTRL08_OPERATION_MASK    0x180
#define    RTL8370_RMA_CTRL08_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8370_RMA_CTRL08_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8370_RMA_CTRL08_TRAP_PRIORITY_OFFSET    3
#define    RTL8370_RMA_CTRL08_TRAP_PRIORITY_MASK    0x38
#define    RTL8370_RMA_CTRL08_KEEP_FORMAT_OFFSET    2
#define    RTL8370_RMA_CTRL08_KEEP_FORMAT_MASK    0x4
#define    RTL8370_RMA_CTRL08_VLAN_LEAKY_OFFSET    1
#define    RTL8370_RMA_CTRL08_VLAN_LEAKY_MASK    0x2
#define    RTL8370_RMA_CTRL08_PORTISO_LEAKY_OFFSET    0
#define    RTL8370_RMA_CTRL08_PORTISO_LEAKY_MASK    0x1

#define    RTL8370_REG_RMA_CTRL09    0x0809
#define    RTL8370_RMA_CTRL09_OPERATION_OFFSET    7
#define    RTL8370_RMA_CTRL09_OPERATION_MASK    0x180
#define    RTL8370_RMA_CTRL09_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8370_RMA_CTRL09_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8370_RMA_CTRL09_TRAP_PRIORITY_OFFSET    3
#define    RTL8370_RMA_CTRL09_TRAP_PRIORITY_MASK    0x38
#define    RTL8370_RMA_CTRL09_KEEP_FORMAT_OFFSET    2
#define    RTL8370_RMA_CTRL09_KEEP_FORMAT_MASK    0x4
#define    RTL8370_RMA_CTRL09_VLAN_LEAKY_OFFSET    1
#define    RTL8370_RMA_CTRL09_VLAN_LEAKY_MASK    0x2
#define    RTL8370_RMA_CTRL09_PORTISO_LEAKY_OFFSET    0
#define    RTL8370_RMA_CTRL09_PORTISO_LEAKY_MASK    0x1

#define    RTL8370_REG_RMA_CTRL0A    0x080a
#define    RTL8370_RMA_CTRL0A_OPERATION_OFFSET    7
#define    RTL8370_RMA_CTRL0A_OPERATION_MASK    0x180
#define    RTL8370_RMA_CTRL0A_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8370_RMA_CTRL0A_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8370_RMA_CTRL0A_TRAP_PRIORITY_OFFSET    3
#define    RTL8370_RMA_CTRL0A_TRAP_PRIORITY_MASK    0x38
#define    RTL8370_RMA_CTRL0A_KEEP_FORMAT_OFFSET    2
#define    RTL8370_RMA_CTRL0A_KEEP_FORMAT_MASK    0x4
#define    RTL8370_RMA_CTRL0A_VLAN_LEAKY_OFFSET    1
#define    RTL8370_RMA_CTRL0A_VLAN_LEAKY_MASK    0x2
#define    RTL8370_RMA_CTRL0A_PORTISO_LEAKY_OFFSET    0
#define    RTL8370_RMA_CTRL0A_PORTISO_LEAKY_MASK    0x1

#define    RTL8370_REG_RMA_CTRL0B    0x080b
#define    RTL8370_RMA_CTRL0B_OPERATION_OFFSET    7
#define    RTL8370_RMA_CTRL0B_OPERATION_MASK    0x180
#define    RTL8370_RMA_CTRL0B_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8370_RMA_CTRL0B_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8370_RMA_CTRL0B_TRAP_PRIORITY_OFFSET    3
#define    RTL8370_RMA_CTRL0B_TRAP_PRIORITY_MASK    0x38
#define    RTL8370_RMA_CTRL0B_KEEP_FORMAT_OFFSET    2
#define    RTL8370_RMA_CTRL0B_KEEP_FORMAT_MASK    0x4
#define    RTL8370_RMA_CTRL0B_VLAN_LEAKY_OFFSET    1
#define    RTL8370_RMA_CTRL0B_VLAN_LEAKY_MASK    0x2
#define    RTL8370_RMA_CTRL0B_PORTISO_LEAKY_OFFSET    0
#define    RTL8370_RMA_CTRL0B_PORTISO_LEAKY_MASK    0x1

#define    RTL8370_REG_RMA_CTRL0C    0x080c
#define    RTL8370_RMA_CTRL0C_OPERATION_OFFSET    7
#define    RTL8370_RMA_CTRL0C_OPERATION_MASK    0x180
#define    RTL8370_RMA_CTRL0C_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8370_RMA_CTRL0C_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8370_RMA_CTRL0C_TRAP_PRIORITY_OFFSET    3
#define    RTL8370_RMA_CTRL0C_TRAP_PRIORITY_MASK    0x38
#define    RTL8370_RMA_CTRL0C_KEEP_FORMAT_OFFSET    2
#define    RTL8370_RMA_CTRL0C_KEEP_FORMAT_MASK    0x4
#define    RTL8370_RMA_CTRL0C_VLAN_LEAKY_OFFSET    1
#define    RTL8370_RMA_CTRL0C_VLAN_LEAKY_MASK    0x2
#define    RTL8370_RMA_CTRL0C_PORTISO_LEAKY_OFFSET    0
#define    RTL8370_RMA_CTRL0C_PORTISO_LEAKY_MASK    0x1

#define    RTL8370_REG_RMA_CTRL0D    0x080d
#define    RTL8370_RMA_CTRL0D_OPERATION_OFFSET    7
#define    RTL8370_RMA_CTRL0D_OPERATION_MASK    0x180
#define    RTL8370_RMA_CTRL0D_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8370_RMA_CTRL0D_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8370_RMA_CTRL0D_TRAP_PRIORITY_OFFSET    3
#define    RTL8370_RMA_CTRL0D_TRAP_PRIORITY_MASK    0x38
#define    RTL8370_RMA_CTRL0D_KEEP_FORMAT_OFFSET    2
#define    RTL8370_RMA_CTRL0D_KEEP_FORMAT_MASK    0x4
#define    RTL8370_RMA_CTRL0D_VLAN_LEAKY_OFFSET    1
#define    RTL8370_RMA_CTRL0D_VLAN_LEAKY_MASK    0x2
#define    RTL8370_RMA_CTRL0D_PORTISO_LEAKY_OFFSET    0
#define    RTL8370_RMA_CTRL0D_PORTISO_LEAKY_MASK    0x1

#define    RTL8370_REG_RMA_CTRL0E    0x080e
#define    RTL8370_RMA_CTRL0E_OPERATION_OFFSET    7
#define    RTL8370_RMA_CTRL0E_OPERATION_MASK    0x180
#define    RTL8370_RMA_CTRL0E_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8370_RMA_CTRL0E_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8370_RMA_CTRL0E_TRAP_PRIORITY_OFFSET    3
#define    RTL8370_RMA_CTRL0E_TRAP_PRIORITY_MASK    0x38
#define    RTL8370_RMA_CTRL0E_KEEP_FORMAT_OFFSET    2
#define    RTL8370_RMA_CTRL0E_KEEP_FORMAT_MASK    0x4
#define    RTL8370_RMA_CTRL0E_VLAN_LEAKY_OFFSET    1
#define    RTL8370_RMA_CTRL0E_VLAN_LEAKY_MASK    0x2
#define    RTL8370_RMA_CTRL0E_PORTISO_LEAKY_OFFSET    0
#define    RTL8370_RMA_CTRL0E_PORTISO_LEAKY_MASK    0x1

#define    RTL8370_REG_RMA_CTRL0F    0x080f
#define    RTL8370_RMA_CTRL0F_OPERATION_OFFSET    7
#define    RTL8370_RMA_CTRL0F_OPERATION_MASK    0x180
#define    RTL8370_RMA_CTRL0F_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8370_RMA_CTRL0F_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8370_RMA_CTRL0F_TRAP_PRIORITY_OFFSET    3
#define    RTL8370_RMA_CTRL0F_TRAP_PRIORITY_MASK    0x38
#define    RTL8370_RMA_CTRL0F_KEEP_FORMAT_OFFSET    2
#define    RTL8370_RMA_CTRL0F_KEEP_FORMAT_MASK    0x4
#define    RTL8370_RMA_CTRL0F_VLAN_LEAKY_OFFSET    1
#define    RTL8370_RMA_CTRL0F_VLAN_LEAKY_MASK    0x2
#define    RTL8370_RMA_CTRL0F_PORTISO_LEAKY_OFFSET    0
#define    RTL8370_RMA_CTRL0F_PORTISO_LEAKY_MASK    0x1

#define    RTL8370_REG_RMA_CTRL10    0x0810
#define    RTL8370_RMA_CTRL10_OPERATION_OFFSET    7
#define    RTL8370_RMA_CTRL10_OPERATION_MASK    0x180
#define    RTL8370_RMA_CTRL10_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8370_RMA_CTRL10_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8370_RMA_CTRL10_TRAP_PRIORITY_OFFSET    3
#define    RTL8370_RMA_CTRL10_TRAP_PRIORITY_MASK    0x38
#define    RTL8370_RMA_CTRL10_KEEP_FORMAT_OFFSET    2
#define    RTL8370_RMA_CTRL10_KEEP_FORMAT_MASK    0x4
#define    RTL8370_RMA_CTRL10_VLAN_LEAKY_OFFSET    1
#define    RTL8370_RMA_CTRL10_VLAN_LEAKY_MASK    0x2
#define    RTL8370_RMA_CTRL10_PORTISO_LEAKY_OFFSET    0
#define    RTL8370_RMA_CTRL10_PORTISO_LEAKY_MASK    0x1

#define    RTL8370_REG_RMA_CTRL11    0x0811
#define    RTL8370_RMA_CTRL11_OPERATION_OFFSET    7
#define    RTL8370_RMA_CTRL11_OPERATION_MASK    0x180
#define    RTL8370_RMA_CTRL11_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8370_RMA_CTRL11_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8370_RMA_CTRL11_TRAP_PRIORITY_OFFSET    3
#define    RTL8370_RMA_CTRL11_TRAP_PRIORITY_MASK    0x38
#define    RTL8370_RMA_CTRL11_KEEP_FORMAT_OFFSET    2
#define    RTL8370_RMA_CTRL11_KEEP_FORMAT_MASK    0x4
#define    RTL8370_RMA_CTRL11_VLAN_LEAKY_OFFSET    1
#define    RTL8370_RMA_CTRL11_VLAN_LEAKY_MASK    0x2
#define    RTL8370_RMA_CTRL11_PORTISO_LEAKY_OFFSET    0
#define    RTL8370_RMA_CTRL11_PORTISO_LEAKY_MASK    0x1

#define    RTL8370_REG_RMA_CTRL12    0x0812
#define    RTL8370_RMA_CTRL12_OPERATION_OFFSET    7
#define    RTL8370_RMA_CTRL12_OPERATION_MASK    0x180
#define    RTL8370_RMA_CTRL12_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8370_RMA_CTRL12_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8370_RMA_CTRL12_TRAP_PRIORITY_OFFSET    3
#define    RTL8370_RMA_CTRL12_TRAP_PRIORITY_MASK    0x38
#define    RTL8370_RMA_CTRL12_KEEP_FORMAT_OFFSET    2
#define    RTL8370_RMA_CTRL12_KEEP_FORMAT_MASK    0x4
#define    RTL8370_RMA_CTRL12_VLAN_LEAKY_OFFSET    1
#define    RTL8370_RMA_CTRL12_VLAN_LEAKY_MASK    0x2
#define    RTL8370_RMA_CTRL12_PORTISO_LEAKY_OFFSET    0
#define    RTL8370_RMA_CTRL12_PORTISO_LEAKY_MASK    0x1

#define    RTL8370_REG_RMA_CTRL13    0x0813
#define    RTL8370_RMA_CTRL13_OPERATION_OFFSET    7
#define    RTL8370_RMA_CTRL13_OPERATION_MASK    0x180
#define    RTL8370_RMA_CTRL13_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8370_RMA_CTRL13_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8370_RMA_CTRL13_TRAP_PRIORITY_OFFSET    3
#define    RTL8370_RMA_CTRL13_TRAP_PRIORITY_MASK    0x38
#define    RTL8370_RMA_CTRL13_KEEP_FORMAT_OFFSET    2
#define    RTL8370_RMA_CTRL13_KEEP_FORMAT_MASK    0x4
#define    RTL8370_RMA_CTRL13_VLAN_LEAKY_OFFSET    1
#define    RTL8370_RMA_CTRL13_VLAN_LEAKY_MASK    0x2
#define    RTL8370_RMA_CTRL13_PORTISO_LEAKY_OFFSET    0
#define    RTL8370_RMA_CTRL13_PORTISO_LEAKY_MASK    0x1

#define    RTL8370_REG_RMA_CTRL14    0x0814
#define    RTL8370_RMA_CTRL14_OPERATION_OFFSET    7
#define    RTL8370_RMA_CTRL14_OPERATION_MASK    0x180
#define    RTL8370_RMA_CTRL14_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8370_RMA_CTRL14_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8370_RMA_CTRL14_TRAP_PRIORITY_OFFSET    3
#define    RTL8370_RMA_CTRL14_TRAP_PRIORITY_MASK    0x38
#define    RTL8370_RMA_CTRL14_KEEP_FORMAT_OFFSET    2
#define    RTL8370_RMA_CTRL14_KEEP_FORMAT_MASK    0x4
#define    RTL8370_RMA_CTRL14_VLAN_LEAKY_OFFSET    1
#define    RTL8370_RMA_CTRL14_VLAN_LEAKY_MASK    0x2
#define    RTL8370_RMA_CTRL14_PORTISO_LEAKY_OFFSET    0
#define    RTL8370_RMA_CTRL14_PORTISO_LEAKY_MASK    0x1

#define    RTL8370_REG_RMA_CTRL15    0x0815
#define    RTL8370_RMA_CTRL15_OPERATION_OFFSET    7
#define    RTL8370_RMA_CTRL15_OPERATION_MASK    0x180
#define    RTL8370_RMA_CTRL15_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8370_RMA_CTRL15_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8370_RMA_CTRL15_TRAP_PRIORITY_OFFSET    3
#define    RTL8370_RMA_CTRL15_TRAP_PRIORITY_MASK    0x38
#define    RTL8370_RMA_CTRL15_KEEP_FORMAT_OFFSET    2
#define    RTL8370_RMA_CTRL15_KEEP_FORMAT_MASK    0x4
#define    RTL8370_RMA_CTRL15_VLAN_LEAKY_OFFSET    1
#define    RTL8370_RMA_CTRL15_VLAN_LEAKY_MASK    0x2
#define    RTL8370_RMA_CTRL15_PORTISO_LEAKY_OFFSET    0
#define    RTL8370_RMA_CTRL15_PORTISO_LEAKY_MASK    0x1

#define    RTL8370_REG_RMA_CTRL16    0x0816
#define    RTL8370_RMA_CTRL16_OPERATION_OFFSET    7
#define    RTL8370_RMA_CTRL16_OPERATION_MASK    0x180
#define    RTL8370_RMA_CTRL16_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8370_RMA_CTRL16_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8370_RMA_CTRL16_TRAP_PRIORITY_OFFSET    3
#define    RTL8370_RMA_CTRL16_TRAP_PRIORITY_MASK    0x38
#define    RTL8370_RMA_CTRL16_KEEP_FORMAT_OFFSET    2
#define    RTL8370_RMA_CTRL16_KEEP_FORMAT_MASK    0x4
#define    RTL8370_RMA_CTRL16_VLAN_LEAKY_OFFSET    1
#define    RTL8370_RMA_CTRL16_VLAN_LEAKY_MASK    0x2
#define    RTL8370_RMA_CTRL16_PORTISO_LEAKY_OFFSET    0
#define    RTL8370_RMA_CTRL16_PORTISO_LEAKY_MASK    0x1

#define    RTL8370_REG_RMA_CTRL17    0x0817
#define    RTL8370_RMA_CTRL17_OPERATION_OFFSET    7
#define    RTL8370_RMA_CTRL17_OPERATION_MASK    0x180
#define    RTL8370_RMA_CTRL17_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8370_RMA_CTRL17_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8370_RMA_CTRL17_TRAP_PRIORITY_OFFSET    3
#define    RTL8370_RMA_CTRL17_TRAP_PRIORITY_MASK    0x38
#define    RTL8370_RMA_CTRL17_KEEP_FORMAT_OFFSET    2
#define    RTL8370_RMA_CTRL17_KEEP_FORMAT_MASK    0x4
#define    RTL8370_RMA_CTRL17_VLAN_LEAKY_OFFSET    1
#define    RTL8370_RMA_CTRL17_VLAN_LEAKY_MASK    0x2
#define    RTL8370_RMA_CTRL17_PORTISO_LEAKY_OFFSET    0
#define    RTL8370_RMA_CTRL17_PORTISO_LEAKY_MASK    0x1

#define    RTL8370_REG_RMA_CTRL18    0x0818
#define    RTL8370_RMA_CTRL18_OPERATION_OFFSET    7
#define    RTL8370_RMA_CTRL18_OPERATION_MASK    0x180
#define    RTL8370_RMA_CTRL18_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8370_RMA_CTRL18_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8370_RMA_CTRL18_TRAP_PRIORITY_OFFSET    3
#define    RTL8370_RMA_CTRL18_TRAP_PRIORITY_MASK    0x38
#define    RTL8370_RMA_CTRL18_KEEP_FORMAT_OFFSET    2
#define    RTL8370_RMA_CTRL18_KEEP_FORMAT_MASK    0x4
#define    RTL8370_RMA_CTRL18_VLAN_LEAKY_OFFSET    1
#define    RTL8370_RMA_CTRL18_VLAN_LEAKY_MASK    0x2
#define    RTL8370_RMA_CTRL18_PORTISO_LEAKY_OFFSET    0
#define    RTL8370_RMA_CTRL18_PORTISO_LEAKY_MASK    0x1

#define    RTL8370_REG_RMA_CTRL19    0x0819
#define    RTL8370_RMA_CTRL19_OPERATION_OFFSET    7
#define    RTL8370_RMA_CTRL19_OPERATION_MASK    0x180
#define    RTL8370_RMA_CTRL19_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8370_RMA_CTRL19_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8370_RMA_CTRL19_TRAP_PRIORITY_OFFSET    3
#define    RTL8370_RMA_CTRL19_TRAP_PRIORITY_MASK    0x38
#define    RTL8370_RMA_CTRL19_KEEP_FORMAT_OFFSET    2
#define    RTL8370_RMA_CTRL19_KEEP_FORMAT_MASK    0x4
#define    RTL8370_RMA_CTRL19_VLAN_LEAKY_OFFSET    1
#define    RTL8370_RMA_CTRL19_VLAN_LEAKY_MASK    0x2
#define    RTL8370_RMA_CTRL19_PORTISO_LEAKY_OFFSET    0
#define    RTL8370_RMA_CTRL19_PORTISO_LEAKY_MASK    0x1

#define    RTL8370_REG_RMA_CTRL1A    0x081a
#define    RTL8370_RMA_CTRL1A_OPERATION_OFFSET    7
#define    RTL8370_RMA_CTRL1A_OPERATION_MASK    0x180
#define    RTL8370_RMA_CTRL1A_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8370_RMA_CTRL1A_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8370_RMA_CTRL1A_TRAP_PRIORITY_OFFSET    3
#define    RTL8370_RMA_CTRL1A_TRAP_PRIORITY_MASK    0x38
#define    RTL8370_RMA_CTRL1A_KEEP_FORMAT_OFFSET    2
#define    RTL8370_RMA_CTRL1A_KEEP_FORMAT_MASK    0x4
#define    RTL8370_RMA_CTRL1A_VLAN_LEAKY_OFFSET    1
#define    RTL8370_RMA_CTRL1A_VLAN_LEAKY_MASK    0x2
#define    RTL8370_RMA_CTRL1A_PORTISO_LEAKY_OFFSET    0
#define    RTL8370_RMA_CTRL1A_PORTISO_LEAKY_MASK    0x1

#define    RTL8370_REG_RMA_CTRL1B    0x081b
#define    RTL8370_RMA_CTRL1B_OPERATION_OFFSET    7
#define    RTL8370_RMA_CTRL1B_OPERATION_MASK    0x180
#define    RTL8370_RMA_CTRL1B_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8370_RMA_CTRL1B_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8370_RMA_CTRL1B_TRAP_PRIORITY_OFFSET    3
#define    RTL8370_RMA_CTRL1B_TRAP_PRIORITY_MASK    0x38
#define    RTL8370_RMA_CTRL1B_KEEP_FORMAT_OFFSET    2
#define    RTL8370_RMA_CTRL1B_KEEP_FORMAT_MASK    0x4
#define    RTL8370_RMA_CTRL1B_VLAN_LEAKY_OFFSET    1
#define    RTL8370_RMA_CTRL1B_VLAN_LEAKY_MASK    0x2
#define    RTL8370_RMA_CTRL1B_PORTISO_LEAKY_OFFSET    0
#define    RTL8370_RMA_CTRL1B_PORTISO_LEAKY_MASK    0x1

#define    RTL8370_REG_RMA_CTRL1C    0x081c
#define    RTL8370_RMA_CTRL1C_OPERATION_OFFSET    7
#define    RTL8370_RMA_CTRL1C_OPERATION_MASK    0x180
#define    RTL8370_RMA_CTRL1C_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8370_RMA_CTRL1C_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8370_RMA_CTRL1C_TRAP_PRIORITY_OFFSET    3
#define    RTL8370_RMA_CTRL1C_TRAP_PRIORITY_MASK    0x38
#define    RTL8370_RMA_CTRL1C_KEEP_FORMAT_OFFSET    2
#define    RTL8370_RMA_CTRL1C_KEEP_FORMAT_MASK    0x4
#define    RTL8370_RMA_CTRL1C_VLAN_LEAKY_OFFSET    1
#define    RTL8370_RMA_CTRL1C_VLAN_LEAKY_MASK    0x2
#define    RTL8370_RMA_CTRL1C_PORTISO_LEAKY_OFFSET    0
#define    RTL8370_RMA_CTRL1C_PORTISO_LEAKY_MASK    0x1

#define    RTL8370_REG_RMA_CTRL1D    0x081d
#define    RTL8370_RMA_CTRL1D_OPERATION_OFFSET    7
#define    RTL8370_RMA_CTRL1D_OPERATION_MASK    0x180
#define    RTL8370_RMA_CTRL1D_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8370_RMA_CTRL1D_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8370_RMA_CTRL1D_TRAP_PRIORITY_OFFSET    3
#define    RTL8370_RMA_CTRL1D_TRAP_PRIORITY_MASK    0x38
#define    RTL8370_RMA_CTRL1D_KEEP_FORMAT_OFFSET    2
#define    RTL8370_RMA_CTRL1D_KEEP_FORMAT_MASK    0x4
#define    RTL8370_RMA_CTRL1D_VLAN_LEAKY_OFFSET    1
#define    RTL8370_RMA_CTRL1D_VLAN_LEAKY_MASK    0x2
#define    RTL8370_RMA_CTRL1D_PORTISO_LEAKY_OFFSET    0
#define    RTL8370_RMA_CTRL1D_PORTISO_LEAKY_MASK    0x1

#define    RTL8370_REG_RMA_CTRL1E    0x081e
#define    RTL8370_RMA_CTRL1E_OPERATION_OFFSET    7
#define    RTL8370_RMA_CTRL1E_OPERATION_MASK    0x180
#define    RTL8370_RMA_CTRL1E_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8370_RMA_CTRL1E_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8370_RMA_CTRL1E_TRAP_PRIORITY_OFFSET    3
#define    RTL8370_RMA_CTRL1E_TRAP_PRIORITY_MASK    0x38
#define    RTL8370_RMA_CTRL1E_KEEP_FORMAT_OFFSET    2
#define    RTL8370_RMA_CTRL1E_KEEP_FORMAT_MASK    0x4
#define    RTL8370_RMA_CTRL1E_VLAN_LEAKY_OFFSET    1
#define    RTL8370_RMA_CTRL1E_VLAN_LEAKY_MASK    0x2
#define    RTL8370_RMA_CTRL1E_PORTISO_LEAKY_OFFSET    0
#define    RTL8370_RMA_CTRL1E_PORTISO_LEAKY_MASK    0x1

#define    RTL8370_REG_RMA_CTRL1F    0x081f
#define    RTL8370_RMA_CTRL1F_OPERATION_OFFSET    7
#define    RTL8370_RMA_CTRL1F_OPERATION_MASK    0x180
#define    RTL8370_RMA_CTRL1F_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8370_RMA_CTRL1F_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8370_RMA_CTRL1F_TRAP_PRIORITY_OFFSET    3
#define    RTL8370_RMA_CTRL1F_TRAP_PRIORITY_MASK    0x38
#define    RTL8370_RMA_CTRL1F_KEEP_FORMAT_OFFSET    2
#define    RTL8370_RMA_CTRL1F_KEEP_FORMAT_MASK    0x4
#define    RTL8370_RMA_CTRL1F_VLAN_LEAKY_OFFSET    1
#define    RTL8370_RMA_CTRL1F_VLAN_LEAKY_MASK    0x2
#define    RTL8370_RMA_CTRL1F_PORTISO_LEAKY_OFFSET    0
#define    RTL8370_RMA_CTRL1F_PORTISO_LEAKY_MASK    0x1

#define    RTL8370_REG_RMA_CTRL20    0x0820
#define    RTL8370_RMA_CTRL20_OPERATION_OFFSET    7
#define    RTL8370_RMA_CTRL20_OPERATION_MASK    0x180
#define    RTL8370_RMA_CTRL20_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8370_RMA_CTRL20_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8370_RMA_CTRL20_TRAP_PRIORITY_OFFSET    3
#define    RTL8370_RMA_CTRL20_TRAP_PRIORITY_MASK    0x38
#define    RTL8370_RMA_CTRL20_KEEP_FORMAT_OFFSET    2
#define    RTL8370_RMA_CTRL20_KEEP_FORMAT_MASK    0x4
#define    RTL8370_RMA_CTRL20_VLAN_LEAKY_OFFSET    1
#define    RTL8370_RMA_CTRL20_VLAN_LEAKY_MASK    0x2
#define    RTL8370_RMA_CTRL20_PORTISO_LEAKY_OFFSET    0
#define    RTL8370_RMA_CTRL20_PORTISO_LEAKY_MASK    0x1

#define    RTL8370_REG_RMA_CTRL21    0x0821
#define    RTL8370_RMA_CTRL21_OPERATION_OFFSET    7
#define    RTL8370_RMA_CTRL21_OPERATION_MASK    0x180
#define    RTL8370_RMA_CTRL21_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8370_RMA_CTRL21_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8370_RMA_CTRL21_TRAP_PRIORITY_OFFSET    3
#define    RTL8370_RMA_CTRL21_TRAP_PRIORITY_MASK    0x38
#define    RTL8370_RMA_CTRL21_KEEP_FORMAT_OFFSET    2
#define    RTL8370_RMA_CTRL21_KEEP_FORMAT_MASK    0x4
#define    RTL8370_RMA_CTRL21_VLAN_LEAKY_OFFSET    1
#define    RTL8370_RMA_CTRL21_VLAN_LEAKY_MASK    0x2
#define    RTL8370_RMA_CTRL21_PORTISO_LEAKY_OFFSET    0
#define    RTL8370_RMA_CTRL21_PORTISO_LEAKY_MASK    0x1

#define    RTL8370_REG_RMA_CTRL22    0x0822
#define    RTL8370_RMA_CTRL22_OPERATION_OFFSET    7
#define    RTL8370_RMA_CTRL22_OPERATION_MASK    0x180
#define    RTL8370_RMA_CTRL22_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8370_RMA_CTRL22_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8370_RMA_CTRL22_TRAP_PRIORITY_OFFSET    3
#define    RTL8370_RMA_CTRL22_TRAP_PRIORITY_MASK    0x38
#define    RTL8370_RMA_CTRL22_KEEP_FORMAT_OFFSET    2
#define    RTL8370_RMA_CTRL22_KEEP_FORMAT_MASK    0x4
#define    RTL8370_RMA_CTRL22_VLAN_LEAKY_OFFSET    1
#define    RTL8370_RMA_CTRL22_VLAN_LEAKY_MASK    0x2
#define    RTL8370_RMA_CTRL22_PORTISO_LEAKY_OFFSET    0
#define    RTL8370_RMA_CTRL22_PORTISO_LEAKY_MASK    0x1

#define    RTL8370_REG_RMA_CTRL23    0x0823
#define    RTL8370_RMA_CTRL23_OPERATION_OFFSET    7
#define    RTL8370_RMA_CTRL23_OPERATION_MASK    0x180
#define    RTL8370_RMA_CTRL23_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8370_RMA_CTRL23_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8370_RMA_CTRL23_TRAP_PRIORITY_OFFSET    3
#define    RTL8370_RMA_CTRL23_TRAP_PRIORITY_MASK    0x38
#define    RTL8370_RMA_CTRL23_KEEP_FORMAT_OFFSET    2
#define    RTL8370_RMA_CTRL23_KEEP_FORMAT_MASK    0x4
#define    RTL8370_RMA_CTRL23_VLAN_LEAKY_OFFSET    1
#define    RTL8370_RMA_CTRL23_VLAN_LEAKY_MASK    0x2
#define    RTL8370_RMA_CTRL23_PORTISO_LEAKY_OFFSET    0
#define    RTL8370_RMA_CTRL23_PORTISO_LEAKY_MASK    0x1

#define    RTL8370_REG_RMA_CTRL24    0x0824
#define    RTL8370_RMA_CTRL24_OPERATION_OFFSET    7
#define    RTL8370_RMA_CTRL24_OPERATION_MASK    0x180
#define    RTL8370_RMA_CTRL24_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8370_RMA_CTRL24_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8370_RMA_CTRL24_TRAP_PRIORITY_OFFSET    3
#define    RTL8370_RMA_CTRL24_TRAP_PRIORITY_MASK    0x38
#define    RTL8370_RMA_CTRL24_KEEP_FORMAT_OFFSET    2
#define    RTL8370_RMA_CTRL24_KEEP_FORMAT_MASK    0x4
#define    RTL8370_RMA_CTRL24_VLAN_LEAKY_OFFSET    1
#define    RTL8370_RMA_CTRL24_VLAN_LEAKY_MASK    0x2
#define    RTL8370_RMA_CTRL24_PORTISO_LEAKY_OFFSET    0
#define    RTL8370_RMA_CTRL24_PORTISO_LEAKY_MASK    0x1

#define    RTL8370_REG_RMA_CTRL25    0x0825
#define    RTL8370_RMA_CTRL25_OPERATION_OFFSET    7
#define    RTL8370_RMA_CTRL25_OPERATION_MASK    0x180
#define    RTL8370_RMA_CTRL25_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8370_RMA_CTRL25_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8370_RMA_CTRL25_TRAP_PRIORITY_OFFSET    3
#define    RTL8370_RMA_CTRL25_TRAP_PRIORITY_MASK    0x38
#define    RTL8370_RMA_CTRL25_KEEP_FORMAT_OFFSET    2
#define    RTL8370_RMA_CTRL25_KEEP_FORMAT_MASK    0x4
#define    RTL8370_RMA_CTRL25_VLAN_LEAKY_OFFSET    1
#define    RTL8370_RMA_CTRL25_VLAN_LEAKY_MASK    0x2
#define    RTL8370_RMA_CTRL25_PORTISO_LEAKY_OFFSET    0
#define    RTL8370_RMA_CTRL25_PORTISO_LEAKY_MASK    0x1

#define    RTL8370_REG_RMA_CTRL26    0x0826
#define    RTL8370_RMA_CTRL26_OPERATION_OFFSET    7
#define    RTL8370_RMA_CTRL26_OPERATION_MASK    0x180
#define    RTL8370_RMA_CTRL26_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8370_RMA_CTRL26_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8370_RMA_CTRL26_TRAP_PRIORITY_OFFSET    3
#define    RTL8370_RMA_CTRL26_TRAP_PRIORITY_MASK    0x38
#define    RTL8370_RMA_CTRL26_KEEP_FORMAT_OFFSET    2
#define    RTL8370_RMA_CTRL26_KEEP_FORMAT_MASK    0x4
#define    RTL8370_RMA_CTRL26_VLAN_LEAKY_OFFSET    1
#define    RTL8370_RMA_CTRL26_VLAN_LEAKY_MASK    0x2
#define    RTL8370_RMA_CTRL26_PORTISO_LEAKY_OFFSET    0
#define    RTL8370_RMA_CTRL26_PORTISO_LEAKY_MASK    0x1

#define    RTL8370_REG_RMA_CTRL27    0x0827
#define    RTL8370_RMA_CTRL27_OPERATION_OFFSET    7
#define    RTL8370_RMA_CTRL27_OPERATION_MASK    0x180
#define    RTL8370_RMA_CTRL27_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8370_RMA_CTRL27_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8370_RMA_CTRL27_TRAP_PRIORITY_OFFSET    3
#define    RTL8370_RMA_CTRL27_TRAP_PRIORITY_MASK    0x38
#define    RTL8370_RMA_CTRL27_KEEP_FORMAT_OFFSET    2
#define    RTL8370_RMA_CTRL27_KEEP_FORMAT_MASK    0x4
#define    RTL8370_RMA_CTRL27_VLAN_LEAKY_OFFSET    1
#define    RTL8370_RMA_CTRL27_VLAN_LEAKY_MASK    0x2
#define    RTL8370_RMA_CTRL27_PORTISO_LEAKY_OFFSET    0
#define    RTL8370_RMA_CTRL27_PORTISO_LEAKY_MASK    0x1

#define    RTL8370_REG_RMA_CTRL28    0x0828
#define    RTL8370_RMA_CTRL28_OPERATION_OFFSET    7
#define    RTL8370_RMA_CTRL28_OPERATION_MASK    0x180
#define    RTL8370_RMA_CTRL28_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8370_RMA_CTRL28_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8370_RMA_CTRL28_TRAP_PRIORITY_OFFSET    3
#define    RTL8370_RMA_CTRL28_TRAP_PRIORITY_MASK    0x38
#define    RTL8370_RMA_CTRL28_KEEP_FORMAT_OFFSET    2
#define    RTL8370_RMA_CTRL28_KEEP_FORMAT_MASK    0x4
#define    RTL8370_RMA_CTRL28_VLAN_LEAKY_OFFSET    1
#define    RTL8370_RMA_CTRL28_VLAN_LEAKY_MASK    0x2
#define    RTL8370_RMA_CTRL28_PORTISO_LEAKY_OFFSET    0
#define    RTL8370_RMA_CTRL28_PORTISO_LEAKY_MASK    0x1

#define    RTL8370_REG_RMA_CTRL29    0x0829
#define    RTL8370_RMA_CTRL29_OPERATION_OFFSET    7
#define    RTL8370_RMA_CTRL29_OPERATION_MASK    0x180
#define    RTL8370_RMA_CTRL29_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8370_RMA_CTRL29_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8370_RMA_CTRL29_TRAP_PRIORITY_OFFSET    3
#define    RTL8370_RMA_CTRL29_TRAP_PRIORITY_MASK    0x38
#define    RTL8370_RMA_CTRL29_KEEP_FORMAT_OFFSET    2
#define    RTL8370_RMA_CTRL29_KEEP_FORMAT_MASK    0x4
#define    RTL8370_RMA_CTRL29_VLAN_LEAKY_OFFSET    1
#define    RTL8370_RMA_CTRL29_VLAN_LEAKY_MASK    0x2
#define    RTL8370_RMA_CTRL29_PORTISO_LEAKY_OFFSET    0
#define    RTL8370_RMA_CTRL29_PORTISO_LEAKY_MASK    0x1

#define    RTL8370_REG_RMA_CTRL2A    0x082a
#define    RTL8370_RMA_CTRL2A_OPERATION_OFFSET    7
#define    RTL8370_RMA_CTRL2A_OPERATION_MASK    0x180
#define    RTL8370_RMA_CTRL2A_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8370_RMA_CTRL2A_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8370_RMA_CTRL2A_TRAP_PRIORITY_OFFSET    3
#define    RTL8370_RMA_CTRL2A_TRAP_PRIORITY_MASK    0x38
#define    RTL8370_RMA_CTRL2A_KEEP_FORMAT_OFFSET    2
#define    RTL8370_RMA_CTRL2A_KEEP_FORMAT_MASK    0x4
#define    RTL8370_RMA_CTRL2A_VLAN_LEAKY_OFFSET    1
#define    RTL8370_RMA_CTRL2A_VLAN_LEAKY_MASK    0x2
#define    RTL8370_RMA_CTRL2A_PORTISO_LEAKY_OFFSET    0
#define    RTL8370_RMA_CTRL2A_PORTISO_LEAKY_MASK    0x1

#define    RTL8370_REG_RMA_CTRL2B    0x082b
#define    RTL8370_RMA_CTRL2B_OPERATION_OFFSET    7
#define    RTL8370_RMA_CTRL2B_OPERATION_MASK    0x180
#define    RTL8370_RMA_CTRL2B_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8370_RMA_CTRL2B_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8370_RMA_CTRL2B_TRAP_PRIORITY_OFFSET    3
#define    RTL8370_RMA_CTRL2B_TRAP_PRIORITY_MASK    0x38
#define    RTL8370_RMA_CTRL2B_KEEP_FORMAT_OFFSET    2
#define    RTL8370_RMA_CTRL2B_KEEP_FORMAT_MASK    0x4
#define    RTL8370_RMA_CTRL2B_VLAN_LEAKY_OFFSET    1
#define    RTL8370_RMA_CTRL2B_VLAN_LEAKY_MASK    0x2
#define    RTL8370_RMA_CTRL2B_PORTISO_LEAKY_OFFSET    0
#define    RTL8370_RMA_CTRL2B_PORTISO_LEAKY_MASK    0x1

#define    RTL8370_REG_RMA_CTRL2C    0x082c
#define    RTL8370_RMA_CTRL2C_OPERATION_OFFSET    7
#define    RTL8370_RMA_CTRL2C_OPERATION_MASK    0x180
#define    RTL8370_RMA_CTRL2C_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8370_RMA_CTRL2C_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8370_RMA_CTRL2C_TRAP_PRIORITY_OFFSET    3
#define    RTL8370_RMA_CTRL2C_TRAP_PRIORITY_MASK    0x38
#define    RTL8370_RMA_CTRL2C_KEEP_FORMAT_OFFSET    2
#define    RTL8370_RMA_CTRL2C_KEEP_FORMAT_MASK    0x4
#define    RTL8370_RMA_CTRL2C_VLAN_LEAKY_OFFSET    1
#define    RTL8370_RMA_CTRL2C_VLAN_LEAKY_MASK    0x2
#define    RTL8370_RMA_CTRL2C_PORTISO_LEAKY_OFFSET    0
#define    RTL8370_RMA_CTRL2C_PORTISO_LEAKY_MASK    0x1

#define    RTL8370_REG_RMA_CTRL2D    0x082d
#define    RTL8370_RMA_CTRL2D_OPERATION_OFFSET    7
#define    RTL8370_RMA_CTRL2D_OPERATION_MASK    0x180
#define    RTL8370_RMA_CTRL2D_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8370_RMA_CTRL2D_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8370_RMA_CTRL2D_TRAP_PRIORITY_OFFSET    3
#define    RTL8370_RMA_CTRL2D_TRAP_PRIORITY_MASK    0x38
#define    RTL8370_RMA_CTRL2D_KEEP_FORMAT_OFFSET    2
#define    RTL8370_RMA_CTRL2D_KEEP_FORMAT_MASK    0x4
#define    RTL8370_RMA_CTRL2D_VLAN_LEAKY_OFFSET    1
#define    RTL8370_RMA_CTRL2D_VLAN_LEAKY_MASK    0x2
#define    RTL8370_RMA_CTRL2D_PORTISO_LEAKY_OFFSET    0
#define    RTL8370_RMA_CTRL2D_PORTISO_LEAKY_MASK    0x1

#define    RTL8370_REG_RMA_CTRL2E    0x082e
#define    RTL8370_RMA_CTRL2E_OPERATION_OFFSET    7
#define    RTL8370_RMA_CTRL2E_OPERATION_MASK    0x180
#define    RTL8370_RMA_CTRL2E_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8370_RMA_CTRL2E_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8370_RMA_CTRL2E_TRAP_PRIORITY_OFFSET    3
#define    RTL8370_RMA_CTRL2E_TRAP_PRIORITY_MASK    0x38
#define    RTL8370_RMA_CTRL2E_KEEP_FORMAT_OFFSET    2
#define    RTL8370_RMA_CTRL2E_KEEP_FORMAT_MASK    0x4
#define    RTL8370_RMA_CTRL2E_VLAN_LEAKY_OFFSET    1
#define    RTL8370_RMA_CTRL2E_VLAN_LEAKY_MASK    0x2
#define    RTL8370_RMA_CTRL2E_PORTISO_LEAKY_OFFSET    0
#define    RTL8370_RMA_CTRL2E_PORTISO_LEAKY_MASK    0x1

#define    RTL8370_REG_RMA_CTRL2F    0x082f
#define    RTL8370_RMA_CTRL2F_OPERATION_OFFSET    7
#define    RTL8370_RMA_CTRL2F_OPERATION_MASK    0x180
#define    RTL8370_RMA_CTRL2F_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8370_RMA_CTRL2F_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8370_RMA_CTRL2F_TRAP_PRIORITY_OFFSET    3
#define    RTL8370_RMA_CTRL2F_TRAP_PRIORITY_MASK    0x38
#define    RTL8370_RMA_CTRL2F_KEEP_FORMAT_OFFSET    2
#define    RTL8370_RMA_CTRL2F_KEEP_FORMAT_MASK    0x4
#define    RTL8370_RMA_CTRL2F_VLAN_LEAKY_OFFSET    1
#define    RTL8370_RMA_CTRL2F_VLAN_LEAKY_MASK    0x2
#define    RTL8370_RMA_CTRL2F_PORTISO_LEAKY_OFFSET    0
#define    RTL8370_RMA_CTRL2F_PORTISO_LEAKY_MASK    0x1

#define    RTL8370_REG_IGMP_CTRL    0x0830
#define    RTL8370_MLD_PPPOE_TRAP_OFFSET    12
#define    RTL8370_MLD_PPPOE_TRAP_MASK    0x3000
#define    RTL8370_IGMP_PPPOE_TRAP_OFFSET    10
#define    RTL8370_IGMP_PPPOE_TRAP_MASK    0xC00
#define    RTL8370_MLD_TRAP_OFFSET    8
#define    RTL8370_MLD_TRAP_MASK    0x300
#define    RTL8370_IGMP_TRAP_OFFSET    6
#define    RTL8370_IGMP_TRAP_MASK    0xC0
#define    RTL8370_IGMP_CTRL_DISCARD_STORM_FILTER_OFFSET    5
#define    RTL8370_IGMP_CTRL_DISCARD_STORM_FILTER_MASK    0x20
#define    RTL8370_IGMP_CTRL_TRAP_PRIORITY_OFFSET    2
#define    RTL8370_IGMP_CTRL_TRAP_PRIORITY_MASK    0x1C
#define    RTL8370_IGMP_CTRL_VLAN_LEAKY_OFFSET    1
#define    RTL8370_IGMP_CTRL_VLAN_LEAKY_MASK    0x2
#define    RTL8370_IGMP_CTRL_PORTISO_LEAKY_OFFSET    0
#define    RTL8370_IGMP_CTRL_PORTISO_LEAKY_MASK    0x1

#define    RTL8370_REG_VLAN_PORTBASED_PRIORITY_CTRL0    0x0851
#define    RTL8370_VLAN_PORTBASED_PRIORITY_CTRL0_PORT3_PRIORITY_OFFSET    12
#define    RTL8370_VLAN_PORTBASED_PRIORITY_CTRL0_PORT3_PRIORITY_MASK    0x7000
#define    RTL8370_VLAN_PORTBASED_PRIORITY_CTRL0_PORT2_PRIORITY_OFFSET    8
#define    RTL8370_VLAN_PORTBASED_PRIORITY_CTRL0_PORT2_PRIORITY_MASK    0x700
#define    RTL8370_VLAN_PORTBASED_PRIORITY_CTRL0_PORT1_PRIORITY_OFFSET    4
#define    RTL8370_VLAN_PORTBASED_PRIORITY_CTRL0_PORT1_PRIORITY_MASK    0x70
#define    RTL8370_VLAN_PORTBASED_PRIORITY_CTRL0_PORT0_PRIORITY_OFFSET    0
#define    RTL8370_VLAN_PORTBASED_PRIORITY_CTRL0_PORT0_PRIORITY_MASK    0x7

#define    RTL8370_REG_VLAN_PORTBASED_PRIORITY_CTRL1    0x0852
#define    RTL8370_VLAN_PORTBASED_PRIORITY_CTRL1_PORT7_PRIORITY_OFFSET    12
#define    RTL8370_VLAN_PORTBASED_PRIORITY_CTRL1_PORT7_PRIORITY_MASK    0x7000
#define    RTL8370_VLAN_PORTBASED_PRIORITY_CTRL1_PORT6_PRIORITY_OFFSET    8
#define    RTL8370_VLAN_PORTBASED_PRIORITY_CTRL1_PORT6_PRIORITY_MASK    0x700
#define    RTL8370_VLAN_PORTBASED_PRIORITY_CTRL1_PORT5_PRIORITY_OFFSET    4
#define    RTL8370_VLAN_PORTBASED_PRIORITY_CTRL1_PORT5_PRIORITY_MASK    0x70
#define    RTL8370_VLAN_PORTBASED_PRIORITY_CTRL1_PORT4_PRIORITY_OFFSET    0
#define    RTL8370_VLAN_PORTBASED_PRIORITY_CTRL1_PORT4_PRIORITY_MASK    0x7

#define    RTL8370_REG_VLAN_PORTBASED_PRIORITY_CTRL2    0x0853
#define    RTL8370_VLAN_PORTBASED_PRIORITY_CTRL2_PORT11_PRIORITY_OFFSET    12
#define    RTL8370_VLAN_PORTBASED_PRIORITY_CTRL2_PORT11_PRIORITY_MASK    0x7000
#define    RTL8370_VLAN_PORTBASED_PRIORITY_CTRL2_PORT10_PRIORITY_OFFSET    8
#define    RTL8370_VLAN_PORTBASED_PRIORITY_CTRL2_PORT10_PRIORITY_MASK    0x700
#define    RTL8370_VLAN_PORTBASED_PRIORITY_CTRL2_PORT9_PRIORITY_OFFSET    4
#define    RTL8370_VLAN_PORTBASED_PRIORITY_CTRL2_PORT9_PRIORITY_MASK    0x70
#define    RTL8370_VLAN_PORTBASED_PRIORITY_CTRL2_PORT8_PRIORITY_OFFSET    0
#define    RTL8370_VLAN_PORTBASED_PRIORITY_CTRL2_PORT8_PRIORITY_MASK    0x7

#define    RTL8370_REG_VLAN_PORTBASED_PRIORITY_CTRL3    0x0854
#define    RTL8370_VLAN_PORTBASED_PRIORITY_CTRL3_PORT15_PRIORITY_OFFSET    12
#define    RTL8370_VLAN_PORTBASED_PRIORITY_CTRL3_PORT15_PRIORITY_MASK    0x7000
#define    RTL8370_VLAN_PORTBASED_PRIORITY_CTRL3_PORT14_PRIORITY_OFFSET    8
#define    RTL8370_VLAN_PORTBASED_PRIORITY_CTRL3_PORT14_PRIORITY_MASK    0x700
#define    RTL8370_VLAN_PORTBASED_PRIORITY_CTRL3_PORT13_PRIORITY_OFFSET    4
#define    RTL8370_VLAN_PORTBASED_PRIORITY_CTRL3_PORT13_PRIORITY_MASK    0x70
#define    RTL8370_VLAN_PORTBASED_PRIORITY_CTRL3_PORT12_PRIORITY_OFFSET    0
#define    RTL8370_VLAN_PORTBASED_PRIORITY_CTRL3_PORT12_PRIORITY_MASK    0x7

#define    RTL8370_REG_VLAN_PPB_PRIORITY_ITEM0_CTRL0    0x0855
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM0_CTRL0_PORT3_PRIORITY_OFFSET    12
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM0_CTRL0_PORT3_PRIORITY_MASK    0x7000
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM0_CTRL0_PORT2_PRIORITY_OFFSET    8
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM0_CTRL0_PORT2_PRIORITY_MASK    0x700
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM0_CTRL0_PORT1_PRIORITY_OFFSET    4
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM0_CTRL0_PORT1_PRIORITY_MASK    0x70
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM0_CTRL0_PORT0_PRIORITY_OFFSET    0
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM0_CTRL0_PORT0_PRIORITY_MASK    0x7

#define    RTL8370_REG_VLAN_PPB_PRIORITY_ITEM0_CTRL1    0x0856
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM0_CTRL1_PORT7_PRIORITY_OFFSET    12
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM0_CTRL1_PORT7_PRIORITY_MASK    0x7000
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM0_CTRL1_PORT6_PRIORITY_OFFSET    8
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM0_CTRL1_PORT6_PRIORITY_MASK    0x700
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM0_CTRL1_PORT5_PRIORITY_OFFSET    4
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM0_CTRL1_PORT5_PRIORITY_MASK    0x70
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM0_CTRL1_PORT4_PRIORITY_OFFSET    0
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM0_CTRL1_PORT4_PRIORITY_MASK    0x7

#define    RTL8370_REG_VLAN_PPB_PRIORITY_ITEM0_CTRL2    0x0857
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM0_CTRL2_PORT11_PRIORITY_OFFSET    12
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM0_CTRL2_PORT11_PRIORITY_MASK    0x7000
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM0_CTRL2_PORT10_PRIORITY_OFFSET    8
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM0_CTRL2_PORT10_PRIORITY_MASK    0x700
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM0_CTRL2_PORT9_PRIORITY_OFFSET    4
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM0_CTRL2_PORT9_PRIORITY_MASK    0x70
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM0_CTRL2_PORT8_PRIORITY_OFFSET    0
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM0_CTRL2_PORT8_PRIORITY_MASK    0x7

#define    RTL8370_REG_VLAN_PPB_PRIORITY_ITEM0_CTRL3    0x0858
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM0_CTRL3_PORT15_PRIORITY_OFFSET    12
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM0_CTRL3_PORT15_PRIORITY_MASK    0x7000
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM0_CTRL3_PORT14_PRIORITY_OFFSET    8
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM0_CTRL3_PORT14_PRIORITY_MASK    0x700
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM0_CTRL3_PORT13_PRIORITY_OFFSET    4
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM0_CTRL3_PORT13_PRIORITY_MASK    0x70
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM0_CTRL3_PORT12_PRIORITY_OFFSET    0
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM0_CTRL3_PORT12_PRIORITY_MASK    0x7

#define    RTL8370_REG_VLAN_PPB_PRIORITY_ITEM1_CTRL0    0x0859
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM1_CTRL0_PORT3_PRIORITY_OFFSET    12
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM1_CTRL0_PORT3_PRIORITY_MASK    0x7000
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM1_CTRL0_PORT2_PRIORITY_OFFSET    8
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM1_CTRL0_PORT2_PRIORITY_MASK    0x700
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM1_CTRL0_PORT1_PRIORITY_OFFSET    4
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM1_CTRL0_PORT1_PRIORITY_MASK    0x70
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM1_CTRL0_PORT0_PRIORITY_OFFSET    0
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM1_CTRL0_PORT0_PRIORITY_MASK    0x7

#define    RTL8370_REG_VLAN_PPB_PRIORITY_ITEM1_CTRL1    0x085a
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM1_CTRL1_PORT7_PRIORITY_OFFSET    12
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM1_CTRL1_PORT7_PRIORITY_MASK    0x7000
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM1_CTRL1_PORT6_PRIORITY_OFFSET    8
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM1_CTRL1_PORT6_PRIORITY_MASK    0x700
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM1_CTRL1_PORT5_PRIORITY_OFFSET    4
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM1_CTRL1_PORT5_PRIORITY_MASK    0x70
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM1_CTRL1_PORT4_PRIORITY_OFFSET    0
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM1_CTRL1_PORT4_PRIORITY_MASK    0x7

#define    RTL8370_REG_VLAN_PPB_PRIORITY_ITEM1_CTRL2    0x085b
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM1_CTRL2_PORT11_PRIORITY_OFFSET    12
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM1_CTRL2_PORT11_PRIORITY_MASK    0x7000
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM1_CTRL2_PORT10_PRIORITY_OFFSET    8
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM1_CTRL2_PORT10_PRIORITY_MASK    0x700
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM1_CTRL2_PORT9_PRIORITY_OFFSET    4
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM1_CTRL2_PORT9_PRIORITY_MASK    0x70
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM1_CTRL2_PORT8_PRIORITY_OFFSET    0
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM1_CTRL2_PORT8_PRIORITY_MASK    0x7

#define    RTL8370_REG_VLAN_PPB_PRIORITY_ITEM1_CTRL3    0x085c
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM1_CTRL3_PORT15_PRIORITY_OFFSET    12
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM1_CTRL3_PORT15_PRIORITY_MASK    0x7000
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM1_CTRL3_PORT14_PRIORITY_OFFSET    8
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM1_CTRL3_PORT14_PRIORITY_MASK    0x700
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM1_CTRL3_PORT13_PRIORITY_OFFSET    4
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM1_CTRL3_PORT13_PRIORITY_MASK    0x70
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM1_CTRL3_PORT12_PRIORITY_OFFSET    0
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM1_CTRL3_PORT12_PRIORITY_MASK    0x7

#define    RTL8370_REG_VLAN_PPB_PRIORITY_ITEM2_CTRL0    0x085d
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM2_CTRL0_PORT3_PRIORITY_OFFSET    12
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM2_CTRL0_PORT3_PRIORITY_MASK    0x7000
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM2_CTRL0_PORT2_PRIORITY_OFFSET    8
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM2_CTRL0_PORT2_PRIORITY_MASK    0x700
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM2_CTRL0_PORT1_PRIORITY_OFFSET    4
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM2_CTRL0_PORT1_PRIORITY_MASK    0x70
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM2_CTRL0_PORT0_PRIORITY_OFFSET    0
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM2_CTRL0_PORT0_PRIORITY_MASK    0x7

#define    RTL8370_REG_VLAN_PPB_PRIORITY_ITEM2_CTRL1    0x085e
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM2_CTRL1_PORT7_PRIORITY_OFFSET    12
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM2_CTRL1_PORT7_PRIORITY_MASK    0x7000
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM2_CTRL1_PORT6_PRIORITY_OFFSET    8
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM2_CTRL1_PORT6_PRIORITY_MASK    0x700
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM2_CTRL1_PORT5_PRIORITY_OFFSET    4
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM2_CTRL1_PORT5_PRIORITY_MASK    0x70
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM2_CTRL1_PORT4_PRIORITY_OFFSET    0
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM2_CTRL1_PORT4_PRIORITY_MASK    0x7

#define    RTL8370_REG_VLAN_PPB_PRIORITY_ITEM2_CTRL2    0x085f
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM2_CTRL2_PORT11_PRIORITY_OFFSET    12
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM2_CTRL2_PORT11_PRIORITY_MASK    0x7000
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM2_CTRL2_PORT10_PRIORITY_OFFSET    8
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM2_CTRL2_PORT10_PRIORITY_MASK    0x700
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM2_CTRL2_PORT9_PRIORITY_OFFSET    4
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM2_CTRL2_PORT9_PRIORITY_MASK    0x70
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM2_CTRL2_PORT8_PRIORITY_OFFSET    0
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM2_CTRL2_PORT8_PRIORITY_MASK    0x7

#define    RTL8370_REG_VLAN_PPB_PRIORITY_ITEM2_CTRL3    0x0860
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM2_CTRL3_PORT15_PRIORITY_OFFSET    12
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM2_CTRL3_PORT15_PRIORITY_MASK    0x7000
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM2_CTRL3_PORT14_PRIORITY_OFFSET    8
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM2_CTRL3_PORT14_PRIORITY_MASK    0x700
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM2_CTRL3_PORT13_PRIORITY_OFFSET    4
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM2_CTRL3_PORT13_PRIORITY_MASK    0x70
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM2_CTRL3_PORT12_PRIORITY_OFFSET    0
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM2_CTRL3_PORT12_PRIORITY_MASK    0x7

#define    RTL8370_REG_VLAN_PPB_PRIORITY_ITEM3_CTRL0    0x0861
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM3_CTRL0_PORT3_PRIORITY_OFFSET    12
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM3_CTRL0_PORT3_PRIORITY_MASK    0x7000
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM3_CTRL0_PORT2_PRIORITY_OFFSET    8
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM3_CTRL0_PORT2_PRIORITY_MASK    0x700
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM3_CTRL0_PORT1_PRIORITY_OFFSET    4
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM3_CTRL0_PORT1_PRIORITY_MASK    0x70
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM3_CTRL0_PORT0_PRIORITY_OFFSET    0
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM3_CTRL0_PORT0_PRIORITY_MASK    0x7

#define    RTL8370_REG_VLAN_PPB_PRIORITY_ITEM3_CTRL1    0x0862
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM3_CTRL1_PORT7_PRIORITY_OFFSET    12
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM3_CTRL1_PORT7_PRIORITY_MASK    0x7000
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM3_CTRL1_PORT6_PRIORITY_OFFSET    8
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM3_CTRL1_PORT6_PRIORITY_MASK    0x700
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM3_CTRL1_PORT5_PRIORITY_OFFSET    4
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM3_CTRL1_PORT5_PRIORITY_MASK    0x70
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM3_CTRL1_PORT4_PRIORITY_OFFSET    0
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM3_CTRL1_PORT4_PRIORITY_MASK    0x7

#define    RTL8370_REG_VLAN_PPB_PRIORITY_ITEM3_CTRL2    0x0863
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM3_CTRL2_PORT11_PRIORITY_OFFSET    12
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM3_CTRL2_PORT11_PRIORITY_MASK    0x7000
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM3_CTRL2_PORT10_PRIORITY_OFFSET    8
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM3_CTRL2_PORT10_PRIORITY_MASK    0x700
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM3_CTRL2_PORT9_PRIORITY_OFFSET    4
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM3_CTRL2_PORT9_PRIORITY_MASK    0x70
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM3_CTRL2_PORT8_PRIORITY_OFFSET    0
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM3_CTRL2_PORT8_PRIORITY_MASK    0x7

#define    RTL8370_REG_VLAN_PPB_PRIORITY_ITEM3_CTRL3    0x0864
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM3_CTRL3_PORT15_PRIORITY_OFFSET    12
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM3_CTRL3_PORT15_PRIORITY_MASK    0x7000
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM3_CTRL3_PORT14_PRIORITY_OFFSET    8
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM3_CTRL3_PORT14_PRIORITY_MASK    0x700
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM3_CTRL3_PORT13_PRIORITY_OFFSET    4
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM3_CTRL3_PORT13_PRIORITY_MASK    0x70
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM3_CTRL3_PORT12_PRIORITY_OFFSET    0
#define    RTL8370_VLAN_PPB_PRIORITY_ITEM3_CTRL3_PORT12_PRIORITY_MASK    0x7

#define    RTL8370_REG_QOS_1Q_PRIORITY_REMAPPING_CTRL0    0x0865
#define    RTL8370_QOS_1Q_PRIORITY_REMAPPING_CTRL0_PRIORITY3_OFFSET    12
#define    RTL8370_QOS_1Q_PRIORITY_REMAPPING_CTRL0_PRIORITY3_MASK    0x7000
#define    RTL8370_QOS_1Q_PRIORITY_REMAPPING_CTRL0_PRIORITY2_OFFSET    8
#define    RTL8370_QOS_1Q_PRIORITY_REMAPPING_CTRL0_PRIORITY2_MASK    0x700
#define    RTL8370_QOS_1Q_PRIORITY_REMAPPING_CTRL0_PRIORITY1_OFFSET    4
#define    RTL8370_QOS_1Q_PRIORITY_REMAPPING_CTRL0_PRIORITY1_MASK    0x70
#define    RTL8370_QOS_1Q_PRIORITY_REMAPPING_CTRL0_PRIORITY0_OFFSET    0
#define    RTL8370_QOS_1Q_PRIORITY_REMAPPING_CTRL0_PRIORITY0_MASK    0x7

#define    RTL8370_REG_QOS_1Q_PRIORITY_REMAPPING_CTRL1    0x0866
#define    RTL8370_QOS_1Q_PRIORITY_REMAPPING_CTRL1_PRIORITY7_OFFSET    12
#define    RTL8370_QOS_1Q_PRIORITY_REMAPPING_CTRL1_PRIORITY7_MASK    0x7000
#define    RTL8370_QOS_1Q_PRIORITY_REMAPPING_CTRL1_PRIORITY6_OFFSET    8
#define    RTL8370_QOS_1Q_PRIORITY_REMAPPING_CTRL1_PRIORITY6_MASK    0x700
#define    RTL8370_QOS_1Q_PRIORITY_REMAPPING_CTRL1_PRIORITY5_OFFSET    4
#define    RTL8370_QOS_1Q_PRIORITY_REMAPPING_CTRL1_PRIORITY5_MASK    0x70
#define    RTL8370_QOS_1Q_PRIORITY_REMAPPING_CTRL1_PRIORITY4_OFFSET    0
#define    RTL8370_QOS_1Q_PRIORITY_REMAPPING_CTRL1_PRIORITY4_MASK    0x7

#define    RTL8370_REG_QOS_DSCP_TO_PRIORITY_CTRL0    0x0867
#define    RTL8370_DSCP3_PRIORITY_OFFSET    12
#define    RTL8370_DSCP3_PRIORITY_MASK    0x7000
#define    RTL8370_DSCP2_PRIORITY_OFFSET    8
#define    RTL8370_DSCP2_PRIORITY_MASK    0x700
#define    RTL8370_DSCP1_PRIORITY_OFFSET    4
#define    RTL8370_DSCP1_PRIORITY_MASK    0x70
#define    RTL8370_DSCP0_PRIORITY_OFFSET    0
#define    RTL8370_DSCP0_PRIORITY_MASK    0x7

#define    RTL8370_REG_QOS_DSCP_TO_PRIORITY_CTRL1    0x0868
#define    RTL8370_DSCP7_PRIORITY_OFFSET    12
#define    RTL8370_DSCP7_PRIORITY_MASK    0x7000
#define    RTL8370_DSCP6_PRIORITY_OFFSET    8
#define    RTL8370_DSCP6_PRIORITY_MASK    0x700
#define    RTL8370_DSCP5_PRIORITY_OFFSET    4
#define    RTL8370_DSCP5_PRIORITY_MASK    0x70
#define    RTL8370_DSCP4_PRIORITY_OFFSET    0
#define    RTL8370_DSCP4_PRIORITY_MASK    0x7

#define    RTL8370_REG_QOS_DSCP_TO_PRIORITY_CTRL2    0x0869
#define    RTL8370_DSCP11_PRIORITY_OFFSET    12
#define    RTL8370_DSCP11_PRIORITY_MASK    0x7000
#define    RTL8370_DSCP10_PRIORITY_OFFSET    8
#define    RTL8370_DSCP10_PRIORITY_MASK    0x700
#define    RTL8370_DSCP9_PRIORITY_OFFSET    4
#define    RTL8370_DSCP9_PRIORITY_MASK    0x70
#define    RTL8370_DSCP8_PRIORITY_OFFSET    0
#define    RTL8370_DSCP8_PRIORITY_MASK    0x7

#define    RTL8370_REG_QOS_DSCP_TO_PRIORITY_CTRL3    0x086a
#define    RTL8370_DSCP15_PRIORITY_OFFSET    12
#define    RTL8370_DSCP15_PRIORITY_MASK    0x7000
#define    RTL8370_DSCP14_PRIORITY_OFFSET    8
#define    RTL8370_DSCP14_PRIORITY_MASK    0x700
#define    RTL8370_DSCP13_PRIORITY_OFFSET    4
#define    RTL8370_DSCP13_PRIORITY_MASK    0x70
#define    RTL8370_DSCP12_PRIORITY_OFFSET    0
#define    RTL8370_DSCP12_PRIORITY_MASK    0x7

#define    RTL8370_REG_QOS_DSCP_TO_PRIORITY_CTRL4    0x086b
#define    RTL8370_DSCP19_PRIORITY_OFFSET    12
#define    RTL8370_DSCP19_PRIORITY_MASK    0x7000
#define    RTL8370_DSCP18_PRIORITY_OFFSET    8
#define    RTL8370_DSCP18_PRIORITY_MASK    0x700
#define    RTL8370_DSCP17_PRIORITY_OFFSET    4
#define    RTL8370_DSCP17_PRIORITY_MASK    0x70
#define    RTL8370_DSCP16_PRIORITY_OFFSET    0
#define    RTL8370_DSCP16_PRIORITY_MASK    0x7

#define    RTL8370_REG_QOS_DSCP_TO_PRIORITY_CTRL5    0x086c
#define    RTL8370_DSCP23_PRIORITY_OFFSET    12
#define    RTL8370_DSCP23_PRIORITY_MASK    0x7000
#define    RTL8370_DSCP22_PRIORITY_OFFSET    8
#define    RTL8370_DSCP22_PRIORITY_MASK    0x700
#define    RTL8370_DSCP21_PRIORITY_OFFSET    4
#define    RTL8370_DSCP21_PRIORITY_MASK    0x70
#define    RTL8370_DSCP20_PRIORITY_OFFSET    0
#define    RTL8370_DSCP20_PRIORITY_MASK    0x7

#define    RTL8370_REG_QOS_DSCP_TO_PRIORITY_CTRL6    0x086d
#define    RTL8370_DSCP27_PRIORITY_OFFSET    12
#define    RTL8370_DSCP27_PRIORITY_MASK    0x7000
#define    RTL8370_DSCP26_PRIORITY_OFFSET    8
#define    RTL8370_DSCP26_PRIORITY_MASK    0x700
#define    RTL8370_DSCP25_PRIORITY_OFFSET    4
#define    RTL8370_DSCP25_PRIORITY_MASK    0x70
#define    RTL8370_DSCP24_PRIORITY_OFFSET    0
#define    RTL8370_DSCP24_PRIORITY_MASK    0x7

#define    RTL8370_REG_QOS_DSCP_TO_PRIORITY_CTRL7    0x086e
#define    RTL8370_DSCP31_PRIORITY_OFFSET    12
#define    RTL8370_DSCP31_PRIORITY_MASK    0x7000
#define    RTL8370_DSCP30_PRIORITY_OFFSET    8
#define    RTL8370_DSCP30_PRIORITY_MASK    0x700
#define    RTL8370_DSCP29_PRIORITY_OFFSET    4
#define    RTL8370_DSCP29_PRIORITY_MASK    0x70
#define    RTL8370_DSCP28_PRIORITY_OFFSET    0
#define    RTL8370_DSCP28_PRIORITY_MASK    0x7

#define    RTL8370_REG_QOS_DSCP_TO_PRIORITY_CTRL8    0x086f
#define    RTL8370_DSCP35_PRIORITY_OFFSET    12
#define    RTL8370_DSCP35_PRIORITY_MASK    0x7000
#define    RTL8370_DSCP34_PRIORITY_OFFSET    8
#define    RTL8370_DSCP34_PRIORITY_MASK    0x700
#define    RTL8370_DSCP33_PRIORITY_OFFSET    4
#define    RTL8370_DSCP33_PRIORITY_MASK    0x70
#define    RTL8370_DSCP32_PRIORITY_OFFSET    0
#define    RTL8370_DSCP32_PRIORITY_MASK    0x7

#define    RTL8370_REG_QOS_DSCP_TO_PRIORITY_CTRL9    0x0870
#define    RTL8370_DSCP39_PRIORITY_OFFSET    12
#define    RTL8370_DSCP39_PRIORITY_MASK    0x7000
#define    RTL8370_DSCP38_PRIORITY_OFFSET    8
#define    RTL8370_DSCP38_PRIORITY_MASK    0x700
#define    RTL8370_DSCP37_PRIORITY_OFFSET    4
#define    RTL8370_DSCP37_PRIORITY_MASK    0x70
#define    RTL8370_DSCP36_PRIORITY_OFFSET    0
#define    RTL8370_DSCP36_PRIORITY_MASK    0x7

#define    RTL8370_REG_QOS_DSCP_TO_PRIORITY_CTRL10    0x0871
#define    RTL8370_DSCP43_PRIORITY_OFFSET    12
#define    RTL8370_DSCP43_PRIORITY_MASK    0x7000
#define    RTL8370_DSCP42_PRIORITY_OFFSET    8
#define    RTL8370_DSCP42_PRIORITY_MASK    0x700
#define    RTL8370_DSCP41_PRIORITY_OFFSET    4
#define    RTL8370_DSCP41_PRIORITY_MASK    0x70
#define    RTL8370_DSCP40_PRIORITY_OFFSET    0
#define    RTL8370_DSCP40_PRIORITY_MASK    0x7

#define    RTL8370_REG_QOS_DSCP_TO_PRIORITY_CTRL11    0x0872
#define    RTL8370_DSCP47_PRIORITY_OFFSET    12
#define    RTL8370_DSCP47_PRIORITY_MASK    0x7000
#define    RTL8370_DSCP46_PRIORITY_OFFSET    8
#define    RTL8370_DSCP46_PRIORITY_MASK    0x700
#define    RTL8370_DSCP45_PRIORITY_OFFSET    4
#define    RTL8370_DSCP45_PRIORITY_MASK    0x70
#define    RTL8370_DSCP44_PRIORITY_OFFSET    0
#define    RTL8370_DSCP44_PRIORITY_MASK    0x7

#define    RTL8370_REG_QOS_DSCP_TO_PRIORITY_CTRL12    0x0873
#define    RTL8370_DSCP51_PRIORITY_OFFSET    12
#define    RTL8370_DSCP51_PRIORITY_MASK    0x7000
#define    RTL8370_DSCP50_PRIORITY_OFFSET    8
#define    RTL8370_DSCP50_PRIORITY_MASK    0x700
#define    RTL8370_DSCP49_PRIORITY_OFFSET    4
#define    RTL8370_DSCP49_PRIORITY_MASK    0x70
#define    RTL8370_DSCP48_PRIORITY_OFFSET    0
#define    RTL8370_DSCP48_PRIORITY_MASK    0x7

#define    RTL8370_REG_QOS_DSCP_TO_PRIORITY_CTRL13    0x0874
#define    RTL8370_DSCP55_PRIORITY_OFFSET    12
#define    RTL8370_DSCP55_PRIORITY_MASK    0x7000
#define    RTL8370_DSCP54_PRIORITY_OFFSET    8
#define    RTL8370_DSCP54_PRIORITY_MASK    0x700
#define    RTL8370_DSCP53_PRIORITY_OFFSET    4
#define    RTL8370_DSCP53_PRIORITY_MASK    0x70
#define    RTL8370_DSCP52_PRIORITY_OFFSET    0
#define    RTL8370_DSCP52_PRIORITY_MASK    0x7

#define    RTL8370_REG_QOS_DSCP_TO_PRIORITY_CTRL14    0x0875
#define    RTL8370_DSCP59_PRIORITY_OFFSET    12
#define    RTL8370_DSCP59_PRIORITY_MASK    0x7000
#define    RTL8370_DSCP58_PRIORITY_OFFSET    8
#define    RTL8370_DSCP58_PRIORITY_MASK    0x700
#define    RTL8370_DSCP57_PRIORITY_OFFSET    4
#define    RTL8370_DSCP57_PRIORITY_MASK    0x70
#define    RTL8370_DSCP56_PRIORITY_OFFSET    0
#define    RTL8370_DSCP56_PRIORITY_MASK    0x7

#define    RTL8370_REG_QOS_DSCP_TO_PRIORITY_CTRL15    0x0876
#define    RTL8370_DSCP63_PRIORITY_OFFSET    12
#define    RTL8370_DSCP63_PRIORITY_MASK    0x7000
#define    RTL8370_DSCP62_PRIORITY_OFFSET    8
#define    RTL8370_DSCP62_PRIORITY_MASK    0x700
#define    RTL8370_DSCP61_PRIORITY_OFFSET    4
#define    RTL8370_DSCP61_PRIORITY_MASK    0x70
#define    RTL8370_DSCP60_PRIORITY_OFFSET    0
#define    RTL8370_DSCP60_PRIORITY_MASK    0x7

#define    RTL8370_REG_QOS_PORTBASED_PRIORITY_CTRL0    0x0877
#define    RTL8370_QOS_PORTBASED_PRIORITY_CTRL0_PORT3_PRIORITY_OFFSET    12
#define    RTL8370_QOS_PORTBASED_PRIORITY_CTRL0_PORT3_PRIORITY_MASK    0x7000
#define    RTL8370_QOS_PORTBASED_PRIORITY_CTRL0_PORT2_PRIORITY_OFFSET    8
#define    RTL8370_QOS_PORTBASED_PRIORITY_CTRL0_PORT2_PRIORITY_MASK    0x700
#define    RTL8370_QOS_PORTBASED_PRIORITY_CTRL0_PORT1_PRIORITY_OFFSET    4
#define    RTL8370_QOS_PORTBASED_PRIORITY_CTRL0_PORT1_PRIORITY_MASK    0x70
#define    RTL8370_QOS_PORTBASED_PRIORITY_CTRL0_PORT0_PRIORITY_OFFSET    0
#define    RTL8370_QOS_PORTBASED_PRIORITY_CTRL0_PORT0_PRIORITY_MASK    0x7

#define    RTL8370_REG_QOS_PORTBASED_PRIORITY_CTRL1    0x0878
#define    RTL8370_QOS_PORTBASED_PRIORITY_CTRL1_PORT7_PRIORITY_OFFSET    12
#define    RTL8370_QOS_PORTBASED_PRIORITY_CTRL1_PORT7_PRIORITY_MASK    0x7000
#define    RTL8370_QOS_PORTBASED_PRIORITY_CTRL1_PORT6_PRIORITY_OFFSET    8
#define    RTL8370_QOS_PORTBASED_PRIORITY_CTRL1_PORT6_PRIORITY_MASK    0x700
#define    RTL8370_QOS_PORTBASED_PRIORITY_CTRL1_PORT5_PRIORITY_OFFSET    4
#define    RTL8370_QOS_PORTBASED_PRIORITY_CTRL1_PORT5_PRIORITY_MASK    0x70
#define    RTL8370_QOS_PORTBASED_PRIORITY_CTRL1_PORT4_PRIORITY_OFFSET    0
#define    RTL8370_QOS_PORTBASED_PRIORITY_CTRL1_PORT4_PRIORITY_MASK    0x7

#define    RTL8370_REG_QOS_PORTBASED_PRIORITY_CTRL2    0x0879
#define    RTL8370_QOS_PORTBASED_PRIORITY_CTRL2_PORT11_PRIORITY_OFFSET    12
#define    RTL8370_QOS_PORTBASED_PRIORITY_CTRL2_PORT11_PRIORITY_MASK    0x7000
#define    RTL8370_QOS_PORTBASED_PRIORITY_CTRL2_PORT10_PRIORITY_OFFSET    8
#define    RTL8370_QOS_PORTBASED_PRIORITY_CTRL2_PORT10_PRIORITY_MASK    0x700
#define    RTL8370_QOS_PORTBASED_PRIORITY_CTRL2_PORT9_PRIORITY_OFFSET    4
#define    RTL8370_QOS_PORTBASED_PRIORITY_CTRL2_PORT9_PRIORITY_MASK    0x70
#define    RTL8370_QOS_PORTBASED_PRIORITY_CTRL2_PORT8_PRIORITY_OFFSET    0
#define    RTL8370_QOS_PORTBASED_PRIORITY_CTRL2_PORT8_PRIORITY_MASK    0x7

#define    RTL8370_REG_QOS_PORTBASED_PRIORITY_CTRL3    0x087a
#define    RTL8370_QOS_PORTBASED_PRIORITY_CTRL3_PORT15_PRIORITY_OFFSET    12
#define    RTL8370_QOS_PORTBASED_PRIORITY_CTRL3_PORT15_PRIORITY_MASK    0x7000
#define    RTL8370_QOS_PORTBASED_PRIORITY_CTRL3_PORT14_PRIORITY_OFFSET    8
#define    RTL8370_QOS_PORTBASED_PRIORITY_CTRL3_PORT14_PRIORITY_MASK    0x700
#define    RTL8370_QOS_PORTBASED_PRIORITY_CTRL3_PORT13_PRIORITY_OFFSET    4
#define    RTL8370_QOS_PORTBASED_PRIORITY_CTRL3_PORT13_PRIORITY_MASK    0x70
#define    RTL8370_QOS_PORTBASED_PRIORITY_CTRL3_PORT12_PRIORITY_OFFSET    0
#define    RTL8370_QOS_PORTBASED_PRIORITY_CTRL3_PORT12_PRIORITY_MASK    0x7

#define    RTL8370_REG_QOS_INTERNAL_PRIORITY_DECISION_CTRL0    0x087b
#define    RTL8370_QOS_ACL_WEIGHT_OFFSET    8
#define    RTL8370_QOS_ACL_WEIGHT_MASK    0xFF00
#define    RTL8370_QOS_PORT_WEIGHT_OFFSET    0
#define    RTL8370_QOS_PORT_WEIGHT_MASK    0xFF

#define    RTL8370_REG_QOS_INTERNAL_PRIORITY_DECISION_CTRL1    0x087c
#define    RTL8370_QOS_DOT1Q_WEIGHT_OFFSET    8
#define    RTL8370_QOS_DOT1Q_WEIGHT_MASK    0xFF00
#define    RTL8370_QOS_DSCP_WEIGHT_OFFSET    0
#define    RTL8370_QOS_DSCP_WEIGHT_MASK    0xFF

#define    RTL8370_REG_QOS_INTERNAL_PRIORITY_DECISION_CTRL2    0x087d
#define    RTL8370_QOS_CVLAN_WEIGHT_OFFSET    8
#define    RTL8370_QOS_CVLAN_WEIGHT_MASK    0xFF00
#define    RTL8370_QOS_SVLAN_WEIGHT_OFFSET    0
#define    RTL8370_QOS_SVLAN_WEIGHT_MASK    0xFF

#define    RTL8370_REG_QOS_INTERNAL_PRIORITY_DECISION_CTRL3    0x087e
#define    RTL8370_QOS_SA_WEIGHT_OFFSET    8
#define    RTL8370_QOS_SA_WEIGHT_MASK    0xFF00
#define    RTL8370_QOS_DA_WEIGHT_OFFSET    0
#define    RTL8370_QOS_DA_WEIGHT_MASK    0xFF

#define    RTL8370_REG_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0    0x087f
#define    RTL8370_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0_PRIORITY3_OFFSET    12
#define    RTL8370_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0_PRIORITY3_MASK    0x7000
#define    RTL8370_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0_PRIORITY2_OFFSET    8
#define    RTL8370_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0_PRIORITY2_MASK    0x700
#define    RTL8370_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0_PRIORITY1_OFFSET    4
#define    RTL8370_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0_PRIORITY1_MASK    0x70
#define    RTL8370_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0_PRIORITY0_OFFSET    0
#define    RTL8370_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0_PRIORITY0_MASK    0x7

#define    RTL8370_REG_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL1    0x0880
#define    RTL8370_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL1_PRIORITY7_OFFSET    12
#define    RTL8370_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL1_PRIORITY7_MASK    0x7000
#define    RTL8370_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL1_PRIORITY6_OFFSET    8
#define    RTL8370_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL1_PRIORITY6_MASK    0x700
#define    RTL8370_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL1_PRIORITY5_OFFSET    4
#define    RTL8370_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL1_PRIORITY5_MASK    0x70
#define    RTL8370_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL1_PRIORITY4_OFFSET    0
#define    RTL8370_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL1_PRIORITY4_MASK    0x7

#define    RTL8370_REG_QOS_TRAP_PRIORITY0    0x0881
#define    RTL8370_UNKNOWN_MC_PRIORTY_OFFSET    12
#define    RTL8370_UNKNOWN_MC_PRIORTY_MASK    0x7000
#define    RTL8370_SVLAN_PRIOIRTY_OFFSET    8
#define    RTL8370_SVLAN_PRIOIRTY_MASK    0x700
#define    RTL8370_OAM_PRIOIRTY_OFFSET    4
#define    RTL8370_OAM_PRIOIRTY_MASK    0x70
#define    RTL8370_DOT1X_PRIORTY_OFFSET    0
#define    RTL8370_DOT1X_PRIORTY_MASK    0x7

#define    RTL8370_REG_QOS_TRAP_PRIORITY1    0x0882
#define    RTL8370_DW8051_TRAP_PRI_OFFSET    4
#define    RTL8370_DW8051_TRAP_PRI_MASK    0x70
#define    RTL8370_EEELLDP_TRAP_PRI_OFFSET    0
#define    RTL8370_EEELLDP_TRAP_PRI_MASK    0x7

#define    RTL8370_REG_UNUCAST_FLOADING_PMSK    0x0890

#define    RTL8370_REG_UNMCAST_FLOADING_PMSK    0x0891

#define    RTL8370_REG_BCAST_FLOADING_PMSK    0x0892

#define    RTL8370_REG_PORT_ISOLATION_PORT0_MASK    0x08a2

#define    RTL8370_REG_PORT_ISOLATION_PORT1_MASK    0x08a3

#define    RTL8370_REG_PORT_ISOLATION_PORT2_MASK    0x08a4

#define    RTL8370_REG_PORT_ISOLATION_PORT3_MASK    0x08a5

#define    RTL8370_REG_PORT_ISOLATION_PORT4_MASK    0x08a6

#define    RTL8370_REG_PORT_ISOLATION_PORT5_MASK    0x08a7

#define    RTL8370_REG_PORT_ISOLATION_PORT6_MASK    0x08a8

#define    RTL8370_REG_PORT_ISOLATION_PORT7_MASK    0x08a9

#define    RTL8370_REG_PORT_ISOLATION_PORT8_MASK    0x08aa

#define    RTL8370_REG_PORT_ISOLATION_PORT9_MASK    0x08ab

#define    RTL8370_REG_PORT_ISOLATION_PORT10_MASK    0x08ac

#define    RTL8370_REG_PORT_ISOLATION_PORT11_MASK    0x08ad

#define    RTL8370_REG_PORT_ISOLATION_PORT12_MASK    0x08ae

#define    RTL8370_REG_PORT_ISOLATION_PORT13_MASK    0x08af

#define    RTL8370_REG_PORT_ISOLATION_PORT14_MASK    0x08b0

#define    RTL8370_REG_PORT_ISOLATION_PORT15_MASK    0x08b1

#define    RTL8370_REG_FORCE_CTRL    0x08b4
#define    RTL8370_FORCE_CTRL_OFFSET    0
#define    RTL8370_FORCE_CTRL_MASK    0x1

#define    RTL8370_REG_FORCE_PORT0_MASK    0x08b5

#define    RTL8370_REG_FORCE_PORT1_MASK    0x08b6

#define    RTL8370_REG_FORCE_PORT2_MASK    0x08b7

#define    RTL8370_REG_FORCE_PORT3_MASK    0x08b8

#define    RTL8370_REG_FORCE_PORT4_MASK    0x08b9

#define    RTL8370_REG_FORCE_PORT5_MASK    0x08ba

#define    RTL8370_REG_FORCE_PORT6_MASK    0x08bb

#define    RTL8370_REG_FORCE_PORT7_MASK    0x08bc

#define    RTL8370_REG_FORCE_PORT8_MASK    0x08bd

#define    RTL8370_REG_FORCE_PORT9_MASK    0x08be

#define    RTL8370_REG_FORCE_PORT10_MASK    0x08bf

#define    RTL8370_REG_FORCE_PORT11_MASK    0x08c0

#define    RTL8370_REG_FORCE_PORT12_MASK    0x08c1

#define    RTL8370_REG_FORCE_PORT13_MASK    0x08c2

#define    RTL8370_REG_FORCE_PORT14_MASK    0x08c3

#define    RTL8370_REG_FORCE_PORT15_MASK    0x08c4

#define    RTL8370_REG_SOURCE_PORT_BLOCK    0x08c5

#define    RTL8370_REG_IPMCAST_VLAN_LEAKY    0x08c6

#define    RTL8370_REG_IPMCAST_PORTISO_LEAKY    0x08c7

#define    RTL8370_REG_PORT_SECURITY_CTRL    0x08c8
#define    RTL8370_UNKNOWN_UNICAST_DA_BEHAVE_OFFSET    6
#define    RTL8370_UNKNOWN_UNICAST_DA_BEHAVE_MASK    0xC0
#define    RTL8370_LUT_LEARN_OVER_ACT_OFFSET    4
#define    RTL8370_LUT_LEARN_OVER_ACT_MASK    0x30
#define    RTL8370_UNMATCHED_SA_BEHAVE_OFFSET    2
#define    RTL8370_UNMATCHED_SA_BEHAVE_MASK    0xC
#define    RTL8370_UNKNOW_SA_BEHAVE_OFFSET    0
#define    RTL8370_UNKNOW_SA_BEHAVE_MASK    0x3

#define    RTL8370_REG_UNKNOWN_IPV4_MULTICAST_CRTL0    0x08c9
#define    RTL8370_PORT7_UNKNOWN_IP4_MCAST_OFFSET    14
#define    RTL8370_PORT7_UNKNOWN_IP4_MCAST_MASK    0xC000
#define    RTL8370_PORT6_UNKNOWN_IP4_MCAST_OFFSET    12
#define    RTL8370_PORT6_UNKNOWN_IP4_MCAST_MASK    0x3000
#define    RTL8370_PORT5_UNKNOWN_IP4_MCAST_OFFSET    10
#define    RTL8370_PORT5_UNKNOWN_IP4_MCAST_MASK    0xC00
#define    RTL8370_PORT4_UNKNOWN_IP4_MCAST_OFFSET    8
#define    RTL8370_PORT4_UNKNOWN_IP4_MCAST_MASK    0x300
#define    RTL8370_PORT3_UNKNOWN_IP4_MCAST_OFFSET    6
#define    RTL8370_PORT3_UNKNOWN_IP4_MCAST_MASK    0xC0
#define    RTL8370_PORT2_UNKNOWN_IP4_MCAST_OFFSET    4
#define    RTL8370_PORT2_UNKNOWN_IP4_MCAST_MASK    0x30
#define    RTL8370_PORT1_UNKNOWN_IP4_MCAST_OFFSET    2
#define    RTL8370_PORT1_UNKNOWN_IP4_MCAST_MASK    0xC
#define    RTL8370_PORT0_UNKNOWN_IP4_MCAST_OFFSET    0
#define    RTL8370_PORT0_UNKNOWN_IP4_MCAST_MASK    0x3

#define    RTL8370_REG_UNKNOWN_IPV4_MULTICAST_CRTL1    0x08ca
#define    RTL8370_PORT15_UNKNOWN_IP4_MCAST_OFFSET    14
#define    RTL8370_PORT15_UNKNOWN_IP4_MCAST_MASK    0xC000
#define    RTL8370_PORT14_UNKNOWN_IP4_MCAST_OFFSET    12
#define    RTL8370_PORT14_UNKNOWN_IP4_MCAST_MASK    0x3000
#define    RTL8370_PORT13_UNKNOWN_IP4_MCAST_OFFSET    10
#define    RTL8370_PORT13_UNKNOWN_IP4_MCAST_MASK    0xC00
#define    RTL8370_PORT12_UNKNOWN_IP4_MCAST_OFFSET    8
#define    RTL8370_PORT12_UNKNOWN_IP4_MCAST_MASK    0x300
#define    RTL8370_PORT11_UNKNOWN_IP4_MCAST_OFFSET    6
#define    RTL8370_PORT11_UNKNOWN_IP4_MCAST_MASK    0xC0
#define    RTL8370_PORT10_UNKNOWN_IP4_MCAST_OFFSET    4
#define    RTL8370_PORT10_UNKNOWN_IP4_MCAST_MASK    0x30
#define    RTL8370_PORT9_UNKNOWN_IP4_MCAST_OFFSET    2
#define    RTL8370_PORT9_UNKNOWN_IP4_MCAST_MASK    0xC
#define    RTL8370_PORT8_UNKNOWN_IP4_MCAST_OFFSET    0
#define    RTL8370_PORT8_UNKNOWN_IP4_MCAST_MASK    0x3

#define    RTL8370_REG_UNKNOWN_IPV6_MULTICAST_CRTL0    0x08cb
#define    RTL8370_PORT7_UNKNOWN_IP6_MCAST_OFFSET    14
#define    RTL8370_PORT7_UNKNOWN_IP6_MCAST_MASK    0xC000
#define    RTL8370_PORT6_UNKNOWN_IP6_MCAST_OFFSET    12
#define    RTL8370_PORT6_UNKNOWN_IP6_MCAST_MASK    0x3000
#define    RTL8370_PORT5_UNKNOWN_IP6_MCAST_OFFSET    10
#define    RTL8370_PORT5_UNKNOWN_IP6_MCAST_MASK    0xC00
#define    RTL8370_PORT4_UNKNOWN_IP6_MCAST_OFFSET    8
#define    RTL8370_PORT4_UNKNOWN_IP6_MCAST_MASK    0x300
#define    RTL8370_PORT3_UNKNOWN_IP6_MCAST_OFFSET    6
#define    RTL8370_PORT3_UNKNOWN_IP6_MCAST_MASK    0xC0
#define    RTL8370_PORT2_UNKNOWN_IP6_MCAST_OFFSET    4
#define    RTL8370_PORT2_UNKNOWN_IP6_MCAST_MASK    0x30
#define    RTL8370_PORT1_UNKNOWN_IP6_MCAST_OFFSET    2
#define    RTL8370_PORT1_UNKNOWN_IP6_MCAST_MASK    0xC
#define    RTL8370_PORT0_UNKNOWN_IP6_MCAST_OFFSET    0
#define    RTL8370_PORT0_UNKNOWN_IP6_MCAST_MASK    0x3

#define    RTL8370_REG_UNKNOWN_IPV6_MULTICAST_CRTL1    0x08cc
#define    RTL8370_PORT15_UNKNOWN_IP6_MCAST_OFFSET    14
#define    RTL8370_PORT15_UNKNOWN_IP6_MCAST_MASK    0xC000
#define    RTL8370_PORT14_UNKNOWN_IP6_MCAST_OFFSET    12
#define    RTL8370_PORT14_UNKNOWN_IP6_MCAST_MASK    0x3000
#define    RTL8370_PORT13_UNKNOWN_IP6_MCAST_OFFSET    10
#define    RTL8370_PORT13_UNKNOWN_IP6_MCAST_MASK    0xC00
#define    RTL8370_PORT12_UNKNOWN_IP6_MCAST_OFFSET    8
#define    RTL8370_PORT12_UNKNOWN_IP6_MCAST_MASK    0x300
#define    RTL8370_PORT11_UNKNOWN_IP6_MCAST_OFFSET    6
#define    RTL8370_PORT11_UNKNOWN_IP6_MCAST_MASK    0xC0
#define    RTL8370_PORT10_UNKNOWN_IP6_MCAST_OFFSET    4
#define    RTL8370_PORT10_UNKNOWN_IP6_MCAST_MASK    0x30
#define    RTL8370_PORT9_UNKNOWN_IP6_MCAST_OFFSET    2
#define    RTL8370_PORT9_UNKNOWN_IP6_MCAST_MASK    0xC
#define    RTL8370_PORT8_UNKNOWN_IP6_MCAST_OFFSET    0
#define    RTL8370_PORT8_UNKNOWN_IP6_MCAST_MASK    0x3

#define    RTL8370_REG_UNKNOWN_L2_MULTICAST_CRTL0    0x08cd
#define    RTL8370_PORT7_UNKNOWN_L2_MCAST_OFFSET    14
#define    RTL8370_PORT7_UNKNOWN_L2_MCAST_MASK    0xC000
#define    RTL8370_PORT6_UNKNOWN_L2_MCAST_OFFSET    12
#define    RTL8370_PORT6_UNKNOWN_L2_MCAST_MASK    0x3000
#define    RTL8370_PORT5_UNKNOWN_L2_MCAST_OFFSET    10
#define    RTL8370_PORT5_UNKNOWN_L2_MCAST_MASK    0xC00
#define    RTL8370_PORT4_UNKNOWN_L2_MCAST_OFFSET    8
#define    RTL8370_PORT4_UNKNOWN_L2_MCAST_MASK    0x300
#define    RTL8370_PORT3_UNKNOWN_L2_MCAST_OFFSET    6
#define    RTL8370_PORT3_UNKNOWN_L2_MCAST_MASK    0xC0
#define    RTL8370_PORT2_UNKNOWN_L2_MCAST_OFFSET    4
#define    RTL8370_PORT2_UNKNOWN_L2_MCAST_MASK    0x30
#define    RTL8370_PORT1_UNKNOWN_L2_MCAST_OFFSET    2
#define    RTL8370_PORT1_UNKNOWN_L2_MCAST_MASK    0xC
#define    RTL8370_PORT0_UNKNOWN_L2_MCAST_OFFSET    0
#define    RTL8370_PORT0_UNKNOWN_L2_MCAST_MASK    0x3

#define    RTL8370_REG_UNKNOWN_L2_MULTICAST_CRTL1    0x08ce
#define    RTL8370_PORT15_UNKNOWN_L2_MCAST_OFFSET    14
#define    RTL8370_PORT15_UNKNOWN_L2_MCAST_MASK    0xC000
#define    RTL8370_PORT14_UNKNOWN_L2_MCAST_OFFSET    12
#define    RTL8370_PORT14_UNKNOWN_L2_MCAST_MASK    0x3000
#define    RTL8370_PORT13_UNKNOWN_L2_MCAST_OFFSET    10
#define    RTL8370_PORT13_UNKNOWN_L2_MCAST_MASK    0xC00
#define    RTL8370_PORT12_UNKNOWN_L2_MCAST_OFFSET    8
#define    RTL8370_PORT12_UNKNOWN_L2_MCAST_MASK    0x300
#define    RTL8370_PORT11_UNKNOWN_L2_MCAST_OFFSET    6
#define    RTL8370_PORT11_UNKNOWN_L2_MCAST_MASK    0xC0
#define    RTL8370_PORT10_UNKNOWN_L2_MCAST_OFFSET    4
#define    RTL8370_PORT10_UNKNOWN_L2_MCAST_MASK    0x30
#define    RTL8370_PORT9_UNKNOWN_L2_MCAST_OFFSET    2
#define    RTL8370_PORT9_UNKNOWN_L2_MCAST_MASK    0xC
#define    RTL8370_PORT8_UNKNOWN_L2_MCAST_OFFSET    0
#define    RTL8370_PORT8_UNKNOWN_L2_MCAST_MASK    0x3

#define    RTL8370_REG_PORT_TRUNK_CTRL    0x08cf
#define    RTL8370_PORT_TRUNK_FLOOD_OFFSET    7
#define    RTL8370_PORT_TRUNK_FLOOD_MASK    0x80
#define    RTL8370_DPORT_HASH_OFFSET    6
#define    RTL8370_DPORT_HASH_MASK    0x40
#define    RTL8370_SPORT_HASH_OFFSET    5
#define    RTL8370_SPORT_HASH_MASK    0x20
#define    RTL8370_DIP_HASH_OFFSET    4
#define    RTL8370_DIP_HASH_MASK    0x10
#define    RTL8370_SIP_HASH_OFFSET    3
#define    RTL8370_SIP_HASH_MASK    0x8
#define    RTL8370_DMAC_HASH_OFFSET    2
#define    RTL8370_DMAC_HASH_MASK    0x4
#define    RTL8370_SMAC_HASH_OFFSET    1
#define    RTL8370_SMAC_HASH_MASK    0x2
#define    RTL8370_SPA_HASH_OFFSET    0
#define    RTL8370_SPA_HASH_MASK    0x1

#define    RTL8370_REG_PORT_TRUNK_GROUP_MASK    0x08d0
#define    RTL8370_PORT_TRUNK_GROUP3_MASK_OFFSET    12
#define    RTL8370_PORT_TRUNK_GROUP3_MASK_MASK    0xF000
#define    RTL8370_PORT_TRUNK_GROUP2_MASK_OFFSET    8
#define    RTL8370_PORT_TRUNK_GROUP2_MASK_MASK    0xF00
#define    RTL8370_PORT_TRUNK_GROUP1_MASK_OFFSET    4
#define    RTL8370_PORT_TRUNK_GROUP1_MASK_MASK    0xF0
#define    RTL8370_PORT_TRUNK_GROUP0_MASK_OFFSET    0
#define    RTL8370_PORT_TRUNK_GROUP0_MASK_MASK    0xF

#define    RTL8370_REG_PORT_TRUNK_FLOWCTRL    0x08d1

#define    RTL8370_REG_QOS_PORT_QUEUE_NUMBER_CTRL0    0x0900
#define    RTL8370_PORT3_NUMBER_OFFSET    12
#define    RTL8370_PORT3_NUMBER_MASK    0x7000
#define    RTL8370_PORT2_NUMBER_OFFSET    8
#define    RTL8370_PORT2_NUMBER_MASK    0x700
#define    RTL8370_PORT1_NUMBER_OFFSET    4
#define    RTL8370_PORT1_NUMBER_MASK    0x70
#define    RTL8370_PORT0_NUMBER_OFFSET    0
#define    RTL8370_PORT0_NUMBER_MASK    0x7

#define    RTL8370_REG_QOS_PORT_QUEUE_NUMBER_CTRL1    0x0901
#define    RTL8370_PORT7_NUMBER_OFFSET    12
#define    RTL8370_PORT7_NUMBER_MASK    0x7000
#define    RTL8370_PORT6_NUMBER_OFFSET    8
#define    RTL8370_PORT6_NUMBER_MASK    0x700
#define    RTL8370_PORT5_NUMBER_OFFSET    4
#define    RTL8370_PORT5_NUMBER_MASK    0x70
#define    RTL8370_PORT4_NUMBER_OFFSET    0
#define    RTL8370_PORT4_NUMBER_MASK    0x7

#define    RTL8370_REG_QOS_PORT_QUEUE_NUMBER_CTRL2    0x0902
#define    RTL8370_PORT11_NUMBER_OFFSET    12
#define    RTL8370_PORT11_NUMBER_MASK    0x7000
#define    RTL8370_PORT10_NUMBER_OFFSET    8
#define    RTL8370_PORT10_NUMBER_MASK    0x700
#define    RTL8370_PORT9_NUMBER_OFFSET    4
#define    RTL8370_PORT9_NUMBER_MASK    0x70
#define    RTL8370_PORT8_NUMBER_OFFSET    0
#define    RTL8370_PORT8_NUMBER_MASK    0x7

#define    RTL8370_REG_QOS_PORT_QUEUE_NUMBER_CTRL3    0x0903
#define    RTL8370_PORT15_NUMBER_OFFSET    12
#define    RTL8370_PORT15_NUMBER_MASK    0x7000
#define    RTL8370_PORT14_NUMBER_OFFSET    8
#define    RTL8370_PORT14_NUMBER_MASK    0x700
#define    RTL8370_PORT13_NUMBER_OFFSET    4
#define    RTL8370_PORT13_NUMBER_MASK    0x70
#define    RTL8370_PORT12_NUMBER_OFFSET    0
#define    RTL8370_PORT12_NUMBER_MASK    0x7

#define    RTL8370_REG_QOS_1Q_PRIORITY_TO_QID_CRTL0    0x0904
#define    RTL8370_QOS_1Q_PRIORITY_TO_QID_CRTL0_PRIORITY3_TO_QID_OFFSET    12
#define    RTL8370_QOS_1Q_PRIORITY_TO_QID_CRTL0_PRIORITY3_TO_QID_MASK    0x7000
#define    RTL8370_QOS_1Q_PRIORITY_TO_QID_CRTL0_PRIORITY2_TO_QID_OFFSET    8
#define    RTL8370_QOS_1Q_PRIORITY_TO_QID_CRTL0_PRIORITY2_TO_QID_MASK    0x700
#define    RTL8370_QOS_1Q_PRIORITY_TO_QID_CRTL0_PRIORITY1_TO_QID_OFFSET    4
#define    RTL8370_QOS_1Q_PRIORITY_TO_QID_CRTL0_PRIORITY1_TO_QID_MASK    0x70
#define    RTL8370_QOS_1Q_PRIORITY_TO_QID_CRTL0_PRIORITY0_TO_QID_OFFSET    0
#define    RTL8370_QOS_1Q_PRIORITY_TO_QID_CRTL0_PRIORITY0_TO_QID_MASK    0x7

#define    RTL8370_REG_QOS_1Q_PRIORITY_TO_QID_CRTL1    0x0905
#define    RTL8370_QOS_1Q_PRIORITY_TO_QID_CRTL1_PRIORITY7_TO_QID_OFFSET    12
#define    RTL8370_QOS_1Q_PRIORITY_TO_QID_CRTL1_PRIORITY7_TO_QID_MASK    0x7000
#define    RTL8370_QOS_1Q_PRIORITY_TO_QID_CRTL1_PRIORITY6_TO_QID_OFFSET    8
#define    RTL8370_QOS_1Q_PRIORITY_TO_QID_CRTL1_PRIORITY6_TO_QID_MASK    0x700
#define    RTL8370_QOS_1Q_PRIORITY_TO_QID_CRTL1_PRIORITY5_TO_QID_OFFSET    4
#define    RTL8370_QOS_1Q_PRIORITY_TO_QID_CRTL1_PRIORITY5_TO_QID_MASK    0x70
#define    RTL8370_QOS_1Q_PRIORITY_TO_QID_CRTL1_PRIORITY4_TO_QID_OFFSET    0
#define    RTL8370_QOS_1Q_PRIORITY_TO_QID_CRTL1_PRIORITY4_TO_QID_MASK    0x7

#define    RTL8370_REG_QOS_2Q_PRIORITY_TO_QID_CRTL0    0x0906
#define    RTL8370_QOS_2Q_PRIORITY_TO_QID_CRTL0_PRIORITY3_TO_QID_OFFSET    12
#define    RTL8370_QOS_2Q_PRIORITY_TO_QID_CRTL0_PRIORITY3_TO_QID_MASK    0x7000
#define    RTL8370_QOS_2Q_PRIORITY_TO_QID_CRTL0_PRIORITY2_TO_QID_OFFSET    8
#define    RTL8370_QOS_2Q_PRIORITY_TO_QID_CRTL0_PRIORITY2_TO_QID_MASK    0x700
#define    RTL8370_QOS_2Q_PRIORITY_TO_QID_CRTL0_PRIORITY1_TO_QID_OFFSET    4
#define    RTL8370_QOS_2Q_PRIORITY_TO_QID_CRTL0_PRIORITY1_TO_QID_MASK    0x70
#define    RTL8370_QOS_2Q_PRIORITY_TO_QID_CRTL0_PRIORITY0_TO_QID_OFFSET    0
#define    RTL8370_QOS_2Q_PRIORITY_TO_QID_CRTL0_PRIORITY0_TO_QID_MASK    0x7

#define    RTL8370_REG_QOS_2Q_PRIORITY_TO_QID_CRTL1    0x0907
#define    RTL8370_QOS_2Q_PRIORITY_TO_QID_CRTL1_PRIORITY7_TO_QID_OFFSET    12
#define    RTL8370_QOS_2Q_PRIORITY_TO_QID_CRTL1_PRIORITY7_TO_QID_MASK    0x7000
#define    RTL8370_QOS_2Q_PRIORITY_TO_QID_CRTL1_PRIORITY6_TO_QID_OFFSET    8
#define    RTL8370_QOS_2Q_PRIORITY_TO_QID_CRTL1_PRIORITY6_TO_QID_MASK    0x700
#define    RTL8370_QOS_2Q_PRIORITY_TO_QID_CRTL1_PRIORITY5_TO_QID_OFFSET    4
#define    RTL8370_QOS_2Q_PRIORITY_TO_QID_CRTL1_PRIORITY5_TO_QID_MASK    0x70
#define    RTL8370_QOS_2Q_PRIORITY_TO_QID_CRTL1_PRIORITY4_TO_QID_OFFSET    0
#define    RTL8370_QOS_2Q_PRIORITY_TO_QID_CRTL1_PRIORITY4_TO_QID_MASK    0x7

#define    RTL8370_REG_QOS_3Q_PRIORITY_TO_QID_CRTL0    0x0908
#define    RTL8370_QOS_3Q_PRIORITY_TO_QID_CRTL0_PRIORITY3_TO_QID_OFFSET    12
#define    RTL8370_QOS_3Q_PRIORITY_TO_QID_CRTL0_PRIORITY3_TO_QID_MASK    0x7000
#define    RTL8370_QOS_3Q_PRIORITY_TO_QID_CRTL0_PRIORITY2_TO_QID_OFFSET    8
#define    RTL8370_QOS_3Q_PRIORITY_TO_QID_CRTL0_PRIORITY2_TO_QID_MASK    0x700
#define    RTL8370_QOS_3Q_PRIORITY_TO_QID_CRTL0_PRIORITY1_TO_QID_OFFSET    4
#define    RTL8370_QOS_3Q_PRIORITY_TO_QID_CRTL0_PRIORITY1_TO_QID_MASK    0x70
#define    RTL8370_QOS_3Q_PRIORITY_TO_QID_CRTL0_PRIORITY0_TO_QID_OFFSET    0
#define    RTL8370_QOS_3Q_PRIORITY_TO_QID_CRTL0_PRIORITY0_TO_QID_MASK    0x7

#define    RTL8370_REG_QOS_3Q_PRIORITY_TO_QID_CRTL1    0x0909
#define    RTL8370_QOS_3Q_PRIORITY_TO_QID_CRTL1_PRIORITY7_TO_QID_OFFSET    12
#define    RTL8370_QOS_3Q_PRIORITY_TO_QID_CRTL1_PRIORITY7_TO_QID_MASK    0x7000
#define    RTL8370_QOS_3Q_PRIORITY_TO_QID_CRTL1_PRIORITY6_TO_QID_OFFSET    8
#define    RTL8370_QOS_3Q_PRIORITY_TO_QID_CRTL1_PRIORITY6_TO_QID_MASK    0x700
#define    RTL8370_QOS_3Q_PRIORITY_TO_QID_CRTL1_PRIORITY5_TO_QID_OFFSET    4
#define    RTL8370_QOS_3Q_PRIORITY_TO_QID_CRTL1_PRIORITY5_TO_QID_MASK    0x70
#define    RTL8370_QOS_3Q_PRIORITY_TO_QID_CRTL1_PRIORITY4_TO_QID_OFFSET    0
#define    RTL8370_QOS_3Q_PRIORITY_TO_QID_CRTL1_PRIORITY4_TO_QID_MASK    0x7

#define    RTL8370_REG_QOS_4Q_PRIORITY_TO_QID_CRTL0    0x090a
#define    RTL8370_QOS_4Q_PRIORITY_TO_QID_CRTL0_PRIORITY3_TO_QID_OFFSET    12
#define    RTL8370_QOS_4Q_PRIORITY_TO_QID_CRTL0_PRIORITY3_TO_QID_MASK    0x7000
#define    RTL8370_QOS_4Q_PRIORITY_TO_QID_CRTL0_PRIORITY2_TO_QID_OFFSET    8
#define    RTL8370_QOS_4Q_PRIORITY_TO_QID_CRTL0_PRIORITY2_TO_QID_MASK    0x700
#define    RTL8370_QOS_4Q_PRIORITY_TO_QID_CRTL0_PRIORITY1_TO_QID_OFFSET    4
#define    RTL8370_QOS_4Q_PRIORITY_TO_QID_CRTL0_PRIORITY1_TO_QID_MASK    0x70
#define    RTL8370_QOS_4Q_PRIORITY_TO_QID_CRTL0_PRIORITY0_TO_QID_OFFSET    0
#define    RTL8370_QOS_4Q_PRIORITY_TO_QID_CRTL0_PRIORITY0_TO_QID_MASK    0x7

#define    RTL8370_REG_QOS_4Q_PRIORITY_TO_QID_CRTL1    0x090b
#define    RTL8370_QOS_4Q_PRIORITY_TO_QID_CRTL1_PRIORITY7_TO_QID_OFFSET    12
#define    RTL8370_QOS_4Q_PRIORITY_TO_QID_CRTL1_PRIORITY7_TO_QID_MASK    0x7000
#define    RTL8370_QOS_4Q_PRIORITY_TO_QID_CRTL1_PRIORITY6_TO_QID_OFFSET    8
#define    RTL8370_QOS_4Q_PRIORITY_TO_QID_CRTL1_PRIORITY6_TO_QID_MASK    0x700
#define    RTL8370_QOS_4Q_PRIORITY_TO_QID_CRTL1_PRIORITY5_TO_QID_OFFSET    4
#define    RTL8370_QOS_4Q_PRIORITY_TO_QID_CRTL1_PRIORITY5_TO_QID_MASK    0x70
#define    RTL8370_QOS_4Q_PRIORITY_TO_QID_CRTL1_PRIORITY4_TO_QID_OFFSET    0
#define    RTL8370_QOS_4Q_PRIORITY_TO_QID_CRTL1_PRIORITY4_TO_QID_MASK    0x7

#define    RTL8370_REG_QOS_5Q_PRIORITY_TO_QID_CRTL0    0x090c
#define    RTL8370_QOS_5Q_PRIORITY_TO_QID_CRTL0_PRIORITY3_TO_QID_OFFSET    12
#define    RTL8370_QOS_5Q_PRIORITY_TO_QID_CRTL0_PRIORITY3_TO_QID_MASK    0x7000
#define    RTL8370_QOS_5Q_PRIORITY_TO_QID_CRTL0_PRIORITY2_TO_QID_OFFSET    8
#define    RTL8370_QOS_5Q_PRIORITY_TO_QID_CRTL0_PRIORITY2_TO_QID_MASK    0x700
#define    RTL8370_QOS_5Q_PRIORITY_TO_QID_CRTL0_PRIORITY1_TO_QID_OFFSET    4
#define    RTL8370_QOS_5Q_PRIORITY_TO_QID_CRTL0_PRIORITY1_TO_QID_MASK    0x70
#define    RTL8370_QOS_5Q_PRIORITY_TO_QID_CRTL0_PRIORITY0_TO_QID_OFFSET    0
#define    RTL8370_QOS_5Q_PRIORITY_TO_QID_CRTL0_PRIORITY0_TO_QID_MASK    0x7

#define    RTL8370_REG_QOS_5Q_PRIORITY_TO_QID_CRTL1    0x090d
#define    RTL8370_QOS_5Q_PRIORITY_TO_QID_CRTL1_PRIORITY7_TO_QID_OFFSET    12
#define    RTL8370_QOS_5Q_PRIORITY_TO_QID_CRTL1_PRIORITY7_TO_QID_MASK    0x7000
#define    RTL8370_QOS_5Q_PRIORITY_TO_QID_CRTL1_PRIORITY6_TO_QID_OFFSET    8
#define    RTL8370_QOS_5Q_PRIORITY_TO_QID_CRTL1_PRIORITY6_TO_QID_MASK    0x700
#define    RTL8370_QOS_5Q_PRIORITY_TO_QID_CRTL1_PRIORITY5_TO_QID_OFFSET    4
#define    RTL8370_QOS_5Q_PRIORITY_TO_QID_CRTL1_PRIORITY5_TO_QID_MASK    0x70
#define    RTL8370_QOS_5Q_PRIORITY_TO_QID_CRTL1_PRIORITY4_TO_QID_OFFSET    0
#define    RTL8370_QOS_5Q_PRIORITY_TO_QID_CRTL1_PRIORITY4_TO_QID_MASK    0x7

#define    RTL8370_REG_QOS_6Q_PRIORITY_TO_QID_CRTL0    0x090e
#define    RTL8370_QOS_6Q_PRIORITY_TO_QID_CRTL0_PRIORITY3_TO_QID_OFFSET    12
#define    RTL8370_QOS_6Q_PRIORITY_TO_QID_CRTL0_PRIORITY3_TO_QID_MASK    0x7000
#define    RTL8370_QOS_6Q_PRIORITY_TO_QID_CRTL0_PRIORITY2_TO_QID_OFFSET    8
#define    RTL8370_QOS_6Q_PRIORITY_TO_QID_CRTL0_PRIORITY2_TO_QID_MASK    0x700
#define    RTL8370_QOS_6Q_PRIORITY_TO_QID_CRTL0_PRIORITY1_TO_QID_OFFSET    4
#define    RTL8370_QOS_6Q_PRIORITY_TO_QID_CRTL0_PRIORITY1_TO_QID_MASK    0x70
#define    RTL8370_QOS_6Q_PRIORITY_TO_QID_CRTL0_PRIORITY0_TO_QID_OFFSET    0
#define    RTL8370_QOS_6Q_PRIORITY_TO_QID_CRTL0_PRIORITY0_TO_QID_MASK    0x7

#define    RTL8370_REG_QOS_6Q_PRIORITY_TO_QID_CRTL1    0x090f
#define    RTL8370_QOS_6Q_PRIORITY_TO_QID_CRTL1_PRIORITY7_TO_QID_OFFSET    12
#define    RTL8370_QOS_6Q_PRIORITY_TO_QID_CRTL1_PRIORITY7_TO_QID_MASK    0x7000
#define    RTL8370_QOS_6Q_PRIORITY_TO_QID_CRTL1_PRIORITY6_TO_QID_OFFSET    8
#define    RTL8370_QOS_6Q_PRIORITY_TO_QID_CRTL1_PRIORITY6_TO_QID_MASK    0x700
#define    RTL8370_QOS_6Q_PRIORITY_TO_QID_CRTL1_PRIORITY5_TO_QID_OFFSET    4
#define    RTL8370_QOS_6Q_PRIORITY_TO_QID_CRTL1_PRIORITY5_TO_QID_MASK    0x70
#define    RTL8370_QOS_6Q_PRIORITY_TO_QID_CRTL1_PRIORITY4_TO_QID_OFFSET    0
#define    RTL8370_QOS_6Q_PRIORITY_TO_QID_CRTL1_PRIORITY4_TO_QID_MASK    0x7

#define    RTL8370_REG_QOS_7Q_PRIORITY_TO_QID_CRTL0    0x0910
#define    RTL8370_QOS_7Q_PRIORITY_TO_QID_CRTL0_PRIORITY3_TO_QID_OFFSET    12
#define    RTL8370_QOS_7Q_PRIORITY_TO_QID_CRTL0_PRIORITY3_TO_QID_MASK    0x7000
#define    RTL8370_QOS_7Q_PRIORITY_TO_QID_CRTL0_PRIORITY2_TO_QID_OFFSET    8
#define    RTL8370_QOS_7Q_PRIORITY_TO_QID_CRTL0_PRIORITY2_TO_QID_MASK    0x700
#define    RTL8370_QOS_7Q_PRIORITY_TO_QID_CRTL0_PRIORITY1_TO_QID_OFFSET    4
#define    RTL8370_QOS_7Q_PRIORITY_TO_QID_CRTL0_PRIORITY1_TO_QID_MASK    0x70
#define    RTL8370_QOS_7Q_PRIORITY_TO_QID_CRTL0_PRIORITY0_TO_QID_OFFSET    0
#define    RTL8370_QOS_7Q_PRIORITY_TO_QID_CRTL0_PRIORITY0_TO_QID_MASK    0x7

#define    RTL8370_REG_QOS_7Q_PRIORITY_TO_QID_CRTL1    0x0911
#define    RTL8370_QOS_7Q_PRIORITY_TO_QID_CRTL1_PRIORITY7_TO_QID_OFFSET    12
#define    RTL8370_QOS_7Q_PRIORITY_TO_QID_CRTL1_PRIORITY7_TO_QID_MASK    0x7000
#define    RTL8370_QOS_7Q_PRIORITY_TO_QID_CRTL1_PRIORITY6_TO_QID_OFFSET    8
#define    RTL8370_QOS_7Q_PRIORITY_TO_QID_CRTL1_PRIORITY6_TO_QID_MASK    0x700
#define    RTL8370_QOS_7Q_PRIORITY_TO_QID_CRTL1_PRIORITY5_TO_QID_OFFSET    4
#define    RTL8370_QOS_7Q_PRIORITY_TO_QID_CRTL1_PRIORITY5_TO_QID_MASK    0x70
#define    RTL8370_QOS_7Q_PRIORITY_TO_QID_CRTL1_PRIORITY4_TO_QID_OFFSET    0
#define    RTL8370_QOS_7Q_PRIORITY_TO_QID_CRTL1_PRIORITY4_TO_QID_MASK    0x7

#define    RTL8370_REG_QOS_8Q_PRIORITY_TO_QID_CRTL0    0x0912
#define    RTL8370_QOS_8Q_PRIORITY_TO_QID_CRTL0_PRIORITY3_TO_QID_OFFSET    12
#define    RTL8370_QOS_8Q_PRIORITY_TO_QID_CRTL0_PRIORITY3_TO_QID_MASK    0x7000
#define    RTL8370_QOS_8Q_PRIORITY_TO_QID_CRTL0_PRIORITY2_TO_QID_OFFSET    8
#define    RTL8370_QOS_8Q_PRIORITY_TO_QID_CRTL0_PRIORITY2_TO_QID_MASK    0x700
#define    RTL8370_QOS_8Q_PRIORITY_TO_QID_CRTL0_PRIORITY1_TO_QID_OFFSET    4
#define    RTL8370_QOS_8Q_PRIORITY_TO_QID_CRTL0_PRIORITY1_TO_QID_MASK    0x70
#define    RTL8370_QOS_8Q_PRIORITY_TO_QID_CRTL0_PRIORITY0_TO_QID_OFFSET    0
#define    RTL8370_QOS_8Q_PRIORITY_TO_QID_CRTL0_PRIORITY0_TO_QID_MASK    0x7

#define    RTL8370_REG_QOS_8Q_PRIORITY_TO_QID_CRTL1    0x0913
#define    RTL8370_QOS_8Q_PRIORITY_TO_QID_CRTL1_PRIORITY7_TO_QID_OFFSET    12
#define    RTL8370_QOS_8Q_PRIORITY_TO_QID_CRTL1_PRIORITY7_TO_QID_MASK    0x7000
#define    RTL8370_QOS_8Q_PRIORITY_TO_QID_CRTL1_PRIORITY6_TO_QID_OFFSET    8
#define    RTL8370_QOS_8Q_PRIORITY_TO_QID_CRTL1_PRIORITY6_TO_QID_MASK    0x700
#define    RTL8370_QOS_8Q_PRIORITY_TO_QID_CRTL1_PRIORITY5_TO_QID_OFFSET    4
#define    RTL8370_QOS_8Q_PRIORITY_TO_QID_CRTL1_PRIORITY5_TO_QID_MASK    0x70
#define    RTL8370_QOS_8Q_PRIORITY_TO_QID_CRTL1_PRIORITY4_TO_QID_OFFSET    0
#define    RTL8370_QOS_8Q_PRIORITY_TO_QID_CRTL1_PRIORITY4_TO_QID_MASK    0x7

#define    RTL8370_REG_MIRROR_PRIORITY    0x0914
#define    RTL8370_MIRROR_PRIORITY_OFFSET    0
#define    RTL8370_MIRROR_PRIORITY_MASK    0x7

#define    RTL8370_REG_HIGHPRI_INDICATOR    0x0915
#define    RTL8370_PORT15_INDICATOR_OFFSET    15
#define    RTL8370_PORT15_INDICATOR_MASK    0x8000
#define    RTL8370_PORT14_INDICATOR_OFFSET    14
#define    RTL8370_PORT14_INDICATOR_MASK    0x4000
#define    RTL8370_PORT13_INDICATOR_OFFSET    13
#define    RTL8370_PORT13_INDICATOR_MASK    0x2000
#define    RTL8370_PORT12_INDICATOR_OFFSET    12
#define    RTL8370_PORT12_INDICATOR_MASK    0x1000
#define    RTL8370_PORT11_INDICATOR_OFFSET    11
#define    RTL8370_PORT11_INDICATOR_MASK    0x800
#define    RTL8370_PORT10_INDICATOR_OFFSET    10
#define    RTL8370_PORT10_INDICATOR_MASK    0x400
#define    RTL8370_PORT9_INDICATOR_OFFSET    9
#define    RTL8370_PORT9_INDICATOR_MASK    0x200
#define    RTL8370_PORT8_INDICATOR_OFFSET    8
#define    RTL8370_PORT8_INDICATOR_MASK    0x100
#define    RTL8370_PORT7_INDICATOR_OFFSET    7
#define    RTL8370_PORT7_INDICATOR_MASK    0x80
#define    RTL8370_PORT6_INDICATOR_OFFSET    6
#define    RTL8370_PORT6_INDICATOR_MASK    0x40
#define    RTL8370_PORT5_INDICATOR_OFFSET    5
#define    RTL8370_PORT5_INDICATOR_MASK    0x20
#define    RTL8370_PORT4_INDICATOR_OFFSET    4
#define    RTL8370_PORT4_INDICATOR_MASK    0x10
#define    RTL8370_PORT3_INDICATOR_OFFSET    3
#define    RTL8370_PORT3_INDICATOR_MASK    0x8
#define    RTL8370_PORT2_INDICATOR_OFFSET    2
#define    RTL8370_PORT2_INDICATOR_MASK    0x4
#define    RTL8370_PORT1_INDICATOR_OFFSET    1
#define    RTL8370_PORT1_INDICATOR_MASK    0x2
#define    RTL8370_PORT0_INDICATOR_OFFSET    0
#define    RTL8370_PORT0_INDICATOR_MASK    0x1

#define    RTL8370_REG_HIGHPRI_CFG    0x0916
#define    RTL8370_HIGHPRI_CFG_OFFSET    0
#define    RTL8370_HIGHPRI_CFG_MASK    0xFF

#define    RTL8370_REG_PORT_DEBUG_INFO_CTRL0    0x0917
#define    RTL8370_PORT1_DEBUG_INFO_OFFSET    8
#define    RTL8370_PORT1_DEBUG_INFO_MASK    0xFF00
#define    RTL8370_PORT0_DEBUG_INFO_OFFSET    0
#define    RTL8370_PORT0_DEBUG_INFO_MASK    0xFF

#define    RTL8370_REG_PORT_DEBUG_INFO_CTRL1    0x0918
#define    RTL8370_PORT3_DEBUG_INFO_OFFSET    8
#define    RTL8370_PORT3_DEBUG_INFO_MASK    0xFF00
#define    RTL8370_PORT2_DEBUG_INFO_OFFSET    0
#define    RTL8370_PORT2_DEBUG_INFO_MASK    0xFF

#define    RTL8370_REG_PORT_DEBUG_INFO_CTRL2    0x0919
#define    RTL8370_PORT5_DEBUG_INFO_OFFSET    8
#define    RTL8370_PORT5_DEBUG_INFO_MASK    0xFF00
#define    RTL8370_PORT4_DEBUG_INFO_OFFSET    0
#define    RTL8370_PORT4_DEBUG_INFO_MASK    0xFF

#define    RTL8370_REG_PORT_DEBUG_INFO_CTRL3    0x091a
#define    RTL8370_PORT7_DEBUG_INFO_OFFSET    8
#define    RTL8370_PORT7_DEBUG_INFO_MASK    0xFF00
#define    RTL8370_PORT6_DEBUG_INFO_OFFSET    0
#define    RTL8370_PORT6_DEBUG_INFO_MASK    0xFF

#define    RTL8370_REG_PORT_DEBUG_INFO_CTRL4    0x091b
#define    RTL8370_PORT9_DEBUG_INFO_OFFSET    8
#define    RTL8370_PORT9_DEBUG_INFO_MASK    0xFF00
#define    RTL8370_PORT8_DEBUG_INFO_OFFSET    0
#define    RTL8370_PORT8_DEBUG_INFO_MASK    0xFF

#define    RTL8370_REG_PORT_DEBUG_INFO_CTRL5    0x091c
#define    RTL8370_PORT11_DEBUG_INFO_OFFSET    8
#define    RTL8370_PORT11_DEBUG_INFO_MASK    0xFF00
#define    RTL8370_PORT10_DEBUG_INFO_OFFSET    0
#define    RTL8370_PORT10_DEBUG_INFO_MASK    0xFF

#define    RTL8370_REG_PORT_DEBUG_INFO_CTRL6    0x091d
#define    RTL8370_PORT13_DEBUG_INFO_OFFSET    8
#define    RTL8370_PORT13_DEBUG_INFO_MASK    0xFF00
#define    RTL8370_PORT12_DEBUG_INFO_OFFSET    0
#define    RTL8370_PORT12_DEBUG_INFO_MASK    0xFF

#define    RTL8370_REG_PORT_DEBUG_INFO_CTRL7    0x091e
#define    RTL8370_PORT15_DEBUG_INFO_OFFSET    8
#define    RTL8370_PORT15_DEBUG_INFO_MASK    0xFF00
#define    RTL8370_PORT14_DEBUG_INFO_OFFSET    0
#define    RTL8370_PORT14_DEBUG_INFO_MASK    0xFF

#define    RTL8370_REG_FLOWCRTL_EGRESS_QUEUE_ENABLE_CTRL0    0x0930
#define    RTL8370_PORT1_QUEUE_MASK_OFFSET    8
#define    RTL8370_PORT1_QUEUE_MASK_MASK    0xFF00
#define    RTL8370_PORT0_QUEUE_MASK_OFFSET    0
#define    RTL8370_PORT0_QUEUE_MASK_MASK    0xFF

#define    RTL8370_REG_FLOWCRTL_EGRESS_QUEUE_ENABLE_CTRL1    0x0931
#define    RTL8370_PORT3_QUEUE_MASK_OFFSET    8
#define    RTL8370_PORT3_QUEUE_MASK_MASK    0xFF00
#define    RTL8370_PORT2_QUEUE_MASK_OFFSET    0
#define    RTL8370_PORT2_QUEUE_MASK_MASK    0xFF

#define    RTL8370_REG_FLOWCRTL_EGRESS_QUEUE_ENABLE_CTRL2    0x0932
#define    RTL8370_PORT5_QUEUE_MASK_OFFSET    8
#define    RTL8370_PORT5_QUEUE_MASK_MASK    0xFF00
#define    RTL8370_PORT4_QUEUE_MASK_OFFSET    0
#define    RTL8370_PORT4_QUEUE_MASK_MASK    0xFF

#define    RTL8370_REG_FLOWCRTL_EGRESS_QUEUE_ENABLE_CTRL3    0x0933
#define    RTL8370_PORT7_QUEUE_MASK_OFFSET    8
#define    RTL8370_PORT7_QUEUE_MASK_MASK    0xFF00
#define    RTL8370_PORT6_QUEUE_MASK_OFFSET    0
#define    RTL8370_PORT6_QUEUE_MASK_MASK    0xFF

#define    RTL8370_REG_FLOWCRTL_EGRESS_QUEUE_ENABLE_CTRL4    0x0934
#define    RTL8370_PORT9_QUEUE_MASK_OFFSET    8
#define    RTL8370_PORT9_QUEUE_MASK_MASK    0xFF00
#define    RTL8370_PORT8_QUEUE_MASK_OFFSET    0
#define    RTL8370_PORT8_QUEUE_MASK_MASK    0xFF

#define    RTL8370_REG_FLOWCRTL_EGRESS_QUEUE_ENABLE_CTRL5    0x0935
#define    RTL8370_PORT11_QUEUE_MASK_OFFSET    8
#define    RTL8370_PORT11_QUEUE_MASK_MASK    0xFF00
#define    RTL8370_PORT10_QUEUE_MASK_OFFSET    0
#define    RTL8370_PORT10_QUEUE_MASK_MASK    0xFF

#define    RTL8370_REG_FLOWCRTL_EGRESS_QUEUE_ENABLE_CTRL6    0x0936
#define    RTL8370_PORT13_QUEUE_MASK_OFFSET    8
#define    RTL8370_PORT13_QUEUE_MASK_MASK    0xFF00
#define    RTL8370_PORT12_QUEUE_MASK_OFFSET    0
#define    RTL8370_PORT12_QUEUE_MASK_MASK    0xFF

#define    RTL8370_REG_FLOWCRTL_EGRESS_QUEUE_ENABLE_CTRL7    0x0937
#define    RTL8370_PORT15_QUEUE_MASK_OFFSET    8
#define    RTL8370_PORT15_QUEUE_MASK_MASK    0xFF00
#define    RTL8370_PORT14_QUEUE_MASK_OFFSET    0
#define    RTL8370_PORT14_QUEUE_MASK_MASK    0xFF

#define    RTL8370_REG_FLOWCRTL_EGRESS_PORT_ENABLE    0x0938

#define    RTL8370_REG_EAV_CTRL    0x0939
#define    RTL8370_EAV_TRAP_CPU_OFFSET    1
#define    RTL8370_EAV_TRAP_CPU_MASK    0x2
#define    RTL8370_EAV_TRAP_8051_OFFSET    0
#define    RTL8370_EAV_TRAP_8051_MASK    0x1

/* (16'h0a00) l2_reg */

#define    RTL8370_REG_VLAN_MSTI0_CTRL0    0x0a00
#define    RTL8370_VLAN_MSTI0_CTRL0_PORT7_STATE_OFFSET    14
#define    RTL8370_VLAN_MSTI0_CTRL0_PORT7_STATE_MASK    0xC000
#define    RTL8370_VLAN_MSTI0_CTRL0_PORT6_STATE_OFFSET    12
#define    RTL8370_VLAN_MSTI0_CTRL0_PORT6_STATE_MASK    0x3000
#define    RTL8370_VLAN_MSTI0_CTRL0_PORT5_STATE_OFFSET    10
#define    RTL8370_VLAN_MSTI0_CTRL0_PORT5_STATE_MASK    0xC00
#define    RTL8370_VLAN_MSTI0_CTRL0_PORT4_STATE_OFFSET    8
#define    RTL8370_VLAN_MSTI0_CTRL0_PORT4_STATE_MASK    0x300
#define    RTL8370_VLAN_MSTI0_CTRL0_PORT3_STATE_OFFSET    6
#define    RTL8370_VLAN_MSTI0_CTRL0_PORT3_STATE_MASK    0xC0
#define    RTL8370_VLAN_MSTI0_CTRL0_PORT2_STATE_OFFSET    4
#define    RTL8370_VLAN_MSTI0_CTRL0_PORT2_STATE_MASK    0x30
#define    RTL8370_VLAN_MSTI0_CTRL0_PORT1_STATE_OFFSET    2
#define    RTL8370_VLAN_MSTI0_CTRL0_PORT1_STATE_MASK    0xC
#define    RTL8370_VLAN_MSTI0_CTRL0_PORT0_STATE_OFFSET    0
#define    RTL8370_VLAN_MSTI0_CTRL0_PORT0_STATE_MASK    0x3

#define    RTL8370_REG_VLAN_MSTI0_CTRL1    0x0a01
#define    RTL8370_VLAN_MSTI0_CTRL1_PORT15_STATE_OFFSET    14
#define    RTL8370_VLAN_MSTI0_CTRL1_PORT15_STATE_MASK    0xC000
#define    RTL8370_VLAN_MSTI0_CTRL1_PORT14_STATE_OFFSET    12
#define    RTL8370_VLAN_MSTI0_CTRL1_PORT14_STATE_MASK    0x3000
#define    RTL8370_VLAN_MSTI0_CTRL1_PORT13_STATE_OFFSET    10
#define    RTL8370_VLAN_MSTI0_CTRL1_PORT13_STATE_MASK    0xC00
#define    RTL8370_VLAN_MSTI0_CTRL1_PORT12_STATE_OFFSET    8
#define    RTL8370_VLAN_MSTI0_CTRL1_PORT12_STATE_MASK    0x300
#define    RTL8370_VLAN_MSTI0_CTRL1_PORT11_STATE_OFFSET    6
#define    RTL8370_VLAN_MSTI0_CTRL1_PORT11_STATE_MASK    0xC0
#define    RTL8370_VLAN_MSTI0_CTRL1_PORT10_STATE_OFFSET    4
#define    RTL8370_VLAN_MSTI0_CTRL1_PORT10_STATE_MASK    0x30
#define    RTL8370_VLAN_MSTI0_CTRL1_PORT9_STATE_OFFSET    2
#define    RTL8370_VLAN_MSTI0_CTRL1_PORT9_STATE_MASK    0xC
#define    RTL8370_VLAN_MSTI0_CTRL1_PORT8_STATE_OFFSET    0
#define    RTL8370_VLAN_MSTI0_CTRL1_PORT8_STATE_MASK    0x3

#define    RTL8370_REG_VLAN_MSTI1_CTRL0    0x0a02
#define    RTL8370_VLAN_MSTI1_CTRL0_PORT7_STATE_OFFSET    14
#define    RTL8370_VLAN_MSTI1_CTRL0_PORT7_STATE_MASK    0xC000
#define    RTL8370_VLAN_MSTI1_CTRL0_PORT6_STATE_OFFSET    12
#define    RTL8370_VLAN_MSTI1_CTRL0_PORT6_STATE_MASK    0x3000
#define    RTL8370_VLAN_MSTI1_CTRL0_PORT5_STATE_OFFSET    10
#define    RTL8370_VLAN_MSTI1_CTRL0_PORT5_STATE_MASK    0xC00
#define    RTL8370_VLAN_MSTI1_CTRL0_PORT4_STATE_OFFSET    8
#define    RTL8370_VLAN_MSTI1_CTRL0_PORT4_STATE_MASK    0x300
#define    RTL8370_VLAN_MSTI1_CTRL0_PORT3_STATE_OFFSET    6
#define    RTL8370_VLAN_MSTI1_CTRL0_PORT3_STATE_MASK    0xC0
#define    RTL8370_VLAN_MSTI1_CTRL0_PORT2_STATE_OFFSET    4
#define    RTL8370_VLAN_MSTI1_CTRL0_PORT2_STATE_MASK    0x30
#define    RTL8370_VLAN_MSTI1_CTRL0_PORT1_STATE_OFFSET    2
#define    RTL8370_VLAN_MSTI1_CTRL0_PORT1_STATE_MASK    0xC
#define    RTL8370_VLAN_MSTI1_CTRL0_PORT0_STATE_OFFSET    0
#define    RTL8370_VLAN_MSTI1_CTRL0_PORT0_STATE_MASK    0x3

#define    RTL8370_REG_VLAN_MSTI1_CTRL1    0x0a03
#define    RTL8370_VLAN_MSTI1_CTRL1_PORT15_STATE_OFFSET    14
#define    RTL8370_VLAN_MSTI1_CTRL1_PORT15_STATE_MASK    0xC000
#define    RTL8370_VLAN_MSTI1_CTRL1_PORT14_STATE_OFFSET    12
#define    RTL8370_VLAN_MSTI1_CTRL1_PORT14_STATE_MASK    0x3000
#define    RTL8370_VLAN_MSTI1_CTRL1_PORT13_STATE_OFFSET    10
#define    RTL8370_VLAN_MSTI1_CTRL1_PORT13_STATE_MASK    0xC00
#define    RTL8370_VLAN_MSTI1_CTRL1_PORT12_STATE_OFFSET    8
#define    RTL8370_VLAN_MSTI1_CTRL1_PORT12_STATE_MASK    0x300
#define    RTL8370_VLAN_MSTI1_CTRL1_PORT11_STATE_OFFSET    6
#define    RTL8370_VLAN_MSTI1_CTRL1_PORT11_STATE_MASK    0xC0
#define    RTL8370_VLAN_MSTI1_CTRL1_PORT10_STATE_OFFSET    4
#define    RTL8370_VLAN_MSTI1_CTRL1_PORT10_STATE_MASK    0x30
#define    RTL8370_VLAN_MSTI1_CTRL1_PORT9_STATE_OFFSET    2
#define    RTL8370_VLAN_MSTI1_CTRL1_PORT9_STATE_MASK    0xC
#define    RTL8370_VLAN_MSTI1_CTRL1_PORT8_STATE_OFFSET    0
#define    RTL8370_VLAN_MSTI1_CTRL1_PORT8_STATE_MASK    0x3

#define    RTL8370_REG_VLAN_MSTI2_CTRL0    0x0a04
#define    RTL8370_VLAN_MSTI2_CTRL0_PORT7_STATE_OFFSET    14
#define    RTL8370_VLAN_MSTI2_CTRL0_PORT7_STATE_MASK    0xC000
#define    RTL8370_VLAN_MSTI2_CTRL0_PORT6_STATE_OFFSET    12
#define    RTL8370_VLAN_MSTI2_CTRL0_PORT6_STATE_MASK    0x3000
#define    RTL8370_VLAN_MSTI2_CTRL0_PORT5_STATE_OFFSET    10
#define    RTL8370_VLAN_MSTI2_CTRL0_PORT5_STATE_MASK    0xC00
#define    RTL8370_VLAN_MSTI2_CTRL0_PORT4_STATE_OFFSET    8
#define    RTL8370_VLAN_MSTI2_CTRL0_PORT4_STATE_MASK    0x300
#define    RTL8370_VLAN_MSTI2_CTRL0_PORT3_STATE_OFFSET    6
#define    RTL8370_VLAN_MSTI2_CTRL0_PORT3_STATE_MASK    0xC0
#define    RTL8370_VLAN_MSTI2_CTRL0_PORT2_STATE_OFFSET    4
#define    RTL8370_VLAN_MSTI2_CTRL0_PORT2_STATE_MASK    0x30
#define    RTL8370_VLAN_MSTI2_CTRL0_PORT1_STATE_OFFSET    2
#define    RTL8370_VLAN_MSTI2_CTRL0_PORT1_STATE_MASK    0xC
#define    RTL8370_VLAN_MSTI2_CTRL0_PORT0_STATE_OFFSET    0
#define    RTL8370_VLAN_MSTI2_CTRL0_PORT0_STATE_MASK    0x3

#define    RTL8370_REG_VLAN_MSTI2_CTRL1    0x0a05
#define    RTL8370_VLAN_MSTI2_CTRL1_PORT15_STATE_OFFSET    14
#define    RTL8370_VLAN_MSTI2_CTRL1_PORT15_STATE_MASK    0xC000
#define    RTL8370_VLAN_MSTI2_CTRL1_PORT14_STATE_OFFSET    12
#define    RTL8370_VLAN_MSTI2_CTRL1_PORT14_STATE_MASK    0x3000
#define    RTL8370_VLAN_MSTI2_CTRL1_PORT13_STATE_OFFSET    10
#define    RTL8370_VLAN_MSTI2_CTRL1_PORT13_STATE_MASK    0xC00
#define    RTL8370_VLAN_MSTI2_CTRL1_PORT12_STATE_OFFSET    8
#define    RTL8370_VLAN_MSTI2_CTRL1_PORT12_STATE_MASK    0x300
#define    RTL8370_VLAN_MSTI2_CTRL1_PORT11_STATE_OFFSET    6
#define    RTL8370_VLAN_MSTI2_CTRL1_PORT11_STATE_MASK    0xC0
#define    RTL8370_VLAN_MSTI2_CTRL1_PORT10_STATE_OFFSET    4
#define    RTL8370_VLAN_MSTI2_CTRL1_PORT10_STATE_MASK    0x30
#define    RTL8370_VLAN_MSTI2_CTRL1_PORT9_STATE_OFFSET    2
#define    RTL8370_VLAN_MSTI2_CTRL1_PORT9_STATE_MASK    0xC
#define    RTL8370_VLAN_MSTI2_CTRL1_PORT8_STATE_OFFSET    0
#define    RTL8370_VLAN_MSTI2_CTRL1_PORT8_STATE_MASK    0x3

#define    RTL8370_REG_VLAN_MSTI3_CTRL0    0x0a06
#define    RTL8370_VLAN_MSTI3_CTRL0_PORT7_STATE_OFFSET    14
#define    RTL8370_VLAN_MSTI3_CTRL0_PORT7_STATE_MASK    0xC000
#define    RTL8370_VLAN_MSTI3_CTRL0_PORT6_STATE_OFFSET    12
#define    RTL8370_VLAN_MSTI3_CTRL0_PORT6_STATE_MASK    0x3000
#define    RTL8370_VLAN_MSTI3_CTRL0_PORT5_STATE_OFFSET    10
#define    RTL8370_VLAN_MSTI3_CTRL0_PORT5_STATE_MASK    0xC00
#define    RTL8370_VLAN_MSTI3_CTRL0_PORT4_STATE_OFFSET    8
#define    RTL8370_VLAN_MSTI3_CTRL0_PORT4_STATE_MASK    0x300
#define    RTL8370_VLAN_MSTI3_CTRL0_PORT3_STATE_OFFSET    6
#define    RTL8370_VLAN_MSTI3_CTRL0_PORT3_STATE_MASK    0xC0
#define    RTL8370_VLAN_MSTI3_CTRL0_PORT2_STATE_OFFSET    4
#define    RTL8370_VLAN_MSTI3_CTRL0_PORT2_STATE_MASK    0x30
#define    RTL8370_VLAN_MSTI3_CTRL0_PORT1_STATE_OFFSET    2
#define    RTL8370_VLAN_MSTI3_CTRL0_PORT1_STATE_MASK    0xC
#define    RTL8370_VLAN_MSTI3_CTRL0_PORT0_STATE_OFFSET    0
#define    RTL8370_VLAN_MSTI3_CTRL0_PORT0_STATE_MASK    0x3

#define    RTL8370_REG_VLAN_MSTI3_CTRL1    0x0a07
#define    RTL8370_VLAN_MSTI3_CTRL1_PORT15_STATE_OFFSET    14
#define    RTL8370_VLAN_MSTI3_CTRL1_PORT15_STATE_MASK    0xC000
#define    RTL8370_VLAN_MSTI3_CTRL1_PORT14_STATE_OFFSET    12
#define    RTL8370_VLAN_MSTI3_CTRL1_PORT14_STATE_MASK    0x3000
#define    RTL8370_VLAN_MSTI3_CTRL1_PORT13_STATE_OFFSET    10
#define    RTL8370_VLAN_MSTI3_CTRL1_PORT13_STATE_MASK    0xC00
#define    RTL8370_VLAN_MSTI3_CTRL1_PORT12_STATE_OFFSET    8
#define    RTL8370_VLAN_MSTI3_CTRL1_PORT12_STATE_MASK    0x300
#define    RTL8370_VLAN_MSTI3_CTRL1_PORT11_STATE_OFFSET    6
#define    RTL8370_VLAN_MSTI3_CTRL1_PORT11_STATE_MASK    0xC0
#define    RTL8370_VLAN_MSTI3_CTRL1_PORT10_STATE_OFFSET    4
#define    RTL8370_VLAN_MSTI3_CTRL1_PORT10_STATE_MASK    0x30
#define    RTL8370_VLAN_MSTI3_CTRL1_PORT9_STATE_OFFSET    2
#define    RTL8370_VLAN_MSTI3_CTRL1_PORT9_STATE_MASK    0xC
#define    RTL8370_VLAN_MSTI3_CTRL1_PORT8_STATE_OFFSET    0
#define    RTL8370_VLAN_MSTI3_CTRL1_PORT8_STATE_MASK    0x3

#define    RTL8370_REG_VLAN_MSTI4_CTRL0    0x0a08
#define    RTL8370_VLAN_MSTI4_CTRL0_PORT7_STATE_OFFSET    14
#define    RTL8370_VLAN_MSTI4_CTRL0_PORT7_STATE_MASK    0xC000
#define    RTL8370_VLAN_MSTI4_CTRL0_PORT6_STATE_OFFSET    12
#define    RTL8370_VLAN_MSTI4_CTRL0_PORT6_STATE_MASK    0x3000
#define    RTL8370_VLAN_MSTI4_CTRL0_PORT5_STATE_OFFSET    10
#define    RTL8370_VLAN_MSTI4_CTRL0_PORT5_STATE_MASK    0xC00
#define    RTL8370_VLAN_MSTI4_CTRL0_PORT4_STATE_OFFSET    8
#define    RTL8370_VLAN_MSTI4_CTRL0_PORT4_STATE_MASK    0x300
#define    RTL8370_VLAN_MSTI4_CTRL0_PORT3_STATE_OFFSET    6
#define    RTL8370_VLAN_MSTI4_CTRL0_PORT3_STATE_MASK    0xC0
#define    RTL8370_VLAN_MSTI4_CTRL0_PORT2_STATE_OFFSET    4
#define    RTL8370_VLAN_MSTI4_CTRL0_PORT2_STATE_MASK    0x30
#define    RTL8370_VLAN_MSTI4_CTRL0_PORT1_STATE_OFFSET    2
#define    RTL8370_VLAN_MSTI4_CTRL0_PORT1_STATE_MASK    0xC
#define    RTL8370_VLAN_MSTI4_CTRL0_PORT0_STATE_OFFSET    0
#define    RTL8370_VLAN_MSTI4_CTRL0_PORT0_STATE_MASK    0x3

#define    RTL8370_REG_VLAN_MSTI4_CTRL1    0x0a09
#define    RTL8370_VLAN_MSTI4_CTRL1_PORT15_STATE_OFFSET    14
#define    RTL8370_VLAN_MSTI4_CTRL1_PORT15_STATE_MASK    0xC000
#define    RTL8370_VLAN_MSTI4_CTRL1_PORT14_STATE_OFFSET    12
#define    RTL8370_VLAN_MSTI4_CTRL1_PORT14_STATE_MASK    0x3000
#define    RTL8370_VLAN_MSTI4_CTRL1_PORT13_STATE_OFFSET    10
#define    RTL8370_VLAN_MSTI4_CTRL1_PORT13_STATE_MASK    0xC00
#define    RTL8370_VLAN_MSTI4_CTRL1_PORT12_STATE_OFFSET    8
#define    RTL8370_VLAN_MSTI4_CTRL1_PORT12_STATE_MASK    0x300
#define    RTL8370_VLAN_MSTI4_CTRL1_PORT11_STATE_OFFSET    6
#define    RTL8370_VLAN_MSTI4_CTRL1_PORT11_STATE_MASK    0xC0
#define    RTL8370_VLAN_MSTI4_CTRL1_PORT10_STATE_OFFSET    4
#define    RTL8370_VLAN_MSTI4_CTRL1_PORT10_STATE_MASK    0x30
#define    RTL8370_VLAN_MSTI4_CTRL1_PORT9_STATE_OFFSET    2
#define    RTL8370_VLAN_MSTI4_CTRL1_PORT9_STATE_MASK    0xC
#define    RTL8370_VLAN_MSTI4_CTRL1_PORT8_STATE_OFFSET    0
#define    RTL8370_VLAN_MSTI4_CTRL1_PORT8_STATE_MASK    0x3

#define    RTL8370_REG_VLAN_MSTI5_CTRL0    0x0a0a
#define    RTL8370_VLAN_MSTI5_CTRL0_PORT7_STATE_OFFSET    14
#define    RTL8370_VLAN_MSTI5_CTRL0_PORT7_STATE_MASK    0xC000
#define    RTL8370_VLAN_MSTI5_CTRL0_PORT6_STATE_OFFSET    12
#define    RTL8370_VLAN_MSTI5_CTRL0_PORT6_STATE_MASK    0x3000
#define    RTL8370_VLAN_MSTI5_CTRL0_PORT5_STATE_OFFSET    10
#define    RTL8370_VLAN_MSTI5_CTRL0_PORT5_STATE_MASK    0xC00
#define    RTL8370_VLAN_MSTI5_CTRL0_PORT4_STATE_OFFSET    8
#define    RTL8370_VLAN_MSTI5_CTRL0_PORT4_STATE_MASK    0x300
#define    RTL8370_VLAN_MSTI5_CTRL0_PORT3_STATE_OFFSET    6
#define    RTL8370_VLAN_MSTI5_CTRL0_PORT3_STATE_MASK    0xC0
#define    RTL8370_VLAN_MSTI5_CTRL0_PORT2_STATE_OFFSET    4
#define    RTL8370_VLAN_MSTI5_CTRL0_PORT2_STATE_MASK    0x30
#define    RTL8370_VLAN_MSTI5_CTRL0_PORT1_STATE_OFFSET    2
#define    RTL8370_VLAN_MSTI5_CTRL0_PORT1_STATE_MASK    0xC
#define    RTL8370_VLAN_MSTI5_CTRL0_PORT0_STATE_OFFSET    0
#define    RTL8370_VLAN_MSTI5_CTRL0_PORT0_STATE_MASK    0x3

#define    RTL8370_REG_VLAN_MSTI5_CTRL1    0x0a0b
#define    RTL8370_VLAN_MSTI5_CTRL1_PORT15_STATE_OFFSET    14
#define    RTL8370_VLAN_MSTI5_CTRL1_PORT15_STATE_MASK    0xC000
#define    RTL8370_VLAN_MSTI5_CTRL1_PORT14_STATE_OFFSET    12
#define    RTL8370_VLAN_MSTI5_CTRL1_PORT14_STATE_MASK    0x3000
#define    RTL8370_VLAN_MSTI5_CTRL1_PORT13_STATE_OFFSET    10
#define    RTL8370_VLAN_MSTI5_CTRL1_PORT13_STATE_MASK    0xC00
#define    RTL8370_VLAN_MSTI5_CTRL1_PORT12_STATE_OFFSET    8
#define    RTL8370_VLAN_MSTI5_CTRL1_PORT12_STATE_MASK    0x300
#define    RTL8370_VLAN_MSTI5_CTRL1_PORT11_STATE_OFFSET    6
#define    RTL8370_VLAN_MSTI5_CTRL1_PORT11_STATE_MASK    0xC0
#define    RTL8370_VLAN_MSTI5_CTRL1_PORT10_STATE_OFFSET    4
#define    RTL8370_VLAN_MSTI5_CTRL1_PORT10_STATE_MASK    0x30
#define    RTL8370_VLAN_MSTI5_CTRL1_PORT9_STATE_OFFSET    2
#define    RTL8370_VLAN_MSTI5_CTRL1_PORT9_STATE_MASK    0xC
#define    RTL8370_VLAN_MSTI5_CTRL1_PORT8_STATE_OFFSET    0
#define    RTL8370_VLAN_MSTI5_CTRL1_PORT8_STATE_MASK    0x3

#define    RTL8370_REG_VLAN_MSTI6_CTRL0    0x0a0c
#define    RTL8370_VLAN_MSTI6_CTRL0_PORT7_STATE_OFFSET    14
#define    RTL8370_VLAN_MSTI6_CTRL0_PORT7_STATE_MASK    0xC000
#define    RTL8370_VLAN_MSTI6_CTRL0_PORT6_STATE_OFFSET    12
#define    RTL8370_VLAN_MSTI6_CTRL0_PORT6_STATE_MASK    0x3000
#define    RTL8370_VLAN_MSTI6_CTRL0_PORT5_STATE_OFFSET    10
#define    RTL8370_VLAN_MSTI6_CTRL0_PORT5_STATE_MASK    0xC00
#define    RTL8370_VLAN_MSTI6_CTRL0_PORT4_STATE_OFFSET    8
#define    RTL8370_VLAN_MSTI6_CTRL0_PORT4_STATE_MASK    0x300
#define    RTL8370_VLAN_MSTI6_CTRL0_PORT3_STATE_OFFSET    6
#define    RTL8370_VLAN_MSTI6_CTRL0_PORT3_STATE_MASK    0xC0
#define    RTL8370_VLAN_MSTI6_CTRL0_PORT2_STATE_OFFSET    4
#define    RTL8370_VLAN_MSTI6_CTRL0_PORT2_STATE_MASK    0x30
#define    RTL8370_VLAN_MSTI6_CTRL0_PORT1_STATE_OFFSET    2
#define    RTL8370_VLAN_MSTI6_CTRL0_PORT1_STATE_MASK    0xC
#define    RTL8370_VLAN_MSTI6_CTRL0_PORT0_STATE_OFFSET    0
#define    RTL8370_VLAN_MSTI6_CTRL0_PORT0_STATE_MASK    0x3

#define    RTL8370_REG_VLAN_MSTI6_CTRL1    0x0a0d
#define    RTL8370_VLAN_MSTI6_CTRL1_PORT15_STATE_OFFSET    14
#define    RTL8370_VLAN_MSTI6_CTRL1_PORT15_STATE_MASK    0xC000
#define    RTL8370_VLAN_MSTI6_CTRL1_PORT14_STATE_OFFSET    12
#define    RTL8370_VLAN_MSTI6_CTRL1_PORT14_STATE_MASK    0x3000
#define    RTL8370_VLAN_MSTI6_CTRL1_PORT13_STATE_OFFSET    10
#define    RTL8370_VLAN_MSTI6_CTRL1_PORT13_STATE_MASK    0xC00
#define    RTL8370_VLAN_MSTI6_CTRL1_PORT12_STATE_OFFSET    8
#define    RTL8370_VLAN_MSTI6_CTRL1_PORT12_STATE_MASK    0x300
#define    RTL8370_VLAN_MSTI6_CTRL1_PORT11_STATE_OFFSET    6
#define    RTL8370_VLAN_MSTI6_CTRL1_PORT11_STATE_MASK    0xC0
#define    RTL8370_VLAN_MSTI6_CTRL1_PORT10_STATE_OFFSET    4
#define    RTL8370_VLAN_MSTI6_CTRL1_PORT10_STATE_MASK    0x30
#define    RTL8370_VLAN_MSTI6_CTRL1_PORT9_STATE_OFFSET    2
#define    RTL8370_VLAN_MSTI6_CTRL1_PORT9_STATE_MASK    0xC
#define    RTL8370_VLAN_MSTI6_CTRL1_PORT8_STATE_OFFSET    0
#define    RTL8370_VLAN_MSTI6_CTRL1_PORT8_STATE_MASK    0x3

#define    RTL8370_REG_VLAN_MSTI7_CTRL0    0x0a0e
#define    RTL8370_VLAN_MSTI7_CTRL0_PORT7_STATE_OFFSET    14
#define    RTL8370_VLAN_MSTI7_CTRL0_PORT7_STATE_MASK    0xC000
#define    RTL8370_VLAN_MSTI7_CTRL0_PORT6_STATE_OFFSET    12
#define    RTL8370_VLAN_MSTI7_CTRL0_PORT6_STATE_MASK    0x3000
#define    RTL8370_VLAN_MSTI7_CTRL0_PORT5_STATE_OFFSET    10
#define    RTL8370_VLAN_MSTI7_CTRL0_PORT5_STATE_MASK    0xC00
#define    RTL8370_VLAN_MSTI7_CTRL0_PORT4_STATE_OFFSET    8
#define    RTL8370_VLAN_MSTI7_CTRL0_PORT4_STATE_MASK    0x300
#define    RTL8370_VLAN_MSTI7_CTRL0_PORT3_STATE_OFFSET    6
#define    RTL8370_VLAN_MSTI7_CTRL0_PORT3_STATE_MASK    0xC0
#define    RTL8370_VLAN_MSTI7_CTRL0_PORT2_STATE_OFFSET    4
#define    RTL8370_VLAN_MSTI7_CTRL0_PORT2_STATE_MASK    0x30
#define    RTL8370_VLAN_MSTI7_CTRL0_PORT1_STATE_OFFSET    2
#define    RTL8370_VLAN_MSTI7_CTRL0_PORT1_STATE_MASK    0xC
#define    RTL8370_VLAN_MSTI7_CTRL0_PORT0_STATE_OFFSET    0
#define    RTL8370_VLAN_MSTI7_CTRL0_PORT0_STATE_MASK    0x3

#define    RTL8370_REG_VLAN_MSTI7_CTRL1    0x0a0f
#define    RTL8370_VLAN_MSTI7_CTRL1_PORT15_STATE_OFFSET    14
#define    RTL8370_VLAN_MSTI7_CTRL1_PORT15_STATE_MASK    0xC000
#define    RTL8370_VLAN_MSTI7_CTRL1_PORT14_STATE_OFFSET    12
#define    RTL8370_VLAN_MSTI7_CTRL1_PORT14_STATE_MASK    0x3000
#define    RTL8370_VLAN_MSTI7_CTRL1_PORT13_STATE_OFFSET    10
#define    RTL8370_VLAN_MSTI7_CTRL1_PORT13_STATE_MASK    0xC00
#define    RTL8370_VLAN_MSTI7_CTRL1_PORT12_STATE_OFFSET    8
#define    RTL8370_VLAN_MSTI7_CTRL1_PORT12_STATE_MASK    0x300
#define    RTL8370_VLAN_MSTI7_CTRL1_PORT11_STATE_OFFSET    6
#define    RTL8370_VLAN_MSTI7_CTRL1_PORT11_STATE_MASK    0xC0
#define    RTL8370_VLAN_MSTI7_CTRL1_PORT10_STATE_OFFSET    4
#define    RTL8370_VLAN_MSTI7_CTRL1_PORT10_STATE_MASK    0x30
#define    RTL8370_VLAN_MSTI7_CTRL1_PORT9_STATE_OFFSET    2
#define    RTL8370_VLAN_MSTI7_CTRL1_PORT9_STATE_MASK    0xC
#define    RTL8370_VLAN_MSTI7_CTRL1_PORT8_STATE_OFFSET    0
#define    RTL8370_VLAN_MSTI7_CTRL1_PORT8_STATE_MASK    0x3

#define    RTL8370_REG_VLAN_MSTI8_CTRL0    0x0a10
#define    RTL8370_VLAN_MSTI8_CTRL0_PORT7_STATE_OFFSET    14
#define    RTL8370_VLAN_MSTI8_CTRL0_PORT7_STATE_MASK    0xC000
#define    RTL8370_VLAN_MSTI8_CTRL0_PORT6_STATE_OFFSET    12
#define    RTL8370_VLAN_MSTI8_CTRL0_PORT6_STATE_MASK    0x3000
#define    RTL8370_VLAN_MSTI8_CTRL0_PORT5_STATE_OFFSET    10
#define    RTL8370_VLAN_MSTI8_CTRL0_PORT5_STATE_MASK    0xC00
#define    RTL8370_VLAN_MSTI8_CTRL0_PORT4_STATE_OFFSET    8
#define    RTL8370_VLAN_MSTI8_CTRL0_PORT4_STATE_MASK    0x300
#define    RTL8370_VLAN_MSTI8_CTRL0_PORT3_STATE_OFFSET    6
#define    RTL8370_VLAN_MSTI8_CTRL0_PORT3_STATE_MASK    0xC0
#define    RTL8370_VLAN_MSTI8_CTRL0_PORT2_STATE_OFFSET    4
#define    RTL8370_VLAN_MSTI8_CTRL0_PORT2_STATE_MASK    0x30
#define    RTL8370_VLAN_MSTI8_CTRL0_PORT1_STATE_OFFSET    2
#define    RTL8370_VLAN_MSTI8_CTRL0_PORT1_STATE_MASK    0xC
#define    RTL8370_VLAN_MSTI8_CTRL0_PORT0_STATE_OFFSET    0
#define    RTL8370_VLAN_MSTI8_CTRL0_PORT0_STATE_MASK    0x3

#define    RTL8370_REG_VLAN_MSTI8_CTRL1    0x0a11
#define    RTL8370_VLAN_MSTI8_CTRL1_PORT15_STATE_OFFSET    14
#define    RTL8370_VLAN_MSTI8_CTRL1_PORT15_STATE_MASK    0xC000
#define    RTL8370_VLAN_MSTI8_CTRL1_PORT14_STATE_OFFSET    12
#define    RTL8370_VLAN_MSTI8_CTRL1_PORT14_STATE_MASK    0x3000
#define    RTL8370_VLAN_MSTI8_CTRL1_PORT13_STATE_OFFSET    10
#define    RTL8370_VLAN_MSTI8_CTRL1_PORT13_STATE_MASK    0xC00
#define    RTL8370_VLAN_MSTI8_CTRL1_PORT12_STATE_OFFSET    8
#define    RTL8370_VLAN_MSTI8_CTRL1_PORT12_STATE_MASK    0x300
#define    RTL8370_VLAN_MSTI8_CTRL1_PORT11_STATE_OFFSET    6
#define    RTL8370_VLAN_MSTI8_CTRL1_PORT11_STATE_MASK    0xC0
#define    RTL8370_VLAN_MSTI8_CTRL1_PORT10_STATE_OFFSET    4
#define    RTL8370_VLAN_MSTI8_CTRL1_PORT10_STATE_MASK    0x30
#define    RTL8370_VLAN_MSTI8_CTRL1_PORT9_STATE_OFFSET    2
#define    RTL8370_VLAN_MSTI8_CTRL1_PORT9_STATE_MASK    0xC
#define    RTL8370_VLAN_MSTI8_CTRL1_PORT8_STATE_OFFSET    0
#define    RTL8370_VLAN_MSTI8_CTRL1_PORT8_STATE_MASK    0x3

#define    RTL8370_REG_VLAN_MSTI9_CTRL0    0x0a12
#define    RTL8370_VLAN_MSTI9_CTRL0_PORT7_STATE_OFFSET    14
#define    RTL8370_VLAN_MSTI9_CTRL0_PORT7_STATE_MASK    0xC000
#define    RTL8370_VLAN_MSTI9_CTRL0_PORT6_STATE_OFFSET    12
#define    RTL8370_VLAN_MSTI9_CTRL0_PORT6_STATE_MASK    0x3000
#define    RTL8370_VLAN_MSTI9_CTRL0_PORT5_STATE_OFFSET    10
#define    RTL8370_VLAN_MSTI9_CTRL0_PORT5_STATE_MASK    0xC00
#define    RTL8370_VLAN_MSTI9_CTRL0_PORT4_STATE_OFFSET    8
#define    RTL8370_VLAN_MSTI9_CTRL0_PORT4_STATE_MASK    0x300
#define    RTL8370_VLAN_MSTI9_CTRL0_PORT3_STATE_OFFSET    6
#define    RTL8370_VLAN_MSTI9_CTRL0_PORT3_STATE_MASK    0xC0
#define    RTL8370_VLAN_MSTI9_CTRL0_PORT2_STATE_OFFSET    4
#define    RTL8370_VLAN_MSTI9_CTRL0_PORT2_STATE_MASK    0x30
#define    RTL8370_VLAN_MSTI9_CTRL0_PORT1_STATE_OFFSET    2
#define    RTL8370_VLAN_MSTI9_CTRL0_PORT1_STATE_MASK    0xC
#define    RTL8370_VLAN_MSTI9_CTRL0_PORT0_STATE_OFFSET    0
#define    RTL8370_VLAN_MSTI9_CTRL0_PORT0_STATE_MASK    0x3

#define    RTL8370_REG_VLAN_MSTI9_CTRL1    0x0a13
#define    RTL8370_VLAN_MSTI9_CTRL1_PORT15_STATE_OFFSET    14
#define    RTL8370_VLAN_MSTI9_CTRL1_PORT15_STATE_MASK    0xC000
#define    RTL8370_VLAN_MSTI9_CTRL1_PORT14_STATE_OFFSET    12
#define    RTL8370_VLAN_MSTI9_CTRL1_PORT14_STATE_MASK    0x3000
#define    RTL8370_VLAN_MSTI9_CTRL1_PORT13_STATE_OFFSET    10
#define    RTL8370_VLAN_MSTI9_CTRL1_PORT13_STATE_MASK    0xC00
#define    RTL8370_VLAN_MSTI9_CTRL1_PORT12_STATE_OFFSET    8
#define    RTL8370_VLAN_MSTI9_CTRL1_PORT12_STATE_MASK    0x300
#define    RTL8370_VLAN_MSTI9_CTRL1_PORT11_STATE_OFFSET    6
#define    RTL8370_VLAN_MSTI9_CTRL1_PORT11_STATE_MASK    0xC0
#define    RTL8370_VLAN_MSTI9_CTRL1_PORT10_STATE_OFFSET    4
#define    RTL8370_VLAN_MSTI9_CTRL1_PORT10_STATE_MASK    0x30
#define    RTL8370_VLAN_MSTI9_CTRL1_PORT9_STATE_OFFSET    2
#define    RTL8370_VLAN_MSTI9_CTRL1_PORT9_STATE_MASK    0xC
#define    RTL8370_VLAN_MSTI9_CTRL1_PORT8_STATE_OFFSET    0
#define    RTL8370_VLAN_MSTI9_CTRL1_PORT8_STATE_MASK    0x3

#define    RTL8370_REG_VLAN_MSTI10_CTRL0    0x0a14
#define    RTL8370_VLAN_MSTI10_CTRL0_PORT7_STATE_OFFSET    14
#define    RTL8370_VLAN_MSTI10_CTRL0_PORT7_STATE_MASK    0xC000
#define    RTL8370_VLAN_MSTI10_CTRL0_PORT6_STATE_OFFSET    12
#define    RTL8370_VLAN_MSTI10_CTRL0_PORT6_STATE_MASK    0x3000
#define    RTL8370_VLAN_MSTI10_CTRL0_PORT5_STATE_OFFSET    10
#define    RTL8370_VLAN_MSTI10_CTRL0_PORT5_STATE_MASK    0xC00
#define    RTL8370_VLAN_MSTI10_CTRL0_PORT4_STATE_OFFSET    8
#define    RTL8370_VLAN_MSTI10_CTRL0_PORT4_STATE_MASK    0x300
#define    RTL8370_VLAN_MSTI10_CTRL0_PORT3_STATE_OFFSET    6
#define    RTL8370_VLAN_MSTI10_CTRL0_PORT3_STATE_MASK    0xC0
#define    RTL8370_VLAN_MSTI10_CTRL0_PORT2_STATE_OFFSET    4
#define    RTL8370_VLAN_MSTI10_CTRL0_PORT2_STATE_MASK    0x30
#define    RTL8370_VLAN_MSTI10_CTRL0_PORT1_STATE_OFFSET    2
#define    RTL8370_VLAN_MSTI10_CTRL0_PORT1_STATE_MASK    0xC
#define    RTL8370_VLAN_MSTI10_CTRL0_PORT0_STATE_OFFSET    0
#define    RTL8370_VLAN_MSTI10_CTRL0_PORT0_STATE_MASK    0x3

#define    RTL8370_REG_VLAN_MSTI10_CTRL1    0x0a15
#define    RTL8370_VLAN_MSTI10_CTRL1_PORT15_STATE_OFFSET    14
#define    RTL8370_VLAN_MSTI10_CTRL1_PORT15_STATE_MASK    0xC000
#define    RTL8370_VLAN_MSTI10_CTRL1_PORT14_STATE_OFFSET    12
#define    RTL8370_VLAN_MSTI10_CTRL1_PORT14_STATE_MASK    0x3000
#define    RTL8370_VLAN_MSTI10_CTRL1_PORT13_STATE_OFFSET    10
#define    RTL8370_VLAN_MSTI10_CTRL1_PORT13_STATE_MASK    0xC00
#define    RTL8370_VLAN_MSTI10_CTRL1_PORT12_STATE_OFFSET    8
#define    RTL8370_VLAN_MSTI10_CTRL1_PORT12_STATE_MASK    0x300
#define    RTL8370_VLAN_MSTI10_CTRL1_PORT11_STATE_OFFSET    6
#define    RTL8370_VLAN_MSTI10_CTRL1_PORT11_STATE_MASK    0xC0
#define    RTL8370_VLAN_MSTI10_CTRL1_PORT10_STATE_OFFSET    4
#define    RTL8370_VLAN_MSTI10_CTRL1_PORT10_STATE_MASK    0x30
#define    RTL8370_VLAN_MSTI10_CTRL1_PORT9_STATE_OFFSET    2
#define    RTL8370_VLAN_MSTI10_CTRL1_PORT9_STATE_MASK    0xC
#define    RTL8370_VLAN_MSTI10_CTRL1_PORT8_STATE_OFFSET    0
#define    RTL8370_VLAN_MSTI10_CTRL1_PORT8_STATE_MASK    0x3

#define    RTL8370_REG_VLAN_MSTI11_CTRL0    0x0a16
#define    RTL8370_VLAN_MSTI11_CTRL0_PORT7_STATE_OFFSET    14
#define    RTL8370_VLAN_MSTI11_CTRL0_PORT7_STATE_MASK    0xC000
#define    RTL8370_VLAN_MSTI11_CTRL0_PORT6_STATE_OFFSET    12
#define    RTL8370_VLAN_MSTI11_CTRL0_PORT6_STATE_MASK    0x3000
#define    RTL8370_VLAN_MSTI11_CTRL0_PORT5_STATE_OFFSET    10
#define    RTL8370_VLAN_MSTI11_CTRL0_PORT5_STATE_MASK    0xC00
#define    RTL8370_VLAN_MSTI11_CTRL0_PORT4_STATE_OFFSET    8
#define    RTL8370_VLAN_MSTI11_CTRL0_PORT4_STATE_MASK    0x300
#define    RTL8370_VLAN_MSTI11_CTRL0_PORT3_STATE_OFFSET    6
#define    RTL8370_VLAN_MSTI11_CTRL0_PORT3_STATE_MASK    0xC0
#define    RTL8370_VLAN_MSTI11_CTRL0_PORT2_STATE_OFFSET    4
#define    RTL8370_VLAN_MSTI11_CTRL0_PORT2_STATE_MASK    0x30
#define    RTL8370_VLAN_MSTI11_CTRL0_PORT1_STATE_OFFSET    2
#define    RTL8370_VLAN_MSTI11_CTRL0_PORT1_STATE_MASK    0xC
#define    RTL8370_VLAN_MSTI11_CTRL0_PORT0_STATE_OFFSET    0
#define    RTL8370_VLAN_MSTI11_CTRL0_PORT0_STATE_MASK    0x3

#define    RTL8370_REG_VLAN_MSTI11_CTRL1    0x0a17
#define    RTL8370_VLAN_MSTI11_CTRL1_PORT15_STATE_OFFSET    14
#define    RTL8370_VLAN_MSTI11_CTRL1_PORT15_STATE_MASK    0xC000
#define    RTL8370_VLAN_MSTI11_CTRL1_PORT14_STATE_OFFSET    12
#define    RTL8370_VLAN_MSTI11_CTRL1_PORT14_STATE_MASK    0x3000
#define    RTL8370_VLAN_MSTI11_CTRL1_PORT13_STATE_OFFSET    10
#define    RTL8370_VLAN_MSTI11_CTRL1_PORT13_STATE_MASK    0xC00
#define    RTL8370_VLAN_MSTI11_CTRL1_PORT12_STATE_OFFSET    8
#define    RTL8370_VLAN_MSTI11_CTRL1_PORT12_STATE_MASK    0x300
#define    RTL8370_VLAN_MSTI11_CTRL1_PORT11_STATE_OFFSET    6
#define    RTL8370_VLAN_MSTI11_CTRL1_PORT11_STATE_MASK    0xC0
#define    RTL8370_VLAN_MSTI11_CTRL1_PORT10_STATE_OFFSET    4
#define    RTL8370_VLAN_MSTI11_CTRL1_PORT10_STATE_MASK    0x30
#define    RTL8370_VLAN_MSTI11_CTRL1_PORT9_STATE_OFFSET    2
#define    RTL8370_VLAN_MSTI11_CTRL1_PORT9_STATE_MASK    0xC
#define    RTL8370_VLAN_MSTI11_CTRL1_PORT8_STATE_OFFSET    0
#define    RTL8370_VLAN_MSTI11_CTRL1_PORT8_STATE_MASK    0x3

#define    RTL8370_REG_VLAN_MSTI12_CTRL0    0x0a18
#define    RTL8370_VLAN_MSTI12_CTRL0_PORT7_STATE_OFFSET    14
#define    RTL8370_VLAN_MSTI12_CTRL0_PORT7_STATE_MASK    0xC000
#define    RTL8370_VLAN_MSTI12_CTRL0_PORT6_STATE_OFFSET    12
#define    RTL8370_VLAN_MSTI12_CTRL0_PORT6_STATE_MASK    0x3000
#define    RTL8370_VLAN_MSTI12_CTRL0_PORT5_STATE_OFFSET    10
#define    RTL8370_VLAN_MSTI12_CTRL0_PORT5_STATE_MASK    0xC00
#define    RTL8370_VLAN_MSTI12_CTRL0_PORT4_STATE_OFFSET    8
#define    RTL8370_VLAN_MSTI12_CTRL0_PORT4_STATE_MASK    0x300
#define    RTL8370_VLAN_MSTI12_CTRL0_PORT3_STATE_OFFSET    6
#define    RTL8370_VLAN_MSTI12_CTRL0_PORT3_STATE_MASK    0xC0
#define    RTL8370_VLAN_MSTI12_CTRL0_PORT2_STATE_OFFSET    4
#define    RTL8370_VLAN_MSTI12_CTRL0_PORT2_STATE_MASK    0x30
#define    RTL8370_VLAN_MSTI12_CTRL0_PORT1_STATE_OFFSET    2
#define    RTL8370_VLAN_MSTI12_CTRL0_PORT1_STATE_MASK    0xC
#define    RTL8370_VLAN_MSTI12_CTRL0_PORT0_STATE_OFFSET    0
#define    RTL8370_VLAN_MSTI12_CTRL0_PORT0_STATE_MASK    0x3

#define    RTL8370_REG_VLAN_MSTI12_CTRL1    0x0a19
#define    RTL8370_VLAN_MSTI12_CTRL1_PORT15_STATE_OFFSET    14
#define    RTL8370_VLAN_MSTI12_CTRL1_PORT15_STATE_MASK    0xC000
#define    RTL8370_VLAN_MSTI12_CTRL1_PORT14_STATE_OFFSET    12
#define    RTL8370_VLAN_MSTI12_CTRL1_PORT14_STATE_MASK    0x3000
#define    RTL8370_VLAN_MSTI12_CTRL1_PORT13_STATE_OFFSET    10
#define    RTL8370_VLAN_MSTI12_CTRL1_PORT13_STATE_MASK    0xC00
#define    RTL8370_VLAN_MSTI12_CTRL1_PORT12_STATE_OFFSET    8
#define    RTL8370_VLAN_MSTI12_CTRL1_PORT12_STATE_MASK    0x300
#define    RTL8370_VLAN_MSTI12_CTRL1_PORT11_STATE_OFFSET    6
#define    RTL8370_VLAN_MSTI12_CTRL1_PORT11_STATE_MASK    0xC0
#define    RTL8370_VLAN_MSTI12_CTRL1_PORT10_STATE_OFFSET    4
#define    RTL8370_VLAN_MSTI12_CTRL1_PORT10_STATE_MASK    0x30
#define    RTL8370_VLAN_MSTI12_CTRL1_PORT9_STATE_OFFSET    2
#define    RTL8370_VLAN_MSTI12_CTRL1_PORT9_STATE_MASK    0xC
#define    RTL8370_VLAN_MSTI12_CTRL1_PORT8_STATE_OFFSET    0
#define    RTL8370_VLAN_MSTI12_CTRL1_PORT8_STATE_MASK    0x3

#define    RTL8370_REG_VLAN_MSTI13_CTRL0    0x0a1a
#define    RTL8370_VLAN_MSTI13_CTRL0_PORT7_STATE_OFFSET    14
#define    RTL8370_VLAN_MSTI13_CTRL0_PORT7_STATE_MASK    0xC000
#define    RTL8370_VLAN_MSTI13_CTRL0_PORT6_STATE_OFFSET    12
#define    RTL8370_VLAN_MSTI13_CTRL0_PORT6_STATE_MASK    0x3000
#define    RTL8370_VLAN_MSTI13_CTRL0_PORT5_STATE_OFFSET    10
#define    RTL8370_VLAN_MSTI13_CTRL0_PORT5_STATE_MASK    0xC00
#define    RTL8370_VLAN_MSTI13_CTRL0_PORT4_STATE_OFFSET    8
#define    RTL8370_VLAN_MSTI13_CTRL0_PORT4_STATE_MASK    0x300
#define    RTL8370_VLAN_MSTI13_CTRL0_PORT3_STATE_OFFSET    6
#define    RTL8370_VLAN_MSTI13_CTRL0_PORT3_STATE_MASK    0xC0
#define    RTL8370_VLAN_MSTI13_CTRL0_PORT2_STATE_OFFSET    4
#define    RTL8370_VLAN_MSTI13_CTRL0_PORT2_STATE_MASK    0x30
#define    RTL8370_VLAN_MSTI13_CTRL0_PORT1_STATE_OFFSET    2
#define    RTL8370_VLAN_MSTI13_CTRL0_PORT1_STATE_MASK    0xC
#define    RTL8370_VLAN_MSTI13_CTRL0_PORT0_STATE_OFFSET    0
#define    RTL8370_VLAN_MSTI13_CTRL0_PORT0_STATE_MASK    0x3

#define    RTL8370_REG_VLAN_MSTI13_CTRL1    0x0a1b
#define    RTL8370_VLAN_MSTI13_CTRL1_PORT15_STATE_OFFSET    14
#define    RTL8370_VLAN_MSTI13_CTRL1_PORT15_STATE_MASK    0xC000
#define    RTL8370_VLAN_MSTI13_CTRL1_PORT14_STATE_OFFSET    12
#define    RTL8370_VLAN_MSTI13_CTRL1_PORT14_STATE_MASK    0x3000
#define    RTL8370_VLAN_MSTI13_CTRL1_PORT13_STATE_OFFSET    10
#define    RTL8370_VLAN_MSTI13_CTRL1_PORT13_STATE_MASK    0xC00
#define    RTL8370_VLAN_MSTI13_CTRL1_PORT12_STATE_OFFSET    8
#define    RTL8370_VLAN_MSTI13_CTRL1_PORT12_STATE_MASK    0x300
#define    RTL8370_VLAN_MSTI13_CTRL1_PORT11_STATE_OFFSET    6
#define    RTL8370_VLAN_MSTI13_CTRL1_PORT11_STATE_MASK    0xC0
#define    RTL8370_VLAN_MSTI13_CTRL1_PORT10_STATE_OFFSET    4
#define    RTL8370_VLAN_MSTI13_CTRL1_PORT10_STATE_MASK    0x30
#define    RTL8370_VLAN_MSTI13_CTRL1_PORT9_STATE_OFFSET    2
#define    RTL8370_VLAN_MSTI13_CTRL1_PORT9_STATE_MASK    0xC
#define    RTL8370_VLAN_MSTI13_CTRL1_PORT8_STATE_OFFSET    0
#define    RTL8370_VLAN_MSTI13_CTRL1_PORT8_STATE_MASK    0x3

#define    RTL8370_REG_VLAN_MSTI14_CTRL0    0x0a1c
#define    RTL8370_VLAN_MSTI14_CTRL0_PORT7_STATE_OFFSET    14
#define    RTL8370_VLAN_MSTI14_CTRL0_PORT7_STATE_MASK    0xC000
#define    RTL8370_VLAN_MSTI14_CTRL0_PORT6_STATE_OFFSET    12
#define    RTL8370_VLAN_MSTI14_CTRL0_PORT6_STATE_MASK    0x3000
#define    RTL8370_VLAN_MSTI14_CTRL0_PORT5_STATE_OFFSET    10
#define    RTL8370_VLAN_MSTI14_CTRL0_PORT5_STATE_MASK    0xC00
#define    RTL8370_VLAN_MSTI14_CTRL0_PORT4_STATE_OFFSET    8
#define    RTL8370_VLAN_MSTI14_CTRL0_PORT4_STATE_MASK    0x300
#define    RTL8370_VLAN_MSTI14_CTRL0_PORT3_STATE_OFFSET    6
#define    RTL8370_VLAN_MSTI14_CTRL0_PORT3_STATE_MASK    0xC0
#define    RTL8370_VLAN_MSTI14_CTRL0_PORT2_STATE_OFFSET    4
#define    RTL8370_VLAN_MSTI14_CTRL0_PORT2_STATE_MASK    0x30
#define    RTL8370_VLAN_MSTI14_CTRL0_PORT1_STATE_OFFSET    2
#define    RTL8370_VLAN_MSTI14_CTRL0_PORT1_STATE_MASK    0xC
#define    RTL8370_VLAN_MSTI14_CTRL0_PORT0_STATE_OFFSET    0
#define    RTL8370_VLAN_MSTI14_CTRL0_PORT0_STATE_MASK    0x3

#define    RTL8370_REG_VLAN_MSTI14_CTRL1    0x0a1d
#define    RTL8370_VLAN_MSTI14_CTRL1_PORT15_STATE_OFFSET    14
#define    RTL8370_VLAN_MSTI14_CTRL1_PORT15_STATE_MASK    0xC000
#define    RTL8370_VLAN_MSTI14_CTRL1_PORT14_STATE_OFFSET    12
#define    RTL8370_VLAN_MSTI14_CTRL1_PORT14_STATE_MASK    0x3000
#define    RTL8370_VLAN_MSTI14_CTRL1_PORT13_STATE_OFFSET    10
#define    RTL8370_VLAN_MSTI14_CTRL1_PORT13_STATE_MASK    0xC00
#define    RTL8370_VLAN_MSTI14_CTRL1_PORT12_STATE_OFFSET    8
#define    RTL8370_VLAN_MSTI14_CTRL1_PORT12_STATE_MASK    0x300
#define    RTL8370_VLAN_MSTI14_CTRL1_PORT11_STATE_OFFSET    6
#define    RTL8370_VLAN_MSTI14_CTRL1_PORT11_STATE_MASK    0xC0
#define    RTL8370_VLAN_MSTI14_CTRL1_PORT10_STATE_OFFSET    4
#define    RTL8370_VLAN_MSTI14_CTRL1_PORT10_STATE_MASK    0x30
#define    RTL8370_VLAN_MSTI14_CTRL1_PORT9_STATE_OFFSET    2
#define    RTL8370_VLAN_MSTI14_CTRL1_PORT9_STATE_MASK    0xC
#define    RTL8370_VLAN_MSTI14_CTRL1_PORT8_STATE_OFFSET    0
#define    RTL8370_VLAN_MSTI14_CTRL1_PORT8_STATE_MASK    0x3

#define    RTL8370_REG_VLAN_MSTI15_CTRL0    0x0a1e
#define    RTL8370_VLAN_MSTI15_CTRL0_PORT7_STATE_OFFSET    14
#define    RTL8370_VLAN_MSTI15_CTRL0_PORT7_STATE_MASK    0xC000
#define    RTL8370_VLAN_MSTI15_CTRL0_PORT6_STATE_OFFSET    12
#define    RTL8370_VLAN_MSTI15_CTRL0_PORT6_STATE_MASK    0x3000
#define    RTL8370_VLAN_MSTI15_CTRL0_PORT5_STATE_OFFSET    10
#define    RTL8370_VLAN_MSTI15_CTRL0_PORT5_STATE_MASK    0xC00
#define    RTL8370_VLAN_MSTI15_CTRL0_PORT4_STATE_OFFSET    8
#define    RTL8370_VLAN_MSTI15_CTRL0_PORT4_STATE_MASK    0x300
#define    RTL8370_VLAN_MSTI15_CTRL0_PORT3_STATE_OFFSET    6
#define    RTL8370_VLAN_MSTI15_CTRL0_PORT3_STATE_MASK    0xC0
#define    RTL8370_VLAN_MSTI15_CTRL0_PORT2_STATE_OFFSET    4
#define    RTL8370_VLAN_MSTI15_CTRL0_PORT2_STATE_MASK    0x30
#define    RTL8370_VLAN_MSTI15_CTRL0_PORT1_STATE_OFFSET    2
#define    RTL8370_VLAN_MSTI15_CTRL0_PORT1_STATE_MASK    0xC
#define    RTL8370_VLAN_MSTI15_CTRL0_PORT0_STATE_OFFSET    0
#define    RTL8370_VLAN_MSTI15_CTRL0_PORT0_STATE_MASK    0x3

#define    RTL8370_REG_VLAN_MSTI15_CTRL1    0x0a1f
#define    RTL8370_VLAN_MSTI15_CTRL1_PORT15_STATE_OFFSET    14
#define    RTL8370_VLAN_MSTI15_CTRL1_PORT15_STATE_MASK    0xC000
#define    RTL8370_VLAN_MSTI15_CTRL1_PORT14_STATE_OFFSET    12
#define    RTL8370_VLAN_MSTI15_CTRL1_PORT14_STATE_MASK    0x3000
#define    RTL8370_VLAN_MSTI15_CTRL1_PORT13_STATE_OFFSET    10
#define    RTL8370_VLAN_MSTI15_CTRL1_PORT13_STATE_MASK    0xC00
#define    RTL8370_VLAN_MSTI15_CTRL1_PORT12_STATE_OFFSET    8
#define    RTL8370_VLAN_MSTI15_CTRL1_PORT12_STATE_MASK    0x300
#define    RTL8370_VLAN_MSTI15_CTRL1_PORT11_STATE_OFFSET    6
#define    RTL8370_VLAN_MSTI15_CTRL1_PORT11_STATE_MASK    0xC0
#define    RTL8370_VLAN_MSTI15_CTRL1_PORT10_STATE_OFFSET    4
#define    RTL8370_VLAN_MSTI15_CTRL1_PORT10_STATE_MASK    0x30
#define    RTL8370_VLAN_MSTI15_CTRL1_PORT9_STATE_OFFSET    2
#define    RTL8370_VLAN_MSTI15_CTRL1_PORT9_STATE_MASK    0xC
#define    RTL8370_VLAN_MSTI15_CTRL1_PORT8_STATE_OFFSET    0
#define    RTL8370_VLAN_MSTI15_CTRL1_PORT8_STATE_MASK    0x3

#define    RTL8370_REG_LUT_PORT0_LEARN_LIMITNO    0x0a20
#define    RTL8370_LUT_PORT0_LEARN_LIMITNO_OFFSET    0
#define    RTL8370_LUT_PORT0_LEARN_LIMITNO_MASK    0x3FFF

#define    RTL8370_REG_LUT_PORT1_LEARN_LIMITNO    0x0a21
#define    RTL8370_LUT_PORT1_LEARN_LIMITNO_OFFSET    0
#define    RTL8370_LUT_PORT1_LEARN_LIMITNO_MASK    0x3FFF

#define    RTL8370_REG_LUT_PORT2_LEARN_LIMITNO    0x0a22
#define    RTL8370_LUT_PORT2_LEARN_LIMITNO_OFFSET    0
#define    RTL8370_LUT_PORT2_LEARN_LIMITNO_MASK    0x3FFF

#define    RTL8370_REG_LUT_PORT3_LEARN_LIMITNO    0x0a23
#define    RTL8370_LUT_PORT3_LEARN_LIMITNO_OFFSET    0
#define    RTL8370_LUT_PORT3_LEARN_LIMITNO_MASK    0x3FFF

#define    RTL8370_REG_LUT_PORT4_LEARN_LIMITNO    0x0a24
#define    RTL8370_LUT_PORT4_LEARN_LIMITNO_OFFSET    0
#define    RTL8370_LUT_PORT4_LEARN_LIMITNO_MASK    0x3FFF

#define    RTL8370_REG_LUT_PORT5_LEARN_LIMITNO    0x0a25
#define    RTL8370_LUT_PORT5_LEARN_LIMITNO_OFFSET    0
#define    RTL8370_LUT_PORT5_LEARN_LIMITNO_MASK    0x3FFF

#define    RTL8370_REG_LUT_PORT6_LEARN_LIMITNO    0x0a26
#define    RTL8370_LUT_PORT6_LEARN_LIMITNO_OFFSET    0
#define    RTL8370_LUT_PORT6_LEARN_LIMITNO_MASK    0x3FFF

#define    RTL8370_REG_LUT_PORT7_LEARN_LIMITNO    0x0a27
#define    RTL8370_LUT_PORT7_LEARN_LIMITNO_OFFSET    0
#define    RTL8370_LUT_PORT7_LEARN_LIMITNO_MASK    0x3FFF

#define    RTL8370_REG_LUT_PORT8_LEARN_LIMITNO    0x0a28
#define    RTL8370_LUT_PORT8_LEARN_LIMITNO_OFFSET    0
#define    RTL8370_LUT_PORT8_LEARN_LIMITNO_MASK    0x3FFF

#define    RTL8370_REG_LUT_PORT9_LEARN_LIMITNO    0x0a29
#define    RTL8370_LUT_PORT9_LEARN_LIMITNO_OFFSET    0
#define    RTL8370_LUT_PORT9_LEARN_LIMITNO_MASK    0x3FFF

#define    RTL8370_REG_LUT_PORT10_LEARN_LIMITNO    0x0a2a
#define    RTL8370_LUT_PORT10_LEARN_LIMITNO_OFFSET    0
#define    RTL8370_LUT_PORT10_LEARN_LIMITNO_MASK    0x3FFF

#define    RTL8370_REG_LUT_PORT11_LEARN_LIMITNO    0x0a2b
#define    RTL8370_LUT_PORT11_LEARN_LIMITNO_OFFSET    0
#define    RTL8370_LUT_PORT11_LEARN_LIMITNO_MASK    0x3FFF

#define    RTL8370_REG_LUT_PORT12_LEARN_LIMITNO    0x0a2c
#define    RTL8370_LUT_PORT12_LEARN_LIMITNO_OFFSET    0
#define    RTL8370_LUT_PORT12_LEARN_LIMITNO_MASK    0x3FFF

#define    RTL8370_REG_LUT_PORT13_LEARN_LIMITNO    0x0a2d
#define    RTL8370_LUT_PORT13_LEARN_LIMITNO_OFFSET    0
#define    RTL8370_LUT_PORT13_LEARN_LIMITNO_MASK    0x3FFF

#define    RTL8370_REG_LUT_PORT14_LEARN_LIMITNO    0x0a2e
#define    RTL8370_LUT_PORT14_LEARN_LIMITNO_OFFSET    0
#define    RTL8370_LUT_PORT14_LEARN_LIMITNO_MASK    0x3FFF

#define    RTL8370_REG_LUT_PORT15_LEARN_LIMITNO    0x0a2f
#define    RTL8370_LUT_PORT15_LEARN_LIMITNO_OFFSET    0
#define    RTL8370_LUT_PORT15_LEARN_LIMITNO_MASK    0x3FFF

#define    RTL8370_REG_LUT_CFG    0x0a30
#define    RTL8370_AGE_SPEED_OFFSET    8
#define    RTL8370_AGE_SPEED_MASK    0x300
#define    RTL8370_BCAM_TYPE_OFFSET    7
#define    RTL8370_BCAM_TYPE_MASK    0x80
#define    RTL8370_BCAM_DISABLE_OFFSET    6
#define    RTL8370_BCAM_DISABLE_MASK    0x40
#define    RTL8370_LINKDOWN_AGEOUT_OFFSET    5
#define    RTL8370_LINKDOWN_AGEOUT_MASK    0x20
#define    RTL8370_IPMCAST_LOOKUP_OFFSET    4
#define    RTL8370_IPMCAST_LOOKUP_MASK    0x10
#define    RTL8370_AGE_TIMER_OFFSET    0
#define    RTL8370_AGE_TIMER_MASK    0x7

#define    RTL8370_REG_LUT_AGEOUT_CRTL    0x0a31

#define    RTL8370_REG_PORT_EFID_CTRL0    0x0a32
#define    RTL8370_PORT3_EFID_OFFSET    12
#define    RTL8370_PORT3_EFID_MASK    0x7000
#define    RTL8370_PORT2_EFID_OFFSET    8
#define    RTL8370_PORT2_EFID_MASK    0x700
#define    RTL8370_PORT1_EFID_OFFSET    4
#define    RTL8370_PORT1_EFID_MASK    0x70
#define    RTL8370_PORT0_EFID_OFFSET    0
#define    RTL8370_PORT0_EFID_MASK    0x7

#define    RTL8370_REG_PORT_EFID_CTRL1    0x0a33
#define    RTL8370_PORT7_EFID_OFFSET    12
#define    RTL8370_PORT7_EFID_MASK    0x7000
#define    RTL8370_PORT6_EFID_OFFSET    8
#define    RTL8370_PORT6_EFID_MASK    0x700
#define    RTL8370_PORT5_EFID_OFFSET    4
#define    RTL8370_PORT5_EFID_MASK    0x70
#define    RTL8370_PORT4_EFID_OFFSET    0
#define    RTL8370_PORT4_EFID_MASK    0x7

#define    RTL8370_REG_PORT_EFID_CTRL2    0x0a34
#define    RTL8370_PORT11_EFID_OFFSET    12
#define    RTL8370_PORT11_EFID_MASK    0x7000
#define    RTL8370_PORT10_EFID_OFFSET    8
#define    RTL8370_PORT10_EFID_MASK    0x700
#define    RTL8370_PORT9_EFID_OFFSET    4
#define    RTL8370_PORT9_EFID_MASK    0x70
#define    RTL8370_PORT8_EFID_OFFSET    0
#define    RTL8370_PORT8_EFID_MASK    0x7

#define    RTL8370_REG_PORT_EFID_CTRL3    0x0a35
#define    RTL8370_PORT15_EFID_OFFSET    12
#define    RTL8370_PORT15_EFID_MASK    0x7000
#define    RTL8370_PORT14_EFID_OFFSET    8
#define    RTL8370_PORT14_EFID_MASK    0x700
#define    RTL8370_PORT13_EFID_OFFSET    4
#define    RTL8370_PORT13_EFID_MASK    0x70
#define    RTL8370_PORT12_EFID_OFFSET    0
#define    RTL8370_PORT12_EFID_MASK    0x7

#define    RTL8370_REG_FORCE_FLUSH    0x0a36

#define    RTL8370_REG_STORM_BCAST    0x0a40

#define    RTL8370_REG_STORM_MCAST    0x0a41

#define    RTL8370_REG_STORM_UNKOWN_UCAST    0x0a42

#define    RTL8370_REG_STORM_UNKOWN_MCAST    0x0a43

#define    RTL8370_REG_STORM_BCAST_METER_CRTL0    0x0a44
#define    RTL8370_STORM_BCAST_METER_CRTL0_PORT1_METERIDX_OFFSET    8
#define    RTL8370_STORM_BCAST_METER_CRTL0_PORT1_METERIDX_MASK    0xFF00
#define    RTL8370_STORM_BCAST_METER_CRTL0_PORT0_METERIDX_OFFSET    0
#define    RTL8370_STORM_BCAST_METER_CRTL0_PORT0_METERIDX_MASK    0xFF

#define    RTL8370_REG_STORM_BCAST_METER_CRTL1    0x0a45
#define    RTL8370_STORM_BCAST_METER_CRTL1_PORT3_METERIDX_OFFSET    8
#define    RTL8370_STORM_BCAST_METER_CRTL1_PORT3_METERIDX_MASK    0xFF00
#define    RTL8370_STORM_BCAST_METER_CRTL1_PORT2_METERIDX_OFFSET    0
#define    RTL8370_STORM_BCAST_METER_CRTL1_PORT2_METERIDX_MASK    0xFF

#define    RTL8370_REG_STORM_BCAST_METER_CRTL2    0x0a46
#define    RTL8370_STORM_BCAST_METER_CRTL2_PORT5_METERIDX_OFFSET    8
#define    RTL8370_STORM_BCAST_METER_CRTL2_PORT5_METERIDX_MASK    0xFF00
#define    RTL8370_STORM_BCAST_METER_CRTL2_PORT4_METERIDX_OFFSET    0
#define    RTL8370_STORM_BCAST_METER_CRTL2_PORT4_METERIDX_MASK    0xFF

#define    RTL8370_REG_STORM_BCAST_METER_CRTL3    0x0a47
#define    RTL8370_STORM_BCAST_METER_CRTL3_PORT7_METERIDX_OFFSET    8
#define    RTL8370_STORM_BCAST_METER_CRTL3_PORT7_METERIDX_MASK    0xFF00
#define    RTL8370_STORM_BCAST_METER_CRTL3_PORT6_METERIDX_OFFSET    0
#define    RTL8370_STORM_BCAST_METER_CRTL3_PORT6_METERIDX_MASK    0xFF

#define    RTL8370_REG_STORM_BCAST_METER_CRTL4    0x0a48
#define    RTL8370_STORM_BCAST_METER_CRTL4_PORT9_METERIDX_OFFSET    8
#define    RTL8370_STORM_BCAST_METER_CRTL4_PORT9_METERIDX_MASK    0xFF00
#define    RTL8370_STORM_BCAST_METER_CRTL4_PORT8_METERIDX_OFFSET    0
#define    RTL8370_STORM_BCAST_METER_CRTL4_PORT8_METERIDX_MASK    0xFF

#define    RTL8370_REG_STORM_BCAST_METER_CRTL5    0x0a49
#define    RTL8370_STORM_BCAST_METER_CRTL5_PORT11_METERIDX_OFFSET    8
#define    RTL8370_STORM_BCAST_METER_CRTL5_PORT11_METERIDX_MASK    0xFF00
#define    RTL8370_STORM_BCAST_METER_CRTL5_PORT10_METERIDX_OFFSET    0
#define    RTL8370_STORM_BCAST_METER_CRTL5_PORT10_METERIDX_MASK    0xFF

#define    RTL8370_REG_STORM_BCAST_METER_CRTL6    0x0a4a
#define    RTL8370_STORM_BCAST_METER_CRTL6_PORT13_METERIDX_OFFSET    8
#define    RTL8370_STORM_BCAST_METER_CRTL6_PORT13_METERIDX_MASK    0xFF00
#define    RTL8370_STORM_BCAST_METER_CRTL6_PORT12_METERIDX_OFFSET    0
#define    RTL8370_STORM_BCAST_METER_CRTL6_PORT12_METERIDX_MASK    0xFF

#define    RTL8370_REG_STORM_BCAST_METER_CRTL7    0x0a4b
#define    RTL8370_STORM_BCAST_METER_CRTL7_PORT15_METERIDX_OFFSET    8
#define    RTL8370_STORM_BCAST_METER_CRTL7_PORT15_METERIDX_MASK    0xFF00
#define    RTL8370_STORM_BCAST_METER_CRTL7_PORT14_METERIDX_OFFSET    0
#define    RTL8370_STORM_BCAST_METER_CRTL7_PORT14_METERIDX_MASK    0xFF

#define    RTL8370_REG_STORM_MCAST_METER_CRTL0    0x0a4c
#define    RTL8370_STORM_MCAST_METER_CRTL0_PORT1_METERIDX_OFFSET    8
#define    RTL8370_STORM_MCAST_METER_CRTL0_PORT1_METERIDX_MASK    0xFF00
#define    RTL8370_STORM_MCAST_METER_CRTL0_PORT0_METERIDX_OFFSET    0
#define    RTL8370_STORM_MCAST_METER_CRTL0_PORT0_METERIDX_MASK    0xFF

#define    RTL8370_REG_STORM_MCAST_METER_CRTL1    0x0a4d
#define    RTL8370_STORM_MCAST_METER_CRTL1_PORT3_METERIDX_OFFSET    8
#define    RTL8370_STORM_MCAST_METER_CRTL1_PORT3_METERIDX_MASK    0xFF00
#define    RTL8370_STORM_MCAST_METER_CRTL1_PORT2_METERIDX_OFFSET    0
#define    RTL8370_STORM_MCAST_METER_CRTL1_PORT2_METERIDX_MASK    0xFF

#define    RTL8370_REG_STORM_MCAST_METER_CRTL2    0x0a4e
#define    RTL8370_STORM_MCAST_METER_CRTL2_PORT5_METERIDX_OFFSET    8
#define    RTL8370_STORM_MCAST_METER_CRTL2_PORT5_METERIDX_MASK    0xFF00
#define    RTL8370_STORM_MCAST_METER_CRTL2_PORT4_METERIDX_OFFSET    0
#define    RTL8370_STORM_MCAST_METER_CRTL2_PORT4_METERIDX_MASK    0xFF

#define    RTL8370_REG_STORM_MCAST_METER_CRTL3    0x0a4f
#define    RTL8370_STORM_MCAST_METER_CRTL3_PORT7_METERIDX_OFFSET    8
#define    RTL8370_STORM_MCAST_METER_CRTL3_PORT7_METERIDX_MASK    0xFF00
#define    RTL8370_STORM_MCAST_METER_CRTL3_PORT6_METERIDX_OFFSET    0
#define    RTL8370_STORM_MCAST_METER_CRTL3_PORT6_METERIDX_MASK    0xFF

#define    RTL8370_REG_STORM_MCAST_METER_CRTL4    0x0a50
#define    RTL8370_STORM_MCAST_METER_CRTL4_PORT9_METERIDX_OFFSET    8
#define    RTL8370_STORM_MCAST_METER_CRTL4_PORT9_METERIDX_MASK    0xFF00
#define    RTL8370_STORM_MCAST_METER_CRTL4_PORT8_METERIDX_OFFSET    0
#define    RTL8370_STORM_MCAST_METER_CRTL4_PORT8_METERIDX_MASK    0xFF

#define    RTL8370_REG_STORM_MCAST_METER_CRTL5    0x0a51
#define    RTL8370_STORM_MCAST_METER_CRTL5_PORT11_METERIDX_OFFSET    8
#define    RTL8370_STORM_MCAST_METER_CRTL5_PORT11_METERIDX_MASK    0xFF00
#define    RTL8370_STORM_MCAST_METER_CRTL5_PORT10_METERIDX_OFFSET    0
#define    RTL8370_STORM_MCAST_METER_CRTL5_PORT10_METERIDX_MASK    0xFF

#define    RTL8370_REG_STORM_MCAST_METER_CRTL6    0x0a52
#define    RTL8370_STORM_MCAST_METER_CRTL6_PORT13_METERIDX_OFFSET    8
#define    RTL8370_STORM_MCAST_METER_CRTL6_PORT13_METERIDX_MASK    0xFF00
#define    RTL8370_STORM_MCAST_METER_CRTL6_PORT12_METERIDX_OFFSET    0
#define    RTL8370_STORM_MCAST_METER_CRTL6_PORT12_METERIDX_MASK    0xFF

#define    RTL8370_REG_STORM_MCAST_METER_CRTL7    0x0a53
#define    RTL8370_STORM_MCAST_METER_CRTL7_PORT15_METERIDX_OFFSET    8
#define    RTL8370_STORM_MCAST_METER_CRTL7_PORT15_METERIDX_MASK    0xFF00
#define    RTL8370_STORM_MCAST_METER_CRTL7_PORT14_METERIDX_OFFSET    0
#define    RTL8370_STORM_MCAST_METER_CRTL7_PORT14_METERIDX_MASK    0xFF

#define    RTL8370_REG_STORM_UNDA_METER_CRTL0    0x0a54
#define    RTL8370_STORM_UNDA_METER_CRTL0_PORT1_METERIDX_OFFSET    8
#define    RTL8370_STORM_UNDA_METER_CRTL0_PORT1_METERIDX_MASK    0xFF00
#define    RTL8370_STORM_UNDA_METER_CRTL0_PORT0_METERIDX_OFFSET    0
#define    RTL8370_STORM_UNDA_METER_CRTL0_PORT0_METERIDX_MASK    0xFF

#define    RTL8370_REG_STORM_UNDA_METER_CRTL1    0x0a55
#define    RTL8370_STORM_UNDA_METER_CRTL1_PORT3_METERIDX_OFFSET    8
#define    RTL8370_STORM_UNDA_METER_CRTL1_PORT3_METERIDX_MASK    0xFF00
#define    RTL8370_STORM_UNDA_METER_CRTL1_PORT2_METERIDX_OFFSET    0
#define    RTL8370_STORM_UNDA_METER_CRTL1_PORT2_METERIDX_MASK    0xFF

#define    RTL8370_REG_STORM_UNDA_METER_CRTL2    0x0a56
#define    RTL8370_STORM_UNDA_METER_CRTL2_PORT5_METERIDX_OFFSET    8
#define    RTL8370_STORM_UNDA_METER_CRTL2_PORT5_METERIDX_MASK    0xFF00
#define    RTL8370_STORM_UNDA_METER_CRTL2_PORT4_METERIDX_OFFSET    0
#define    RTL8370_STORM_UNDA_METER_CRTL2_PORT4_METERIDX_MASK    0xFF

#define    RTL8370_REG_STORM_UNDA_METER_CRTL3    0x0a57
#define    RTL8370_STORM_UNDA_METER_CRTL3_PORT7_METERIDX_OFFSET    8
#define    RTL8370_STORM_UNDA_METER_CRTL3_PORT7_METERIDX_MASK    0xFF00
#define    RTL8370_STORM_UNDA_METER_CRTL3_PORT6_METERIDX_OFFSET    0
#define    RTL8370_STORM_UNDA_METER_CRTL3_PORT6_METERIDX_MASK    0xFF

#define    RTL8370_REG_STORM_UNDA_METER_CRTL4    0x0a58
#define    RTL8370_STORM_UNDA_METER_CRTL4_PORT9_METERIDX_OFFSET    8
#define    RTL8370_STORM_UNDA_METER_CRTL4_PORT9_METERIDX_MASK    0xFF00
#define    RTL8370_STORM_UNDA_METER_CRTL4_PORT8_METERIDX_OFFSET    0
#define    RTL8370_STORM_UNDA_METER_CRTL4_PORT8_METERIDX_MASK    0xFF

#define    RTL8370_REG_STORM_UNDA_METER_CRTL5    0x0a59
#define    RTL8370_STORM_UNDA_METER_CRTL5_PORT11_METERIDX_OFFSET    8
#define    RTL8370_STORM_UNDA_METER_CRTL5_PORT11_METERIDX_MASK    0xFF00
#define    RTL8370_STORM_UNDA_METER_CRTL5_PORT10_METERIDX_OFFSET    0
#define    RTL8370_STORM_UNDA_METER_CRTL5_PORT10_METERIDX_MASK    0xFF

#define    RTL8370_REG_STORM_UNDA_METER_CRTL6    0x0a5a
#define    RTL8370_STORM_UNDA_METER_CRTL6_PORT13_METERIDX_OFFSET    8
#define    RTL8370_STORM_UNDA_METER_CRTL6_PORT13_METERIDX_MASK    0xFF00
#define    RTL8370_STORM_UNDA_METER_CRTL6_PORT12_METERIDX_OFFSET    0
#define    RTL8370_STORM_UNDA_METER_CRTL6_PORT12_METERIDX_MASK    0xFF

#define    RTL8370_REG_STORM_UNDA_METER_CRTL7    0x0a5b
#define    RTL8370_STORM_UNDA_METER_CRTL7_PORT15_METERIDX_OFFSET    8
#define    RTL8370_STORM_UNDA_METER_CRTL7_PORT15_METERIDX_MASK    0xFF00
#define    RTL8370_STORM_UNDA_METER_CRTL7_PORT14_METERIDX_OFFSET    0
#define    RTL8370_STORM_UNDA_METER_CRTL7_PORT14_METERIDX_MASK    0xFF

#define    RTL8370_REG_STORM_UNMC_METER_CRTL0    0x0a5c
#define    RTL8370_STORM_UNMC_METER_CRTL0_PORT1_METERIDX_OFFSET    8
#define    RTL8370_STORM_UNMC_METER_CRTL0_PORT1_METERIDX_MASK    0xFF00
#define    RTL8370_STORM_UNMC_METER_CRTL0_PORT0_METERIDX_OFFSET    0
#define    RTL8370_STORM_UNMC_METER_CRTL0_PORT0_METERIDX_MASK    0xFF

#define    RTL8370_REG_STORM_UNMC_METER_CRTL1    0x0a5d
#define    RTL8370_STORM_UNMC_METER_CRTL1_PORT3_METERIDX_OFFSET    8
#define    RTL8370_STORM_UNMC_METER_CRTL1_PORT3_METERIDX_MASK    0xFF00
#define    RTL8370_STORM_UNMC_METER_CRTL1_PORT2_METERIDX_OFFSET    0
#define    RTL8370_STORM_UNMC_METER_CRTL1_PORT2_METERIDX_MASK    0xFF

#define    RTL8370_REG_STORM_UNMC_METER_CRTL2    0x0a5e
#define    RTL8370_STORM_UNMC_METER_CRTL2_PORT5_METERIDX_OFFSET    8
#define    RTL8370_STORM_UNMC_METER_CRTL2_PORT5_METERIDX_MASK    0xFF00
#define    RTL8370_STORM_UNMC_METER_CRTL2_PORT4_METERIDX_OFFSET    0
#define    RTL8370_STORM_UNMC_METER_CRTL2_PORT4_METERIDX_MASK    0xFF

#define    RTL8370_REG_STORM_UNMC_METER_CRTL3    0x0a5f
#define    RTL8370_STORM_UNMC_METER_CRTL3_PORT7_METERIDX_OFFSET    8
#define    RTL8370_STORM_UNMC_METER_CRTL3_PORT7_METERIDX_MASK    0xFF00
#define    RTL8370_STORM_UNMC_METER_CRTL3_PORT6_METERIDX_OFFSET    0
#define    RTL8370_STORM_UNMC_METER_CRTL3_PORT6_METERIDX_MASK    0xFF

#define    RTL8370_REG_STORM_UNMC_METER_CRTL4    0x0a60
#define    RTL8370_STORM_UNMC_METER_CRTL4_PORT9_METERIDX_OFFSET    8
#define    RTL8370_STORM_UNMC_METER_CRTL4_PORT9_METERIDX_MASK    0xFF00
#define    RTL8370_STORM_UNMC_METER_CRTL4_PORT8_METERIDX_OFFSET    0
#define    RTL8370_STORM_UNMC_METER_CRTL4_PORT8_METERIDX_MASK    0xFF

#define    RTL8370_REG_STORM_UNMC_METER_CRTL5    0x0a61
#define    RTL8370_STORM_UNMC_METER_CRTL5_PORT11_METERIDX_OFFSET    8
#define    RTL8370_STORM_UNMC_METER_CRTL5_PORT11_METERIDX_MASK    0xFF00
#define    RTL8370_STORM_UNMC_METER_CRTL5_PORT10_METERIDX_OFFSET    0
#define    RTL8370_STORM_UNMC_METER_CRTL5_PORT10_METERIDX_MASK    0xFF

#define    RTL8370_REG_STORM_UNMC_METER_CRTL6    0x0a62
#define    RTL8370_STORM_UNMC_METER_CRTL6_PORT13_METERIDX_OFFSET    8
#define    RTL8370_STORM_UNMC_METER_CRTL6_PORT13_METERIDX_MASK    0xFF00
#define    RTL8370_STORM_UNMC_METER_CRTL6_PORT12_METERIDX_OFFSET    0
#define    RTL8370_STORM_UNMC_METER_CRTL6_PORT12_METERIDX_MASK    0xFF

#define    RTL8370_REG_STORM_UNMC_METER_CRTL7    0x0a63
#define    RTL8370_STORM_UNMC_METER_CRTL7_PORT15_METERIDX_OFFSET    8
#define    RTL8370_STORM_UNMC_METER_CRTL7_PORT15_METERIDX_MASK    0xFF00
#define    RTL8370_STORM_UNMC_METER_CRTL7_PORT14_METERIDX_OFFSET    0
#define    RTL8370_STORM_UNMC_METER_CRTL7_PORT14_METERIDX_MASK    0xFF

#define    RTL8370_REG_OAM_PARSER_CTRL0    0x0a70
#define    RTL8370_PORT7_PARACT_OFFSET    14
#define    RTL8370_PORT7_PARACT_MASK    0xC000
#define    RTL8370_PORT6_PARACT_OFFSET    12
#define    RTL8370_PORT6_PARACT_MASK    0x3000
#define    RTL8370_PORT5_PARACT_OFFSET    10
#define    RTL8370_PORT5_PARACT_MASK    0xC00
#define    RTL8370_PORT4_PARACT_OFFSET    8
#define    RTL8370_PORT4_PARACT_MASK    0x300
#define    RTL8370_PORT3_PARACT_OFFSET    6
#define    RTL8370_PORT3_PARACT_MASK    0xC0
#define    RTL8370_PORT2_PARACT_OFFSET    4
#define    RTL8370_PORT2_PARACT_MASK    0x30
#define    RTL8370_PORT1_PARACT_OFFSET    2
#define    RTL8370_PORT1_PARACT_MASK    0xC
#define    RTL8370_PORT0_PARACT_OFFSET    0
#define    RTL8370_PORT0_PARACT_MASK    0x3

#define    RTL8370_REG_OAM_PARSER_CTRL1    0x0a71
#define    RTL8370_PORT15_PARACT_OFFSET    14
#define    RTL8370_PORT15_PARACT_MASK    0xC000
#define    RTL8370_PORT14_PARACT_OFFSET    12
#define    RTL8370_PORT14_PARACT_MASK    0x3000
#define    RTL8370_PORT13_PARACT_OFFSET    10
#define    RTL8370_PORT13_PARACT_MASK    0xC00
#define    RTL8370_PORT12_PARACT_OFFSET    8
#define    RTL8370_PORT12_PARACT_MASK    0x300
#define    RTL8370_PORT11_PARACT_OFFSET    6
#define    RTL8370_PORT11_PARACT_MASK    0xC0
#define    RTL8370_PORT10_PARACT_OFFSET    4
#define    RTL8370_PORT10_PARACT_MASK    0x30
#define    RTL8370_PORT9_PARACT_OFFSET    2
#define    RTL8370_PORT9_PARACT_MASK    0xC
#define    RTL8370_PORT8_PARACT_OFFSET    0
#define    RTL8370_PORT8_PARACT_MASK    0x3

#define    RTL8370_REG_OAM_MULTIPLEXER_CTRL0    0x0a72
#define    RTL8370_PORT7_MULACT_OFFSET    14
#define    RTL8370_PORT7_MULACT_MASK    0xC000
#define    RTL8370_PORT6_MULACT_OFFSET    12
#define    RTL8370_PORT6_MULACT_MASK    0x3000
#define    RTL8370_PORT5_MULACT_OFFSET    10
#define    RTL8370_PORT5_MULACT_MASK    0xC00
#define    RTL8370_PORT4_MULACT_OFFSET    8
#define    RTL8370_PORT4_MULACT_MASK    0x300
#define    RTL8370_PORT3_MULACT_OFFSET    6
#define    RTL8370_PORT3_MULACT_MASK    0xC0
#define    RTL8370_PORT2_MULACT_OFFSET    4
#define    RTL8370_PORT2_MULACT_MASK    0x30
#define    RTL8370_PORT1_MULACT_OFFSET    2
#define    RTL8370_PORT1_MULACT_MASK    0xC
#define    RTL8370_PORT0_MULACT_OFFSET    0
#define    RTL8370_PORT0_MULACT_MASK    0x3

#define    RTL8370_REG_OAM_MULTIPLEXER_CTRL1    0x0a73
#define    RTL8370_PORT15_MULACT_OFFSET    14
#define    RTL8370_PORT15_MULACT_MASK    0xC000
#define    RTL8370_PORT14_MULACT_OFFSET    12
#define    RTL8370_PORT14_MULACT_MASK    0x3000
#define    RTL8370_PORT13_MULACT_OFFSET    10
#define    RTL8370_PORT13_MULACT_MASK    0xC00
#define    RTL8370_PORT12_MULACT_OFFSET    8
#define    RTL8370_PORT12_MULACT_MASK    0x300
#define    RTL8370_PORT11_MULACT_OFFSET    6
#define    RTL8370_PORT11_MULACT_MASK    0xC0
#define    RTL8370_PORT10_MULACT_OFFSET    4
#define    RTL8370_PORT10_MULACT_MASK    0x30
#define    RTL8370_PORT9_MULACT_OFFSET    2
#define    RTL8370_PORT9_MULACT_MASK    0xC
#define    RTL8370_PORT8_MULACT_OFFSET    0
#define    RTL8370_PORT8_MULACT_MASK    0x3

#define    RTL8370_REG_OAM_CTRL    0x0a74
#define    RTL8370_OAM_CTRL_OFFSET    0
#define    RTL8370_OAM_CTRL_MASK    0x1

#define    RTL8370_REG_DOT1X_PORT_ENABLE    0x0a80

#define    RTL8370_REG_DOT1X_MAC_ENABLE    0x0a81

#define    RTL8370_REG_DOT1X_PORT_AUTH    0x0a82

#define    RTL8370_REG_DOT1X_PORT_OPDIR    0x0a83

#define    RTL8370_REG_DOT1X_UNAUTH_ACT_W0    0x0a84
#define    RTL8370_DOT1X_PORT7_UNAUTHBH_OFFSET    14
#define    RTL8370_DOT1X_PORT7_UNAUTHBH_MASK    0xC000
#define    RTL8370_DOT1X_PORT6_UNAUTHBH_OFFSET    12
#define    RTL8370_DOT1X_PORT6_UNAUTHBH_MASK    0x3000
#define    RTL8370_DOT1X_PORT5_UNAUTHBH_OFFSET    10
#define    RTL8370_DOT1X_PORT5_UNAUTHBH_MASK    0xC00
#define    RTL8370_DOT1X_PORT4_UNAUTHBH_OFFSET    8
#define    RTL8370_DOT1X_PORT4_UNAUTHBH_MASK    0x300
#define    RTL8370_DOT1X_PORT3_UNAUTHBH_OFFSET    6
#define    RTL8370_DOT1X_PORT3_UNAUTHBH_MASK    0xC0
#define    RTL8370_DOT1X_PORT2_UNAUTHBH_OFFSET    4
#define    RTL8370_DOT1X_PORT2_UNAUTHBH_MASK    0x30
#define    RTL8370_DOT1X_PORT1_UNAUTHBH_OFFSET    2
#define    RTL8370_DOT1X_PORT1_UNAUTHBH_MASK    0xC
#define    RTL8370_DOT1X_PORT0_UNAUTHBH_OFFSET    0
#define    RTL8370_DOT1X_PORT0_UNAUTHBH_MASK    0x3

#define    RTL8370_REG_DOT1X_UNAUTH_ACT_W1    0x0a85
#define    RTL8370_DOT1X_PORT15_UNAUTHBH_OFFSET    14
#define    RTL8370_DOT1X_PORT15_UNAUTHBH_MASK    0xC000
#define    RTL8370_DOT1X_PORT14_UNAUTHBH_OFFSET    12
#define    RTL8370_DOT1X_PORT14_UNAUTHBH_MASK    0x3000
#define    RTL8370_DOT1X_PORT13_UNAUTHBH_OFFSET    10
#define    RTL8370_DOT1X_PORT13_UNAUTHBH_MASK    0xC00
#define    RTL8370_DOT1X_PORT12_UNAUTHBH_OFFSET    8
#define    RTL8370_DOT1X_PORT12_UNAUTHBH_MASK    0x300
#define    RTL8370_DOT1X_PORT11_UNAUTHBH_OFFSET    6
#define    RTL8370_DOT1X_PORT11_UNAUTHBH_MASK    0xC0
#define    RTL8370_DOT1X_PORT10_UNAUTHBH_OFFSET    4
#define    RTL8370_DOT1X_PORT10_UNAUTHBH_MASK    0x30
#define    RTL8370_DOT1X_PORT9_UNAUTHBH_OFFSET    2
#define    RTL8370_DOT1X_PORT9_UNAUTHBH_MASK    0xC
#define    RTL8370_DOT1X_PORT8_UNAUTHBH_OFFSET    0
#define    RTL8370_DOT1X_PORT8_UNAUTHBH_MASK    0x3

#define    RTL8370_REG_DOT1X_CFG    0x0a86
#define    RTL8370_DOT1X_GVOPDIR_OFFSET    6
#define    RTL8370_DOT1X_GVOPDIR_MASK    0x40
#define    RTL8370_DOT1X_MAC_OPDIR_OFFSET    5
#define    RTL8370_DOT1X_MAC_OPDIR_MASK    0x20
#define    RTL8370_DOT1X_GVIDX_OFFSET    0
#define    RTL8370_DOT1X_GVIDX_MASK    0x1F

#define    RTL8370_REG_L2_LRN_CNT_CTRL0    0x0a87
#define    RTL8370_L2_LRN_CNT_CTRL0_OFFSET    0
#define    RTL8370_L2_LRN_CNT_CTRL0_MASK    0x3FFF

#define    RTL8370_REG_L2_LRN_CNT_CTRL1    0x0a88
#define    RTL8370_L2_LRN_CNT_CTRL1_OFFSET    0
#define    RTL8370_L2_LRN_CNT_CTRL1_MASK    0x3FFF

#define    RTL8370_REG_L2_LRN_CNT_CTRL2    0x0a89
#define    RTL8370_L2_LRN_CNT_CTRL2_OFFSET    0
#define    RTL8370_L2_LRN_CNT_CTRL2_MASK    0x3FFF

#define    RTL8370_REG_L2_LRN_CNT_CTRL3    0x0a8a
#define    RTL8370_L2_LRN_CNT_CTRL3_OFFSET    0
#define    RTL8370_L2_LRN_CNT_CTRL3_MASK    0x3FFF

#define    RTL8370_REG_L2_LRN_CNT_CTRL4    0x0a8b
#define    RTL8370_L2_LRN_CNT_CTRL4_OFFSET    0
#define    RTL8370_L2_LRN_CNT_CTRL4_MASK    0x3FFF

#define    RTL8370_REG_L2_LRN_CNT_CTRL5    0x0a8c
#define    RTL8370_L2_LRN_CNT_CTRL5_OFFSET    0
#define    RTL8370_L2_LRN_CNT_CTRL5_MASK    0x3FFF

#define    RTL8370_REG_L2_LRN_CNT_CTRL6    0x0a8d
#define    RTL8370_L2_LRN_CNT_CTRL6_OFFSET    0
#define    RTL8370_L2_LRN_CNT_CTRL6_MASK    0x3FFF

#define    RTL8370_REG_L2_LRN_CNT_CTRL7    0x0a8e
#define    RTL8370_L2_LRN_CNT_CTRL7_OFFSET    0
#define    RTL8370_L2_LRN_CNT_CTRL7_MASK    0x3FFF

#define    RTL8370_REG_L2_LRN_CNT_CTRL8    0x0a8f
#define    RTL8370_L2_LRN_CNT_CTRL8_OFFSET    0
#define    RTL8370_L2_LRN_CNT_CTRL8_MASK    0x3FFF

#define    RTL8370_REG_L2_LRN_CNT_CTRL9    0x0a90
#define    RTL8370_L2_LRN_CNT_CTRL9_OFFSET    0
#define    RTL8370_L2_LRN_CNT_CTRL9_MASK    0x3FFF

#define    RTL8370_REG_L2_LRN_CNT_CTRL10    0x0a91
#define    RTL8370_L2_LRN_CNT_CTRL10_OFFSET    0
#define    RTL8370_L2_LRN_CNT_CTRL10_MASK    0x3FFF

#define    RTL8370_REG_L2_LRN_CNT_CTRL11    0x0a92
#define    RTL8370_L2_LRN_CNT_CTRL11_OFFSET    0
#define    RTL8370_L2_LRN_CNT_CTRL11_MASK    0x3FFF

#define    RTL8370_REG_L2_LRN_CNT_CTRL12    0x0a93
#define    RTL8370_L2_LRN_CNT_CTRL12_OFFSET    0
#define    RTL8370_L2_LRN_CNT_CTRL12_MASK    0x3FFF

#define    RTL8370_REG_L2_LRN_CNT_CTRL13    0x0a94
#define    RTL8370_L2_LRN_CNT_CTRL13_OFFSET    0
#define    RTL8370_L2_LRN_CNT_CTRL13_MASK    0x3FFF

#define    RTL8370_REG_L2_LRN_CNT_CTRL14    0x0a95
#define    RTL8370_L2_LRN_CNT_CTRL14_OFFSET    0
#define    RTL8370_L2_LRN_CNT_CTRL14_MASK    0x3FFF

#define    RTL8370_REG_L2_LRN_CNT_CTRL15    0x0a96
#define    RTL8370_L2_LRN_CNT_CTRL15_OFFSET    0
#define    RTL8370_L2_LRN_CNT_CTRL15_MASK    0x3FFF

/* (16'h0b00) mltvlan_reg */

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY0_CTRL0    0x0b00
#define    RTL8370_SVLAN_MCAST2S_ENTRY0_CTRL0_VALID_OFFSET    7
#define    RTL8370_SVLAN_MCAST2S_ENTRY0_CTRL0_VALID_MASK    0x80
#define    RTL8370_SVLAN_MCAST2S_ENTRY0_CTRL0_FORMAT_OFFSET    6
#define    RTL8370_SVLAN_MCAST2S_ENTRY0_CTRL0_FORMAT_MASK    0x40
#define    RTL8370_SVLAN_MCAST2S_ENTRY0_CTRL0_SVIDX_OFFSET    0
#define    RTL8370_SVLAN_MCAST2S_ENTRY0_CTRL0_SVIDX_MASK    0x3F

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY0_CTRL1    0x0b01

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY0_CTRL2    0x0b02

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY0_CTRL3    0x0b03

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY0_CTRL4    0x0b04

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY1_CTRL0    0x0b05
#define    RTL8370_SVLAN_MCAST2S_ENTRY1_CTRL0_VALID_OFFSET    7
#define    RTL8370_SVLAN_MCAST2S_ENTRY1_CTRL0_VALID_MASK    0x80
#define    RTL8370_SVLAN_MCAST2S_ENTRY1_CTRL0_FORMAT_OFFSET    6
#define    RTL8370_SVLAN_MCAST2S_ENTRY1_CTRL0_FORMAT_MASK    0x40
#define    RTL8370_SVLAN_MCAST2S_ENTRY1_CTRL0_SVIDX_OFFSET    0
#define    RTL8370_SVLAN_MCAST2S_ENTRY1_CTRL0_SVIDX_MASK    0x3F

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY1_CTRL1    0x0b06

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY1_CTRL2    0x0b07

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY1_CTRL3    0x0b08

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY1_CTRL4    0x0b09

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY2_CTRL0    0x0b0a
#define    RTL8370_SVLAN_MCAST2S_ENTRY2_CTRL0_VALID_OFFSET    7
#define    RTL8370_SVLAN_MCAST2S_ENTRY2_CTRL0_VALID_MASK    0x80
#define    RTL8370_SVLAN_MCAST2S_ENTRY2_CTRL0_FORMAT_OFFSET    6
#define    RTL8370_SVLAN_MCAST2S_ENTRY2_CTRL0_FORMAT_MASK    0x40
#define    RTL8370_SVLAN_MCAST2S_ENTRY2_CTRL0_SVIDX_OFFSET    0
#define    RTL8370_SVLAN_MCAST2S_ENTRY2_CTRL0_SVIDX_MASK    0x3F

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY2_CTRL1    0x0b0b

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY2_CTRL2    0x0b0c

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY2_CTRL3    0x0b0d

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY2_CTRL4    0x0b0e

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY3_CTRL0    0x0b0f
#define    RTL8370_SVLAN_MCAST2S_ENTRY3_CTRL0_VALID_OFFSET    7
#define    RTL8370_SVLAN_MCAST2S_ENTRY3_CTRL0_VALID_MASK    0x80
#define    RTL8370_SVLAN_MCAST2S_ENTRY3_CTRL0_FORMAT_OFFSET    6
#define    RTL8370_SVLAN_MCAST2S_ENTRY3_CTRL0_FORMAT_MASK    0x40
#define    RTL8370_SVLAN_MCAST2S_ENTRY3_CTRL0_SVIDX_OFFSET    0
#define    RTL8370_SVLAN_MCAST2S_ENTRY3_CTRL0_SVIDX_MASK    0x3F

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY3_CTRL1    0x0b10

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY3_CTRL2    0x0b11

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY3_CTRL3    0x0b12

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY3_CTRL4    0x0b13

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY4_CTRL0    0x0b14
#define    RTL8370_SVLAN_MCAST2S_ENTRY4_CTRL0_VALID_OFFSET    7
#define    RTL8370_SVLAN_MCAST2S_ENTRY4_CTRL0_VALID_MASK    0x80
#define    RTL8370_SVLAN_MCAST2S_ENTRY4_CTRL0_FORMAT_OFFSET    6
#define    RTL8370_SVLAN_MCAST2S_ENTRY4_CTRL0_FORMAT_MASK    0x40
#define    RTL8370_SVLAN_MCAST2S_ENTRY4_CTRL0_SVIDX_OFFSET    0
#define    RTL8370_SVLAN_MCAST2S_ENTRY4_CTRL0_SVIDX_MASK    0x3F

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY4_CTRL1    0x0b15

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY4_CTRL2    0x0b16

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY4_CTRL3    0x0b17

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY4_CTRL4    0x0b18

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY5_CTRL0    0x0b19
#define    RTL8370_SVLAN_MCAST2S_ENTRY5_CTRL0_VALID_OFFSET    7
#define    RTL8370_SVLAN_MCAST2S_ENTRY5_CTRL0_VALID_MASK    0x80
#define    RTL8370_SVLAN_MCAST2S_ENTRY5_CTRL0_FORMAT_OFFSET    6
#define    RTL8370_SVLAN_MCAST2S_ENTRY5_CTRL0_FORMAT_MASK    0x40
#define    RTL8370_SVLAN_MCAST2S_ENTRY5_CTRL0_SVIDX_OFFSET    0
#define    RTL8370_SVLAN_MCAST2S_ENTRY5_CTRL0_SVIDX_MASK    0x3F

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY5_CTRL1    0x0b1a

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY5_CTRL2    0x0b1b

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY5_CTRL3    0x0b1c

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY5_CTRL4    0x0b1d

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY6_CTRL0    0x0b1e
#define    RTL8370_SVLAN_MCAST2S_ENTRY6_CTRL0_VALID_OFFSET    7
#define    RTL8370_SVLAN_MCAST2S_ENTRY6_CTRL0_VALID_MASK    0x80
#define    RTL8370_SVLAN_MCAST2S_ENTRY6_CTRL0_FORMAT_OFFSET    6
#define    RTL8370_SVLAN_MCAST2S_ENTRY6_CTRL0_FORMAT_MASK    0x40
#define    RTL8370_SVLAN_MCAST2S_ENTRY6_CTRL0_SVIDX_OFFSET    0
#define    RTL8370_SVLAN_MCAST2S_ENTRY6_CTRL0_SVIDX_MASK    0x3F

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY6_CTRL1    0x0b1f

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY6_CTRL2    0x0b20

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY6_CTRL3    0x0b21

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY6_CTRL4    0x0b22

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY7_CTRL0    0x0b23
#define    RTL8370_SVLAN_MCAST2S_ENTRY7_CTRL0_VALID_OFFSET    7
#define    RTL8370_SVLAN_MCAST2S_ENTRY7_CTRL0_VALID_MASK    0x80
#define    RTL8370_SVLAN_MCAST2S_ENTRY7_CTRL0_FORMAT_OFFSET    6
#define    RTL8370_SVLAN_MCAST2S_ENTRY7_CTRL0_FORMAT_MASK    0x40
#define    RTL8370_SVLAN_MCAST2S_ENTRY7_CTRL0_SVIDX_OFFSET    0
#define    RTL8370_SVLAN_MCAST2S_ENTRY7_CTRL0_SVIDX_MASK    0x3F

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY7_CTRL1    0x0b24

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY7_CTRL2    0x0b25

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY7_CTRL3    0x0b26

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY7_CTRL4    0x0b27

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY8_CTRL0    0x0b28
#define    RTL8370_SVLAN_MCAST2S_ENTRY8_CTRL0_VALID_OFFSET    7
#define    RTL8370_SVLAN_MCAST2S_ENTRY8_CTRL0_VALID_MASK    0x80
#define    RTL8370_SVLAN_MCAST2S_ENTRY8_CTRL0_FORMAT_OFFSET    6
#define    RTL8370_SVLAN_MCAST2S_ENTRY8_CTRL0_FORMAT_MASK    0x40
#define    RTL8370_SVLAN_MCAST2S_ENTRY8_CTRL0_SVIDX_OFFSET    0
#define    RTL8370_SVLAN_MCAST2S_ENTRY8_CTRL0_SVIDX_MASK    0x3F

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY8_CTRL1    0x0b29

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY8_CTRL2    0x0b2a

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY8_CTRL3    0x0b2b

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY8_CTRL4    0x0b2c

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY9_CTRL0    0x0b2d
#define    RTL8370_SVLAN_MCAST2S_ENTRY9_CTRL0_VALID_OFFSET    7
#define    RTL8370_SVLAN_MCAST2S_ENTRY9_CTRL0_VALID_MASK    0x80
#define    RTL8370_SVLAN_MCAST2S_ENTRY9_CTRL0_FORMAT_OFFSET    6
#define    RTL8370_SVLAN_MCAST2S_ENTRY9_CTRL0_FORMAT_MASK    0x40
#define    RTL8370_SVLAN_MCAST2S_ENTRY9_CTRL0_SVIDX_OFFSET    0
#define    RTL8370_SVLAN_MCAST2S_ENTRY9_CTRL0_SVIDX_MASK    0x3F

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY9_CTRL1    0x0b2e

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY9_CTRL2    0x0b2f

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY9_CTRL3    0x0b30

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY9_CTRL4    0x0b31

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY10_CTRL0    0x0b32
#define    RTL8370_SVLAN_MCAST2S_ENTRY10_CTRL0_VALID_OFFSET    7
#define    RTL8370_SVLAN_MCAST2S_ENTRY10_CTRL0_VALID_MASK    0x80
#define    RTL8370_SVLAN_MCAST2S_ENTRY10_CTRL0_FORMAT_OFFSET    6
#define    RTL8370_SVLAN_MCAST2S_ENTRY10_CTRL0_FORMAT_MASK    0x40
#define    RTL8370_SVLAN_MCAST2S_ENTRY10_CTRL0_SVIDX_OFFSET    0
#define    RTL8370_SVLAN_MCAST2S_ENTRY10_CTRL0_SVIDX_MASK    0x3F

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY10_CTRL1    0x0b33

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY10_CTRL2    0x0b34

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY10_CTRL3    0x0b35

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY10_CTRL4    0x0b36

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY11_CTRL0    0x0b37
#define    RTL8370_SVLAN_MCAST2S_ENTRY11_CTRL0_VALID_OFFSET    7
#define    RTL8370_SVLAN_MCAST2S_ENTRY11_CTRL0_VALID_MASK    0x80
#define    RTL8370_SVLAN_MCAST2S_ENTRY11_CTRL0_FORMAT_OFFSET    6
#define    RTL8370_SVLAN_MCAST2S_ENTRY11_CTRL0_FORMAT_MASK    0x40
#define    RTL8370_SVLAN_MCAST2S_ENTRY11_CTRL0_SVIDX_OFFSET    0
#define    RTL8370_SVLAN_MCAST2S_ENTRY11_CTRL0_SVIDX_MASK    0x3F

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY11_CTRL1    0x0b38

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY11_CTRL2    0x0b39

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY11_CTRL3    0x0b3a

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY11_CTRL4    0x0b3b

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY12_CTRL0    0x0b3c
#define    RTL8370_SVLAN_MCAST2S_ENTRY12_CTRL0_VALID_OFFSET    7
#define    RTL8370_SVLAN_MCAST2S_ENTRY12_CTRL0_VALID_MASK    0x80
#define    RTL8370_SVLAN_MCAST2S_ENTRY12_CTRL0_FORMAT_OFFSET    6
#define    RTL8370_SVLAN_MCAST2S_ENTRY12_CTRL0_FORMAT_MASK    0x40
#define    RTL8370_SVLAN_MCAST2S_ENTRY12_CTRL0_SVIDX_OFFSET    0
#define    RTL8370_SVLAN_MCAST2S_ENTRY12_CTRL0_SVIDX_MASK    0x3F

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY12_CTRL1    0x0b3d

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY12_CTRL2    0x0b3e

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY12_CTRL3    0x0b3f

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY12_CTRL4    0x0b40

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY13_CTRL0    0x0b41
#define    RTL8370_SVLAN_MCAST2S_ENTRY13_CTRL0_VALID_OFFSET    7
#define    RTL8370_SVLAN_MCAST2S_ENTRY13_CTRL0_VALID_MASK    0x80
#define    RTL8370_SVLAN_MCAST2S_ENTRY13_CTRL0_FORMAT_OFFSET    6
#define    RTL8370_SVLAN_MCAST2S_ENTRY13_CTRL0_FORMAT_MASK    0x40
#define    RTL8370_SVLAN_MCAST2S_ENTRY13_CTRL0_SVIDX_OFFSET    0
#define    RTL8370_SVLAN_MCAST2S_ENTRY13_CTRL0_SVIDX_MASK    0x3F

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY13_CTRL1    0x0b42

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY13_CTRL2    0x0b43

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY13_CTRL3    0x0b44

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY13_CTRL4    0x0b45

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY14_CTRL0    0x0b46
#define    RTL8370_SVLAN_MCAST2S_ENTRY14_CTRL0_VALID_OFFSET    7
#define    RTL8370_SVLAN_MCAST2S_ENTRY14_CTRL0_VALID_MASK    0x80
#define    RTL8370_SVLAN_MCAST2S_ENTRY14_CTRL0_FORMAT_OFFSET    6
#define    RTL8370_SVLAN_MCAST2S_ENTRY14_CTRL0_FORMAT_MASK    0x40
#define    RTL8370_SVLAN_MCAST2S_ENTRY14_CTRL0_SVIDX_OFFSET    0
#define    RTL8370_SVLAN_MCAST2S_ENTRY14_CTRL0_SVIDX_MASK    0x3F

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY14_CTRL1    0x0b47

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY14_CTRL2    0x0b48

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY14_CTRL3    0x0b49

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY14_CTRL4    0x0b4a

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY15_CTRL0    0x0b4b
#define    RTL8370_SVLAN_MCAST2S_ENTRY15_CTRL0_VALID_OFFSET    7
#define    RTL8370_SVLAN_MCAST2S_ENTRY15_CTRL0_VALID_MASK    0x80
#define    RTL8370_SVLAN_MCAST2S_ENTRY15_CTRL0_FORMAT_OFFSET    6
#define    RTL8370_SVLAN_MCAST2S_ENTRY15_CTRL0_FORMAT_MASK    0x40
#define    RTL8370_SVLAN_MCAST2S_ENTRY15_CTRL0_SVIDX_OFFSET    0
#define    RTL8370_SVLAN_MCAST2S_ENTRY15_CTRL0_SVIDX_MASK    0x3F

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY15_CTRL1    0x0b4c

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY15_CTRL2    0x0b4d

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY15_CTRL3    0x0b4e

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY15_CTRL4    0x0b4f

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY16_CTRL0    0x0b50
#define    RTL8370_SVLAN_MCAST2S_ENTRY16_CTRL0_VALID_OFFSET    7
#define    RTL8370_SVLAN_MCAST2S_ENTRY16_CTRL0_VALID_MASK    0x80
#define    RTL8370_SVLAN_MCAST2S_ENTRY16_CTRL0_FORMAT_OFFSET    6
#define    RTL8370_SVLAN_MCAST2S_ENTRY16_CTRL0_FORMAT_MASK    0x40
#define    RTL8370_SVLAN_MCAST2S_ENTRY16_CTRL0_SVIDX_OFFSET    0
#define    RTL8370_SVLAN_MCAST2S_ENTRY16_CTRL0_SVIDX_MASK    0x3F

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY16_CTRL1    0x0b51

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY16_CTRL2    0x0b52

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY16_CTRL3    0x0b53

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY16_CTRL4    0x0b54

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY17_CTRL0    0x0b55
#define    RTL8370_SVLAN_MCAST2S_ENTRY17_CTRL0_VALID_OFFSET    7
#define    RTL8370_SVLAN_MCAST2S_ENTRY17_CTRL0_VALID_MASK    0x80
#define    RTL8370_SVLAN_MCAST2S_ENTRY17_CTRL0_FORMAT_OFFSET    6
#define    RTL8370_SVLAN_MCAST2S_ENTRY17_CTRL0_FORMAT_MASK    0x40
#define    RTL8370_SVLAN_MCAST2S_ENTRY17_CTRL0_SVIDX_OFFSET    0
#define    RTL8370_SVLAN_MCAST2S_ENTRY17_CTRL0_SVIDX_MASK    0x3F

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY17_CTRL1    0x0b56

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY17_CTRL2    0x0b57

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY17_CTRL3    0x0b58

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY17_CTRL4    0x0b59

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY18_CTRL0    0x0b5a
#define    RTL8370_SVLAN_MCAST2S_ENTRY18_CTRL0_VALID_OFFSET    7
#define    RTL8370_SVLAN_MCAST2S_ENTRY18_CTRL0_VALID_MASK    0x80
#define    RTL8370_SVLAN_MCAST2S_ENTRY18_CTRL0_FORMAT_OFFSET    6
#define    RTL8370_SVLAN_MCAST2S_ENTRY18_CTRL0_FORMAT_MASK    0x40
#define    RTL8370_SVLAN_MCAST2S_ENTRY18_CTRL0_SVIDX_OFFSET    0
#define    RTL8370_SVLAN_MCAST2S_ENTRY18_CTRL0_SVIDX_MASK    0x3F

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY18_CTRL1    0x0b5b

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY18_CTRL2    0x0b5c

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY18_CTRL3    0x0b5d

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY18_CTRL4    0x0b5e

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY19_CTRL0    0x0b5f
#define    RTL8370_SVLAN_MCAST2S_ENTRY19_CTRL0_VALID_OFFSET    7
#define    RTL8370_SVLAN_MCAST2S_ENTRY19_CTRL0_VALID_MASK    0x80
#define    RTL8370_SVLAN_MCAST2S_ENTRY19_CTRL0_FORMAT_OFFSET    6
#define    RTL8370_SVLAN_MCAST2S_ENTRY19_CTRL0_FORMAT_MASK    0x40
#define    RTL8370_SVLAN_MCAST2S_ENTRY19_CTRL0_SVIDX_OFFSET    0
#define    RTL8370_SVLAN_MCAST2S_ENTRY19_CTRL0_SVIDX_MASK    0x3F

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY19_CTRL1    0x0b60

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY19_CTRL2    0x0b61

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY19_CTRL3    0x0b62

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY19_CTRL4    0x0b63

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY20_CTRL0    0x0b64
#define    RTL8370_SVLAN_MCAST2S_ENTRY20_CTRL0_VALID_OFFSET    7
#define    RTL8370_SVLAN_MCAST2S_ENTRY20_CTRL0_VALID_MASK    0x80
#define    RTL8370_SVLAN_MCAST2S_ENTRY20_CTRL0_FORMAT_OFFSET    6
#define    RTL8370_SVLAN_MCAST2S_ENTRY20_CTRL0_FORMAT_MASK    0x40
#define    RTL8370_SVLAN_MCAST2S_ENTRY20_CTRL0_SVIDX_OFFSET    0
#define    RTL8370_SVLAN_MCAST2S_ENTRY20_CTRL0_SVIDX_MASK    0x3F

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY20_CTRL1    0x0b65

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY20_CTRL2    0x0b66

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY20_CTRL3    0x0b67

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY20_CTRL4    0x0b68

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY21_CTRL0    0x0b69
#define    RTL8370_SVLAN_MCAST2S_ENTRY21_CTRL0_VALID_OFFSET    7
#define    RTL8370_SVLAN_MCAST2S_ENTRY21_CTRL0_VALID_MASK    0x80
#define    RTL8370_SVLAN_MCAST2S_ENTRY21_CTRL0_FORMAT_OFFSET    6
#define    RTL8370_SVLAN_MCAST2S_ENTRY21_CTRL0_FORMAT_MASK    0x40
#define    RTL8370_SVLAN_MCAST2S_ENTRY21_CTRL0_SVIDX_OFFSET    0
#define    RTL8370_SVLAN_MCAST2S_ENTRY21_CTRL0_SVIDX_MASK    0x3F

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY21_CTRL1    0x0b6a

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY21_CTRL2    0x0b6b

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY21_CTRL3    0x0b6c

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY21_CTRL4    0x0b6d

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY22_CTRL0    0x0b6e
#define    RTL8370_SVLAN_MCAST2S_ENTRY22_CTRL0_VALID_OFFSET    7
#define    RTL8370_SVLAN_MCAST2S_ENTRY22_CTRL0_VALID_MASK    0x80
#define    RTL8370_SVLAN_MCAST2S_ENTRY22_CTRL0_FORMAT_OFFSET    6
#define    RTL8370_SVLAN_MCAST2S_ENTRY22_CTRL0_FORMAT_MASK    0x40
#define    RTL8370_SVLAN_MCAST2S_ENTRY22_CTRL0_SVIDX_OFFSET    0
#define    RTL8370_SVLAN_MCAST2S_ENTRY22_CTRL0_SVIDX_MASK    0x3F

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY22_CTRL1    0x0b6f

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY22_CTRL2    0x0b70

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY22_CTRL3    0x0b71

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY22_CTRL4    0x0b72

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY23_CTRL0    0x0b73
#define    RTL8370_SVLAN_MCAST2S_ENTRY23_CTRL0_VALID_OFFSET    7
#define    RTL8370_SVLAN_MCAST2S_ENTRY23_CTRL0_VALID_MASK    0x80
#define    RTL8370_SVLAN_MCAST2S_ENTRY23_CTRL0_FORMAT_OFFSET    6
#define    RTL8370_SVLAN_MCAST2S_ENTRY23_CTRL0_FORMAT_MASK    0x40
#define    RTL8370_SVLAN_MCAST2S_ENTRY23_CTRL0_SVIDX_OFFSET    0
#define    RTL8370_SVLAN_MCAST2S_ENTRY23_CTRL0_SVIDX_MASK    0x3F

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY23_CTRL1    0x0b74

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY23_CTRL2    0x0b75

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY23_CTRL3    0x0b76

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY23_CTRL4    0x0b77

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY24_CTRL0    0x0b78
#define    RTL8370_SVLAN_MCAST2S_ENTRY24_CTRL0_VALID_OFFSET    7
#define    RTL8370_SVLAN_MCAST2S_ENTRY24_CTRL0_VALID_MASK    0x80
#define    RTL8370_SVLAN_MCAST2S_ENTRY24_CTRL0_FORMAT_OFFSET    6
#define    RTL8370_SVLAN_MCAST2S_ENTRY24_CTRL0_FORMAT_MASK    0x40
#define    RTL8370_SVLAN_MCAST2S_ENTRY24_CTRL0_SVIDX_OFFSET    0
#define    RTL8370_SVLAN_MCAST2S_ENTRY24_CTRL0_SVIDX_MASK    0x3F

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY24_CTRL1    0x0b79

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY24_CTRL2    0x0b7a

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY24_CTRL3    0x0b7b

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY24_CTRL4    0x0b7c

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY25_CTRL0    0x0b7d
#define    RTL8370_SVLAN_MCAST2S_ENTRY25_CTRL0_VALID_OFFSET    7
#define    RTL8370_SVLAN_MCAST2S_ENTRY25_CTRL0_VALID_MASK    0x80
#define    RTL8370_SVLAN_MCAST2S_ENTRY25_CTRL0_FORMAT_OFFSET    6
#define    RTL8370_SVLAN_MCAST2S_ENTRY25_CTRL0_FORMAT_MASK    0x40
#define    RTL8370_SVLAN_MCAST2S_ENTRY25_CTRL0_SVIDX_OFFSET    0
#define    RTL8370_SVLAN_MCAST2S_ENTRY25_CTRL0_SVIDX_MASK    0x3F

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY25_CTRL1    0x0b7e

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY25_CTRL2    0x0b7f

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY25_CTRL3    0x0b80

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY25_CTRL4    0x0b81

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY26_CTRL0    0x0b82
#define    RTL8370_SVLAN_MCAST2S_ENTRY26_CTRL0_VALID_OFFSET    7
#define    RTL8370_SVLAN_MCAST2S_ENTRY26_CTRL0_VALID_MASK    0x80
#define    RTL8370_SVLAN_MCAST2S_ENTRY26_CTRL0_FORMAT_OFFSET    6
#define    RTL8370_SVLAN_MCAST2S_ENTRY26_CTRL0_FORMAT_MASK    0x40
#define    RTL8370_SVLAN_MCAST2S_ENTRY26_CTRL0_SVIDX_OFFSET    0
#define    RTL8370_SVLAN_MCAST2S_ENTRY26_CTRL0_SVIDX_MASK    0x3F

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY26_CTRL1    0x0b83

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY26_CTRL2    0x0b84

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY26_CTRL3    0x0b85

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY26_CTRL4    0x0b86

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY27_CTRL0    0x0b87
#define    RTL8370_SVLAN_MCAST2S_ENTRY27_CTRL0_VALID_OFFSET    7
#define    RTL8370_SVLAN_MCAST2S_ENTRY27_CTRL0_VALID_MASK    0x80
#define    RTL8370_SVLAN_MCAST2S_ENTRY27_CTRL0_FORMAT_OFFSET    6
#define    RTL8370_SVLAN_MCAST2S_ENTRY27_CTRL0_FORMAT_MASK    0x40
#define    RTL8370_SVLAN_MCAST2S_ENTRY27_CTRL0_SVIDX_OFFSET    0
#define    RTL8370_SVLAN_MCAST2S_ENTRY27_CTRL0_SVIDX_MASK    0x3F

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY27_CTRL1    0x0b88

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY27_CTRL2    0x0b89

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY27_CTRL3    0x0b8a

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY27_CTRL4    0x0b8b

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY28_CTRL0    0x0b8c
#define    RTL8370_SVLAN_MCAST2S_ENTRY28_CTRL0_VALID_OFFSET    7
#define    RTL8370_SVLAN_MCAST2S_ENTRY28_CTRL0_VALID_MASK    0x80
#define    RTL8370_SVLAN_MCAST2S_ENTRY28_CTRL0_FORMAT_OFFSET    6
#define    RTL8370_SVLAN_MCAST2S_ENTRY28_CTRL0_FORMAT_MASK    0x40
#define    RTL8370_SVLAN_MCAST2S_ENTRY28_CTRL0_SVIDX_OFFSET    0
#define    RTL8370_SVLAN_MCAST2S_ENTRY28_CTRL0_SVIDX_MASK    0x3F

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY28_CTRL1    0x0b8d

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY28_CTRL2    0x0b8e

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY28_CTRL3    0x0b8f

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY28_CTRL4    0x0b90

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY29_CTRL0    0x0b91
#define    RTL8370_SVLAN_MCAST2S_ENTRY29_CTRL0_VALID_OFFSET    7
#define    RTL8370_SVLAN_MCAST2S_ENTRY29_CTRL0_VALID_MASK    0x80
#define    RTL8370_SVLAN_MCAST2S_ENTRY29_CTRL0_FORMAT_OFFSET    6
#define    RTL8370_SVLAN_MCAST2S_ENTRY29_CTRL0_FORMAT_MASK    0x40
#define    RTL8370_SVLAN_MCAST2S_ENTRY29_CTRL0_SVIDX_OFFSET    0
#define    RTL8370_SVLAN_MCAST2S_ENTRY29_CTRL0_SVIDX_MASK    0x3F

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY29_CTRL1    0x0b92

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY29_CTRL2    0x0b93

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY29_CTRL3    0x0b94

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY29_CTRL4    0x0b95

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY30_CTRL0    0x0b96
#define    RTL8370_SVLAN_MCAST2S_ENTRY30_CTRL0_VALID_OFFSET    7
#define    RTL8370_SVLAN_MCAST2S_ENTRY30_CTRL0_VALID_MASK    0x80
#define    RTL8370_SVLAN_MCAST2S_ENTRY30_CTRL0_FORMAT_OFFSET    6
#define    RTL8370_SVLAN_MCAST2S_ENTRY30_CTRL0_FORMAT_MASK    0x40
#define    RTL8370_SVLAN_MCAST2S_ENTRY30_CTRL0_SVIDX_OFFSET    0
#define    RTL8370_SVLAN_MCAST2S_ENTRY30_CTRL0_SVIDX_MASK    0x3F

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY30_CTRL1    0x0b97

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY30_CTRL2    0x0b98

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY30_CTRL3    0x0b99

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY30_CTRL4    0x0b9a

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY31_CTRL0    0x0b9b
#define    RTL8370_SVLAN_MCAST2S_ENTRY31_CTRL0_VALID_OFFSET    7
#define    RTL8370_SVLAN_MCAST2S_ENTRY31_CTRL0_VALID_MASK    0x80
#define    RTL8370_SVLAN_MCAST2S_ENTRY31_CTRL0_FORMAT_OFFSET    6
#define    RTL8370_SVLAN_MCAST2S_ENTRY31_CTRL0_FORMAT_MASK    0x40
#define    RTL8370_SVLAN_MCAST2S_ENTRY31_CTRL0_SVIDX_OFFSET    0
#define    RTL8370_SVLAN_MCAST2S_ENTRY31_CTRL0_SVIDX_MASK    0x3F

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY31_CTRL1    0x0b9c

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY31_CTRL2    0x0b9d

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY31_CTRL3    0x0b9e

#define    RTL8370_REG_SVLAN_MCAST2S_ENTRY31_CTRL4    0x0b9f

/* (16'h0c00) svlan_reg */

#define    RTL8370_REG_SVLAN_MEMBERCFG0_CTRL0    0x0c00
#define    RTL8370_SVLAN_MEMBERCFG0_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG0_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG0_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG0_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG0_CTRL1    0x0c01

#define    RTL8370_REG_SVLAN_MEMBERCFG0_CTRL2    0x0c02
#define    RTL8370_SVLAN_MEMBERCFG0_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG0_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG0_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG0_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG0_CTRL3    0x0c03
#define    RTL8370_SVLAN_MEMBERCFG0_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG0_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG0_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG0_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG0_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG0_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG1_CTRL0    0x0c04
#define    RTL8370_SVLAN_MEMBERCFG1_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG1_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG1_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG1_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG1_CTRL1    0x0c05

#define    RTL8370_REG_SVLAN_MEMBERCFG1_CTRL2    0x0c06
#define    RTL8370_SVLAN_MEMBERCFG1_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG1_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG1_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG1_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG1_CTRL3    0x0c07
#define    RTL8370_SVLAN_MEMBERCFG1_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG1_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG1_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG1_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG1_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG1_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG2_CTRL0    0x0c08
#define    RTL8370_SVLAN_MEMBERCFG2_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG2_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG2_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG2_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG2_CTRL1    0x0c09

#define    RTL8370_REG_SVLAN_MEMBERCFG2_CTRL2    0x0c0a
#define    RTL8370_SVLAN_MEMBERCFG2_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG2_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG2_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG2_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG2_CTRL3    0x0c0b
#define    RTL8370_SVLAN_MEMBERCFG2_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG2_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG2_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG2_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG2_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG2_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG3_CTRL0    0x0c0c
#define    RTL8370_SVLAN_MEMBERCFG3_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG3_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG3_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG3_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG3_CTRL1    0x0c0d

#define    RTL8370_REG_SVLAN_MEMBERCFG3_CTRL2    0x0c0e
#define    RTL8370_SVLAN_MEMBERCFG3_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG3_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG3_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG3_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG3_CTRL3    0x0c0f
#define    RTL8370_SVLAN_MEMBERCFG3_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG3_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG3_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG3_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG3_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG3_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG4_CTRL0    0x0c10
#define    RTL8370_SVLAN_MEMBERCFG4_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG4_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG4_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG4_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG4_CTRL1    0x0c11

#define    RTL8370_REG_SVLAN_MEMBERCFG4_CTRL2    0x0c12
#define    RTL8370_SVLAN_MEMBERCFG4_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG4_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG4_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG4_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG4_CTRL3    0x0c13
#define    RTL8370_SVLAN_MEMBERCFG4_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG4_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG4_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG4_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG4_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG4_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG5_CTRL0    0x0c14
#define    RTL8370_SVLAN_MEMBERCFG5_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG5_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG5_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG5_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG5_CTRL1    0x0c15

#define    RTL8370_REG_SVLAN_MEMBERCFG5_CTRL2    0x0c16
#define    RTL8370_SVLAN_MEMBERCFG5_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG5_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG5_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG5_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG5_CTRL3    0x0c17
#define    RTL8370_SVLAN_MEMBERCFG5_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG5_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG5_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG5_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG5_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG5_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG6_CTRL0    0x0c18
#define    RTL8370_SVLAN_MEMBERCFG6_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG6_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG6_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG6_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG6_CTRL1    0x0c19

#define    RTL8370_REG_SVLAN_MEMBERCFG6_CTRL2    0x0c1a
#define    RTL8370_SVLAN_MEMBERCFG6_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG6_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG6_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG6_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG6_CTRL3    0x0c1b
#define    RTL8370_SVLAN_MEMBERCFG6_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG6_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG6_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG6_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG6_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG6_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG7_CTRL0    0x0c1c
#define    RTL8370_SVLAN_MEMBERCFG7_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG7_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG7_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG7_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG7_CTRL1    0x0c1d

#define    RTL8370_REG_SVLAN_MEMBERCFG7_CTRL2    0x0c1e
#define    RTL8370_SVLAN_MEMBERCFG7_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG7_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG7_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG7_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG7_CTRL3    0x0c1f
#define    RTL8370_SVLAN_MEMBERCFG7_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG7_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG7_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG7_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG7_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG7_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG8_CTRL0    0x0c20
#define    RTL8370_SVLAN_MEMBERCFG8_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG8_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG8_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG8_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG8_CTRL1    0x0c21

#define    RTL8370_REG_SVLAN_MEMBERCFG8_CTRL2    0x0c22
#define    RTL8370_SVLAN_MEMBERCFG8_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG8_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG8_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG8_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG8_CTRL3    0x0c23
#define    RTL8370_SVLAN_MEMBERCFG8_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG8_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG8_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG8_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG8_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG8_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG9_CTRL0    0x0c24
#define    RTL8370_SVLAN_MEMBERCFG9_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG9_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG9_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG9_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG9_CTRL1    0x0c25

#define    RTL8370_REG_SVLAN_MEMBERCFG9_CTRL2    0x0c26
#define    RTL8370_SVLAN_MEMBERCFG9_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG9_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG9_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG9_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG9_CTRL3    0x0c27
#define    RTL8370_SVLAN_MEMBERCFG9_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG9_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG9_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG9_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG9_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG9_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG10_CTRL0    0x0c28
#define    RTL8370_SVLAN_MEMBERCFG10_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG10_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG10_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG10_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG10_CTRL1    0x0c29

#define    RTL8370_REG_SVLAN_MEMBERCFG10_CTRL2    0x0c2a
#define    RTL8370_SVLAN_MEMBERCFG10_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG10_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG10_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG10_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG10_CTRL3    0x0c2b
#define    RTL8370_SVLAN_MEMBERCFG10_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG10_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG10_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG10_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG10_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG10_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG11_CTRL0    0x0c2c
#define    RTL8370_SVLAN_MEMBERCFG11_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG11_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG11_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG11_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG11_CTRL1    0x0c2d

#define    RTL8370_REG_SVLAN_MEMBERCFG11_CTRL2    0x0c2e
#define    RTL8370_SVLAN_MEMBERCFG11_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG11_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG11_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG11_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG11_CTRL3    0x0c2f
#define    RTL8370_SVLAN_MEMBERCFG11_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG11_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG11_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG11_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG11_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG11_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG12_CTRL0    0x0c30
#define    RTL8370_SVLAN_MEMBERCFG12_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG12_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG12_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG12_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG12_CTRL1    0x0c31

#define    RTL8370_REG_SVLAN_MEMBERCFG12_CTRL2    0x0c32
#define    RTL8370_SVLAN_MEMBERCFG12_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG12_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG12_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG12_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG12_CTRL3    0x0c33
#define    RTL8370_SVLAN_MEMBERCFG12_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG12_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG12_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG12_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG12_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG12_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG13_CTRL0    0x0c34
#define    RTL8370_SVLAN_MEMBERCFG13_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG13_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG13_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG13_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG13_CTRL1    0x0c35

#define    RTL8370_REG_SVLAN_MEMBERCFG13_CTRL2    0x0c36
#define    RTL8370_SVLAN_MEMBERCFG13_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG13_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG13_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG13_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG13_CTRL3    0x0c37
#define    RTL8370_SVLAN_MEMBERCFG13_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG13_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG13_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG13_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG13_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG13_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG14_CTRL0    0x0c38
#define    RTL8370_SVLAN_MEMBERCFG14_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG14_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG14_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG14_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG14_CTRL1    0x0c39

#define    RTL8370_REG_SVLAN_MEMBERCFG14_CTRL2    0x0c3a
#define    RTL8370_SVLAN_MEMBERCFG14_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG14_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG14_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG14_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG14_CTRL3    0x0c3b
#define    RTL8370_SVLAN_MEMBERCFG14_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG14_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG14_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG14_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG14_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG14_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG15_CTRL0    0x0c3c
#define    RTL8370_SVLAN_MEMBERCFG15_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG15_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG15_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG15_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG15_CTRL1    0x0c3d

#define    RTL8370_REG_SVLAN_MEMBERCFG15_CTRL2    0x0c3e
#define    RTL8370_SVLAN_MEMBERCFG15_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG15_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG15_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG15_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG15_CTRL3    0x0c3f
#define    RTL8370_SVLAN_MEMBERCFG15_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG15_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG15_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG15_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG15_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG15_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG16_CTRL0    0x0c40
#define    RTL8370_SVLAN_MEMBERCFG16_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG16_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG16_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG16_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG16_CTRL1    0x0c41

#define    RTL8370_REG_SVLAN_MEMBERCFG16_CTRL2    0x0c42
#define    RTL8370_SVLAN_MEMBERCFG16_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG16_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG16_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG16_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG16_CTRL3    0x0c43
#define    RTL8370_SVLAN_MEMBERCFG16_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG16_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG16_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG16_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG16_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG16_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG17_CTRL0    0x0c44
#define    RTL8370_SVLAN_MEMBERCFG17_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG17_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG17_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG17_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG17_CTRL1    0x0c45

#define    RTL8370_REG_SVLAN_MEMBERCFG17_CTRL2    0x0c46
#define    RTL8370_SVLAN_MEMBERCFG17_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG17_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG17_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG17_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG17_CTRL3    0x0c47
#define    RTL8370_SVLAN_MEMBERCFG17_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG17_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG17_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG17_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG17_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG17_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG18_CTRL0    0x0c48
#define    RTL8370_SVLAN_MEMBERCFG18_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG18_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG18_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG18_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG18_CTRL1    0x0c49

#define    RTL8370_REG_SVLAN_MEMBERCFG18_CTRL2    0x0c4a
#define    RTL8370_SVLAN_MEMBERCFG18_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG18_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG18_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG18_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG18_CTRL3    0x0c4b
#define    RTL8370_SVLAN_MEMBERCFG18_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG18_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG18_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG18_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG18_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG18_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG19_CTRL0    0x0c4c
#define    RTL8370_SVLAN_MEMBERCFG19_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG19_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG19_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG19_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG19_CTRL1    0x0c4d

#define    RTL8370_REG_SVLAN_MEMBERCFG19_CTRL2    0x0c4e
#define    RTL8370_SVLAN_MEMBERCFG19_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG19_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG19_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG19_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG19_CTRL3    0x0c4f
#define    RTL8370_SVLAN_MEMBERCFG19_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG19_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG19_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG19_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG19_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG19_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG20_CTRL0    0x0c50
#define    RTL8370_SVLAN_MEMBERCFG20_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG20_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG20_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG20_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG20_CTRL1    0x0c51

#define    RTL8370_REG_SVLAN_MEMBERCFG20_CTRL2    0x0c52
#define    RTL8370_SVLAN_MEMBERCFG20_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG20_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG20_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG20_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG20_CTRL3    0x0c53
#define    RTL8370_SVLAN_MEMBERCFG20_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG20_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG20_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG20_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG20_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG20_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG21_CTRL0    0x0c54
#define    RTL8370_SVLAN_MEMBERCFG21_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG21_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG21_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG21_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG21_CTRL1    0x0c55

#define    RTL8370_REG_SVLAN_MEMBERCFG21_CTRL2    0x0c56
#define    RTL8370_SVLAN_MEMBERCFG21_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG21_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG21_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG21_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG21_CTRL3    0x0c57
#define    RTL8370_SVLAN_MEMBERCFG21_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG21_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG21_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG21_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG21_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG21_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG22_CTRL0    0x0c58
#define    RTL8370_SVLAN_MEMBERCFG22_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG22_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG22_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG22_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG22_CTRL1    0x0c59

#define    RTL8370_REG_SVLAN_MEMBERCFG22_CTRL2    0x0c5a
#define    RTL8370_SVLAN_MEMBERCFG22_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG22_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG22_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG22_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG22_CTRL3    0x0c5b
#define    RTL8370_SVLAN_MEMBERCFG22_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG22_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG22_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG22_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG22_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG22_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG23_CTRL0    0x0c5c
#define    RTL8370_SVLAN_MEMBERCFG23_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG23_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG23_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG23_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG23_CTRL1    0x0c5d

#define    RTL8370_REG_SVLAN_MEMBERCFG23_CTRL2    0x0c5e
#define    RTL8370_SVLAN_MEMBERCFG23_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG23_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG23_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG23_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG23_CTRL3    0x0c5f
#define    RTL8370_SVLAN_MEMBERCFG23_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG23_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG23_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG23_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG23_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG23_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG24_CTRL0    0x0c60
#define    RTL8370_SVLAN_MEMBERCFG24_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG24_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG24_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG24_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG24_CTRL1    0x0c61

#define    RTL8370_REG_SVLAN_MEMBERCFG24_CTRL2    0x0c62
#define    RTL8370_SVLAN_MEMBERCFG24_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG24_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG24_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG24_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG24_CTRL3    0x0c63
#define    RTL8370_SVLAN_MEMBERCFG24_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG24_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG24_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG24_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG24_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG24_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG25_CTRL0    0x0c64
#define    RTL8370_SVLAN_MEMBERCFG25_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG25_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG25_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG25_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG25_CTRL1    0x0c65

#define    RTL8370_REG_SVLAN_MEMBERCFG25_CTRL2    0x0c66
#define    RTL8370_SVLAN_MEMBERCFG25_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG25_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG25_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG25_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG25_CTRL3    0x0c67
#define    RTL8370_SVLAN_MEMBERCFG25_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG25_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG25_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG25_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG25_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG25_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG26_CTRL0    0x0c68
#define    RTL8370_SVLAN_MEMBERCFG26_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG26_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG26_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG26_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG26_CTRL1    0x0c69

#define    RTL8370_REG_SVLAN_MEMBERCFG26_CTRL2    0x0c6a
#define    RTL8370_SVLAN_MEMBERCFG26_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG26_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG26_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG26_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG26_CTRL3    0x0c6b
#define    RTL8370_SVLAN_MEMBERCFG26_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG26_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG26_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG26_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG26_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG26_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG27_CTRL0    0x0c6c
#define    RTL8370_SVLAN_MEMBERCFG27_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG27_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG27_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG27_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG27_CTRL1    0x0c6d

#define    RTL8370_REG_SVLAN_MEMBERCFG27_CTRL2    0x0c6e
#define    RTL8370_SVLAN_MEMBERCFG27_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG27_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG27_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG27_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG27_CTRL3    0x0c6f
#define    RTL8370_SVLAN_MEMBERCFG27_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG27_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG27_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG27_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG27_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG27_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG28_CTRL0    0x0c70
#define    RTL8370_SVLAN_MEMBERCFG28_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG28_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG28_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG28_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG28_CTRL1    0x0c71

#define    RTL8370_REG_SVLAN_MEMBERCFG28_CTRL2    0x0c72
#define    RTL8370_SVLAN_MEMBERCFG28_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG28_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG28_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG28_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG28_CTRL3    0x0c73
#define    RTL8370_SVLAN_MEMBERCFG28_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG28_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG28_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG28_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG28_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG28_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG29_CTRL0    0x0c74
#define    RTL8370_SVLAN_MEMBERCFG29_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG29_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG29_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG29_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG29_CTRL1    0x0c75

#define    RTL8370_REG_SVLAN_MEMBERCFG29_CTRL2    0x0c76
#define    RTL8370_SVLAN_MEMBERCFG29_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG29_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG29_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG29_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG29_CTRL3    0x0c77
#define    RTL8370_SVLAN_MEMBERCFG29_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG29_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG29_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG29_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG29_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG29_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG30_CTRL0    0x0c78
#define    RTL8370_SVLAN_MEMBERCFG30_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG30_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG30_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG30_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG30_CTRL1    0x0c79

#define    RTL8370_REG_SVLAN_MEMBERCFG30_CTRL2    0x0c7a
#define    RTL8370_SVLAN_MEMBERCFG30_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG30_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG30_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG30_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG30_CTRL3    0x0c7b
#define    RTL8370_SVLAN_MEMBERCFG30_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG30_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG30_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG30_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG30_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG30_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG31_CTRL0    0x0c7c
#define    RTL8370_SVLAN_MEMBERCFG31_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG31_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG31_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG31_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG31_CTRL1    0x0c7d

#define    RTL8370_REG_SVLAN_MEMBERCFG31_CTRL2    0x0c7e
#define    RTL8370_SVLAN_MEMBERCFG31_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG31_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG31_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG31_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG31_CTRL3    0x0c7f
#define    RTL8370_SVLAN_MEMBERCFG31_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG31_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG31_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG31_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG31_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG31_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG32_CTRL0    0x0c80
#define    RTL8370_SVLAN_MEMBERCFG32_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG32_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG32_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG32_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG32_CTRL1    0x0c81

#define    RTL8370_REG_SVLAN_MEMBERCFG32_CTRL2    0x0c82
#define    RTL8370_SVLAN_MEMBERCFG32_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG32_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG32_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG32_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG32_CTRL3    0x0c83
#define    RTL8370_SVLAN_MEMBERCFG32_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG32_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG32_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG32_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG32_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG32_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG33_CTRL0    0x0c84
#define    RTL8370_SVLAN_MEMBERCFG33_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG33_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG33_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG33_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG33_CTRL1    0x0c85

#define    RTL8370_REG_SVLAN_MEMBERCFG33_CTRL2    0x0c86
#define    RTL8370_SVLAN_MEMBERCFG33_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG33_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG33_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG33_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG33_CTRL3    0x0c87
#define    RTL8370_SVLAN_MEMBERCFG33_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG33_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG33_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG33_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG33_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG33_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG34_CTRL0    0x0c88
#define    RTL8370_SVLAN_MEMBERCFG34_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG34_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG34_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG34_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG34_CTRL1    0x0c89

#define    RTL8370_REG_SVLAN_MEMBERCFG34_CTRL2    0x0c8a
#define    RTL8370_SVLAN_MEMBERCFG34_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG34_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG34_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG34_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG34_CTRL3    0x0c8b
#define    RTL8370_SVLAN_MEMBERCFG34_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG34_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG34_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG34_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG34_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG34_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG35_CTRL0    0x0c8c
#define    RTL8370_SVLAN_MEMBERCFG35_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG35_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG35_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG35_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG35_CTRL1    0x0c8d

#define    RTL8370_REG_SVLAN_MEMBERCFG35_CTRL2    0x0c8e
#define    RTL8370_SVLAN_MEMBERCFG35_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG35_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG35_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG35_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG35_CTRL3    0x0c8f
#define    RTL8370_SVLAN_MEMBERCFG35_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG35_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG35_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG35_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG35_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG35_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG36_CTRL0    0x0c90
#define    RTL8370_SVLAN_MEMBERCFG36_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG36_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG36_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG36_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG36_CTRL1    0x0c91

#define    RTL8370_REG_SVLAN_MEMBERCFG36_CTRL2    0x0c92
#define    RTL8370_SVLAN_MEMBERCFG36_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG36_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG36_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG36_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG36_CTRL3    0x0c93
#define    RTL8370_SVLAN_MEMBERCFG36_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG36_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG36_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG36_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG36_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG36_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG37_CTRL0    0x0c94
#define    RTL8370_SVLAN_MEMBERCFG37_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG37_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG37_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG37_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG37_CTRL1    0x0c95

#define    RTL8370_REG_SVLAN_MEMBERCFG37_CTRL2    0x0c96
#define    RTL8370_SVLAN_MEMBERCFG37_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG37_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG37_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG37_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG37_CTRL3    0x0c97
#define    RTL8370_SVLAN_MEMBERCFG37_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG37_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG37_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG37_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG37_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG37_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG38_CTRL0    0x0c98
#define    RTL8370_SVLAN_MEMBERCFG38_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG38_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG38_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG38_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG38_CTRL1    0x0c99

#define    RTL8370_REG_SVLAN_MEMBERCFG38_CTRL2    0x0c9a
#define    RTL8370_SVLAN_MEMBERCFG38_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG38_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG38_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG38_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG38_CTRL3    0x0c9b
#define    RTL8370_SVLAN_MEMBERCFG38_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG38_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG38_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG38_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG38_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG38_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG39_CTRL0    0x0c9c
#define    RTL8370_SVLAN_MEMBERCFG39_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG39_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG39_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG39_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG39_CTRL1    0x0c9d

#define    RTL8370_REG_SVLAN_MEMBERCFG39_CTRL2    0x0c9e
#define    RTL8370_SVLAN_MEMBERCFG39_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG39_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG39_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG39_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG39_CTRL3    0x0c9f
#define    RTL8370_SVLAN_MEMBERCFG39_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG39_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG39_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG39_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG39_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG39_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG40_CTRL0    0x0ca0
#define    RTL8370_SVLAN_MEMBERCFG40_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG40_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG40_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG40_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG40_CTRL1    0x0ca1

#define    RTL8370_REG_SVLAN_MEMBERCFG40_CTRL2    0x0ca2
#define    RTL8370_SVLAN_MEMBERCFG40_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG40_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG40_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG40_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG40_CTRL3    0x0ca3
#define    RTL8370_SVLAN_MEMBERCFG40_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG40_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG40_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG40_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG40_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG40_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG41_CTRL0    0x0ca4
#define    RTL8370_SVLAN_MEMBERCFG41_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG41_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG41_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG41_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG41_CTRL1    0x0ca5

#define    RTL8370_REG_SVLAN_MEMBERCFG41_CTRL2    0x0ca6
#define    RTL8370_SVLAN_MEMBERCFG41_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG41_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG41_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG41_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG41_CTRL3    0x0ca7
#define    RTL8370_SVLAN_MEMBERCFG41_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG41_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG41_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG41_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG41_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG41_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG42_CTRL0    0x0ca8
#define    RTL8370_SVLAN_MEMBERCFG42_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG42_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG42_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG42_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG42_CTRL1    0x0ca9

#define    RTL8370_REG_SVLAN_MEMBERCFG42_CTRL2    0x0caa
#define    RTL8370_SVLAN_MEMBERCFG42_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG42_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG42_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG42_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG42_CTRL3    0x0cab
#define    RTL8370_SVLAN_MEMBERCFG42_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG42_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG42_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG42_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG42_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG42_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG43_CTRL0    0x0cac
#define    RTL8370_SVLAN_MEMBERCFG43_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG43_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG43_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG43_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG43_CTRL1    0x0cad

#define    RTL8370_REG_SVLAN_MEMBERCFG43_CTRL2    0x0cae
#define    RTL8370_SVLAN_MEMBERCFG43_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG43_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG43_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG43_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG43_CTRL3    0x0caf
#define    RTL8370_SVLAN_MEMBERCFG43_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG43_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG43_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG43_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG43_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG43_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG44_CTRL0    0x0cb0
#define    RTL8370_SVLAN_MEMBERCFG44_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG44_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG44_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG44_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG44_CTRL1    0x0cb1

#define    RTL8370_REG_SVLAN_MEMBERCFG44_CTRL2    0x0cb2
#define    RTL8370_SVLAN_MEMBERCFG44_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG44_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG44_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG44_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG44_CTRL3    0x0cb3
#define    RTL8370_SVLAN_MEMBERCFG44_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG44_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG44_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG44_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG44_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG44_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG45_CTRL0    0x0cb4
#define    RTL8370_SVLAN_MEMBERCFG45_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG45_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG45_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG45_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG45_CTRL1    0x0cb5

#define    RTL8370_REG_SVLAN_MEMBERCFG45_CTRL2    0x0cb6
#define    RTL8370_SVLAN_MEMBERCFG45_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG45_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG45_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG45_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG45_CTRL3    0x0cb7
#define    RTL8370_SVLAN_MEMBERCFG45_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG45_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG45_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG45_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG45_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG45_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG46_CTRL0    0x0cb8
#define    RTL8370_SVLAN_MEMBERCFG46_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG46_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG46_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG46_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG46_CTRL1    0x0cb9

#define    RTL8370_REG_SVLAN_MEMBERCFG46_CTRL2    0x0cba
#define    RTL8370_SVLAN_MEMBERCFG46_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG46_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG46_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG46_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG46_CTRL3    0x0cbb
#define    RTL8370_SVLAN_MEMBERCFG46_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG46_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG46_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG46_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG46_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG46_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG47_CTRL0    0x0cbc
#define    RTL8370_SVLAN_MEMBERCFG47_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG47_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG47_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG47_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG47_CTRL1    0x0cbd

#define    RTL8370_REG_SVLAN_MEMBERCFG47_CTRL2    0x0cbe
#define    RTL8370_SVLAN_MEMBERCFG47_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG47_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG47_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG47_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG47_CTRL3    0x0cbf
#define    RTL8370_SVLAN_MEMBERCFG47_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG47_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG47_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG47_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG47_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG47_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG48_CTRL0    0x0cc0
#define    RTL8370_SVLAN_MEMBERCFG48_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG48_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG48_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG48_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG48_CTRL1    0x0cc1

#define    RTL8370_REG_SVLAN_MEMBERCFG48_CTRL2    0x0cc2
#define    RTL8370_SVLAN_MEMBERCFG48_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG48_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG48_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG48_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG48_CTRL3    0x0cc3
#define    RTL8370_SVLAN_MEMBERCFG48_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG48_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG48_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG48_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG48_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG48_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG49_CTRL0    0x0cc4
#define    RTL8370_SVLAN_MEMBERCFG49_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG49_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG49_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG49_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG49_CTRL1    0x0cc5

#define    RTL8370_REG_SVLAN_MEMBERCFG49_CTRL2    0x0cc6
#define    RTL8370_SVLAN_MEMBERCFG49_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG49_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG49_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG49_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG49_CTRL3    0x0cc7
#define    RTL8370_SVLAN_MEMBERCFG49_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG49_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG49_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG49_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG49_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG49_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG50_CTRL0    0x0cc8
#define    RTL8370_SVLAN_MEMBERCFG50_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG50_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG50_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG50_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG50_CTRL1    0x0cc9

#define    RTL8370_REG_SVLAN_MEMBERCFG50_CTRL2    0x0cca
#define    RTL8370_SVLAN_MEMBERCFG50_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG50_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG50_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG50_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG50_CTRL3    0x0ccb
#define    RTL8370_SVLAN_MEMBERCFG50_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG50_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG50_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG50_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG50_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG50_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG51_CTRL0    0x0ccc
#define    RTL8370_SVLAN_MEMBERCFG51_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG51_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG51_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG51_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG51_CTRL1    0x0ccd

#define    RTL8370_REG_SVLAN_MEMBERCFG51_CTRL2    0x0cce
#define    RTL8370_SVLAN_MEMBERCFG51_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG51_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG51_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG51_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG51_CTRL3    0x0ccf
#define    RTL8370_SVLAN_MEMBERCFG51_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG51_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG51_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG51_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG51_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG51_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG52_CTRL0    0x0cd0
#define    RTL8370_SVLAN_MEMBERCFG52_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG52_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG52_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG52_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG52_CTRL1    0x0cd1

#define    RTL8370_REG_SVLAN_MEMBERCFG52_CTRL2    0x0cd2
#define    RTL8370_SVLAN_MEMBERCFG52_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG52_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG52_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG52_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG52_CTRL3    0x0cd3
#define    RTL8370_SVLAN_MEMBERCFG52_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG52_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG52_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG52_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG52_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG52_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG53_CTRL0    0x0cd4
#define    RTL8370_SVLAN_MEMBERCFG53_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG53_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG53_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG53_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG53_CTRL1    0x0cd5

#define    RTL8370_REG_SVLAN_MEMBERCFG53_CTRL2    0x0cd6
#define    RTL8370_SVLAN_MEMBERCFG53_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG53_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG53_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG53_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG53_CTRL3    0x0cd7
#define    RTL8370_SVLAN_MEMBERCFG53_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG53_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG53_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG53_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG53_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG53_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG54_CTRL0    0x0cd8
#define    RTL8370_SVLAN_MEMBERCFG54_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG54_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG54_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG54_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG54_CTRL1    0x0cd9

#define    RTL8370_REG_SVLAN_MEMBERCFG54_CTRL2    0x0cda
#define    RTL8370_SVLAN_MEMBERCFG54_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG54_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG54_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG54_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG54_CTRL3    0x0cdb
#define    RTL8370_SVLAN_MEMBERCFG54_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG54_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG54_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG54_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG54_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG54_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG55_CTRL0    0x0cdc
#define    RTL8370_SVLAN_MEMBERCFG55_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG55_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG55_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG55_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG55_CTRL1    0x0cdd

#define    RTL8370_REG_SVLAN_MEMBERCFG55_CTRL2    0x0cde
#define    RTL8370_SVLAN_MEMBERCFG55_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG55_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG55_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG55_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG55_CTRL3    0x0cdf
#define    RTL8370_SVLAN_MEMBERCFG55_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG55_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG55_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG55_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG55_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG55_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG56_CTRL0    0x0ce0
#define    RTL8370_SVLAN_MEMBERCFG56_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG56_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG56_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG56_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG56_CTRL1    0x0ce1

#define    RTL8370_REG_SVLAN_MEMBERCFG56_CTRL2    0x0ce2
#define    RTL8370_SVLAN_MEMBERCFG56_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG56_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG56_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG56_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG56_CTRL3    0x0ce3
#define    RTL8370_SVLAN_MEMBERCFG56_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG56_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG56_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG56_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG56_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG56_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG57_CTRL0    0x0ce4
#define    RTL8370_SVLAN_MEMBERCFG57_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG57_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG57_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG57_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG57_CTRL1    0x0ce5

#define    RTL8370_REG_SVLAN_MEMBERCFG57_CTRL2    0x0ce6
#define    RTL8370_SVLAN_MEMBERCFG57_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG57_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG57_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG57_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG57_CTRL3    0x0ce7
#define    RTL8370_SVLAN_MEMBERCFG57_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG57_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG57_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG57_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG57_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG57_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG58_CTRL0    0x0ce8
#define    RTL8370_SVLAN_MEMBERCFG58_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG58_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG58_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG58_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG58_CTRL1    0x0ce9

#define    RTL8370_REG_SVLAN_MEMBERCFG58_CTRL2    0x0cea
#define    RTL8370_SVLAN_MEMBERCFG58_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG58_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG58_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG58_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG58_CTRL3    0x0ceb
#define    RTL8370_SVLAN_MEMBERCFG58_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG58_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG58_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG58_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG58_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG58_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG59_CTRL0    0x0cec
#define    RTL8370_SVLAN_MEMBERCFG59_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG59_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG59_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG59_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG59_CTRL1    0x0ced

#define    RTL8370_REG_SVLAN_MEMBERCFG59_CTRL2    0x0cee
#define    RTL8370_SVLAN_MEMBERCFG59_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG59_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG59_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG59_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG59_CTRL3    0x0cef
#define    RTL8370_SVLAN_MEMBERCFG59_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG59_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG59_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG59_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG59_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG59_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG60_CTRL0    0x0cf0
#define    RTL8370_SVLAN_MEMBERCFG60_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG60_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG60_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG60_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG60_CTRL1    0x0cf1

#define    RTL8370_REG_SVLAN_MEMBERCFG60_CTRL2    0x0cf2
#define    RTL8370_SVLAN_MEMBERCFG60_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG60_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG60_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG60_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG60_CTRL3    0x0cf3
#define    RTL8370_SVLAN_MEMBERCFG60_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG60_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG60_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG60_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG60_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG60_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG61_CTRL0    0x0cf4
#define    RTL8370_SVLAN_MEMBERCFG61_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG61_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG61_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG61_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG61_CTRL1    0x0cf5

#define    RTL8370_REG_SVLAN_MEMBERCFG61_CTRL2    0x0cf6
#define    RTL8370_SVLAN_MEMBERCFG61_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG61_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG61_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG61_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG61_CTRL3    0x0cf7
#define    RTL8370_SVLAN_MEMBERCFG61_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG61_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG61_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG61_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG61_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG61_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG62_CTRL0    0x0cf8
#define    RTL8370_SVLAN_MEMBERCFG62_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG62_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG62_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG62_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG62_CTRL1    0x0cf9

#define    RTL8370_REG_SVLAN_MEMBERCFG62_CTRL2    0x0cfa
#define    RTL8370_SVLAN_MEMBERCFG62_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG62_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG62_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG62_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG62_CTRL3    0x0cfb
#define    RTL8370_SVLAN_MEMBERCFG62_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG62_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG62_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG62_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG62_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG62_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG63_CTRL0    0x0cfc
#define    RTL8370_SVLAN_MEMBERCFG63_CTRL0_VS_MSTI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG63_CTRL0_VS_MSTI_MASK    0xF000
#define    RTL8370_SVLAN_MEMBERCFG63_CTRL0_VS_RELAYSVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG63_CTRL0_VS_RELAYSVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG63_CTRL1    0x0cfd

#define    RTL8370_REG_SVLAN_MEMBERCFG63_CTRL2    0x0cfe
#define    RTL8370_SVLAN_MEMBERCFG63_CTRL2_VS_SPRI_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG63_CTRL2_VS_SPRI_MASK    0x7000
#define    RTL8370_SVLAN_MEMBERCFG63_CTRL2_VS_FID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG63_CTRL2_VS_FID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_MEMBERCFG63_CTRL3    0x0cff
#define    RTL8370_SVLAN_MEMBERCFG63_CTRL3_VS_EFID_OFFSET    13
#define    RTL8370_SVLAN_MEMBERCFG63_CTRL3_VS_EFID_MASK    0xE000
#define    RTL8370_SVLAN_MEMBERCFG63_CTRL3_VS_EFIDEN_OFFSET    12
#define    RTL8370_SVLAN_MEMBERCFG63_CTRL3_VS_EFIDEN_MASK    0x1000
#define    RTL8370_SVLAN_MEMBERCFG63_CTRL3_VS_SVID_OFFSET    0
#define    RTL8370_SVLAN_MEMBERCFG63_CTRL3_VS_SVID_MASK    0xFFF

#define    RTL8370_REG_SVLAN_C2SCFG0_CTRL0    0x0d00
#define    RTL8370_SVLAN_C2SCFG0_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG0_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG0_CTRL1    0x0d01

#define    RTL8370_REG_SVLAN_C2SCFG0_CTRL2    0x0d02
#define    RTL8370_SVLAN_C2SCFG0_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG0_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG1_CTRL0    0x0d03
#define    RTL8370_SVLAN_C2SCFG1_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG1_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG1_CTRL1    0x0d04

#define    RTL8370_REG_SVLAN_C2SCFG1_CTRL2    0x0d05
#define    RTL8370_SVLAN_C2SCFG1_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG1_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG2_CTRL0    0x0d06
#define    RTL8370_SVLAN_C2SCFG2_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG2_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG2_CTRL1    0x0d07

#define    RTL8370_REG_SVLAN_C2SCFG2_CTRL2    0x0d08
#define    RTL8370_SVLAN_C2SCFG2_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG2_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG3_CTRL0    0x0d09
#define    RTL8370_SVLAN_C2SCFG3_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG3_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG3_CTRL1    0x0d0a

#define    RTL8370_REG_SVLAN_C2SCFG3_CTRL2    0x0d0b
#define    RTL8370_SVLAN_C2SCFG3_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG3_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG4_CTRL0    0x0d0c
#define    RTL8370_SVLAN_C2SCFG4_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG4_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG4_CTRL1    0x0d0d

#define    RTL8370_REG_SVLAN_C2SCFG4_CTRL2    0x0d0e
#define    RTL8370_SVLAN_C2SCFG4_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG4_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG5_CTRL0    0x0d0f
#define    RTL8370_SVLAN_C2SCFG5_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG5_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG5_CTRL1    0x0d10

#define    RTL8370_REG_SVLAN_C2SCFG5_CTRL2    0x0d11
#define    RTL8370_SVLAN_C2SCFG5_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG5_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG6_CTRL0    0x0d12
#define    RTL8370_SVLAN_C2SCFG6_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG6_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG6_CTRL1    0x0d13

#define    RTL8370_REG_SVLAN_C2SCFG6_CTRL2    0x0d14
#define    RTL8370_SVLAN_C2SCFG6_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG6_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG7_CTRL0    0x0d15
#define    RTL8370_SVLAN_C2SCFG7_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG7_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG7_CTRL1    0x0d16

#define    RTL8370_REG_SVLAN_C2SCFG7_CTRL2    0x0d17
#define    RTL8370_SVLAN_C2SCFG7_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG7_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG8_CTRL0    0x0d18
#define    RTL8370_SVLAN_C2SCFG8_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG8_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG8_CTRL1    0x0d19

#define    RTL8370_REG_SVLAN_C2SCFG8_CTRL2    0x0d1a
#define    RTL8370_SVLAN_C2SCFG8_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG8_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG9_CTRL0    0x0d1b
#define    RTL8370_SVLAN_C2SCFG9_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG9_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG9_CTRL1    0x0d1c

#define    RTL8370_REG_SVLAN_C2SCFG9_CTRL2    0x0d1d
#define    RTL8370_SVLAN_C2SCFG9_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG9_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG10_CTRL0    0x0d1e
#define    RTL8370_SVLAN_C2SCFG10_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG10_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG10_CTRL1    0x0d1f

#define    RTL8370_REG_SVLAN_C2SCFG10_CTRL2    0x0d20
#define    RTL8370_SVLAN_C2SCFG10_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG10_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG11_CTRL0    0x0d21
#define    RTL8370_SVLAN_C2SCFG11_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG11_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG11_CTRL1    0x0d22

#define    RTL8370_REG_SVLAN_C2SCFG11_CTRL2    0x0d23
#define    RTL8370_SVLAN_C2SCFG11_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG11_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG12_CTRL0    0x0d24
#define    RTL8370_SVLAN_C2SCFG12_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG12_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG12_CTRL1    0x0d25

#define    RTL8370_REG_SVLAN_C2SCFG12_CTRL2    0x0d26
#define    RTL8370_SVLAN_C2SCFG12_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG12_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG13_CTRL0    0x0d27
#define    RTL8370_SVLAN_C2SCFG13_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG13_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG13_CTRL1    0x0d28

#define    RTL8370_REG_SVLAN_C2SCFG13_CTRL2    0x0d29
#define    RTL8370_SVLAN_C2SCFG13_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG13_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG14_CTRL0    0x0d2a
#define    RTL8370_SVLAN_C2SCFG14_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG14_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG14_CTRL1    0x0d2b

#define    RTL8370_REG_SVLAN_C2SCFG14_CTRL2    0x0d2c
#define    RTL8370_SVLAN_C2SCFG14_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG14_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG15_CTRL0    0x0d2d
#define    RTL8370_SVLAN_C2SCFG15_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG15_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG15_CTRL1    0x0d2e

#define    RTL8370_REG_SVLAN_C2SCFG15_CTRL2    0x0d2f
#define    RTL8370_SVLAN_C2SCFG15_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG15_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG16_CTRL0    0x0d30
#define    RTL8370_SVLAN_C2SCFG16_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG16_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG16_CTRL1    0x0d31

#define    RTL8370_REG_SVLAN_C2SCFG16_CTRL2    0x0d32
#define    RTL8370_SVLAN_C2SCFG16_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG16_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG17_CTRL0    0x0d33
#define    RTL8370_SVLAN_C2SCFG17_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG17_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG17_CTRL1    0x0d34

#define    RTL8370_REG_SVLAN_C2SCFG17_CTRL2    0x0d35
#define    RTL8370_SVLAN_C2SCFG17_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG17_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG18_CTRL0    0x0d36
#define    RTL8370_SVLAN_C2SCFG18_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG18_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG18_CTRL1    0x0d37

#define    RTL8370_REG_SVLAN_C2SCFG18_CTRL2    0x0d38
#define    RTL8370_SVLAN_C2SCFG18_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG18_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG19_CTRL0    0x0d39
#define    RTL8370_SVLAN_C2SCFG19_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG19_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG19_CTRL1    0x0d3a

#define    RTL8370_REG_SVLAN_C2SCFG19_CTRL2    0x0d3b
#define    RTL8370_SVLAN_C2SCFG19_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG19_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG20_CTRL0    0x0d3c
#define    RTL8370_SVLAN_C2SCFG20_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG20_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG20_CTRL1    0x0d3d

#define    RTL8370_REG_SVLAN_C2SCFG20_CTRL2    0x0d3e
#define    RTL8370_SVLAN_C2SCFG20_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG20_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG21_CTRL0    0x0d3f
#define    RTL8370_SVLAN_C2SCFG21_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG21_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG21_CTRL1    0x0d40

#define    RTL8370_REG_SVLAN_C2SCFG21_CTRL2    0x0d41
#define    RTL8370_SVLAN_C2SCFG21_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG21_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG22_CTRL0    0x0d42
#define    RTL8370_SVLAN_C2SCFG22_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG22_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG22_CTRL1    0x0d43

#define    RTL8370_REG_SVLAN_C2SCFG22_CTRL2    0x0d44
#define    RTL8370_SVLAN_C2SCFG22_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG22_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG23_CTRL0    0x0d45
#define    RTL8370_SVLAN_C2SCFG23_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG23_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG23_CTRL1    0x0d46

#define    RTL8370_REG_SVLAN_C2SCFG23_CTRL2    0x0d47
#define    RTL8370_SVLAN_C2SCFG23_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG23_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG24_CTRL0    0x0d48
#define    RTL8370_SVLAN_C2SCFG24_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG24_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG24_CTRL1    0x0d49

#define    RTL8370_REG_SVLAN_C2SCFG24_CTRL2    0x0d4a
#define    RTL8370_SVLAN_C2SCFG24_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG24_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG25_CTRL0    0x0d4b
#define    RTL8370_SVLAN_C2SCFG25_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG25_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG25_CTRL1    0x0d4c

#define    RTL8370_REG_SVLAN_C2SCFG25_CTRL2    0x0d4d
#define    RTL8370_SVLAN_C2SCFG25_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG25_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG26_CTRL0    0x0d4e
#define    RTL8370_SVLAN_C2SCFG26_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG26_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG26_CTRL1    0x0d4f

#define    RTL8370_REG_SVLAN_C2SCFG26_CTRL2    0x0d50
#define    RTL8370_SVLAN_C2SCFG26_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG26_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG27_CTRL0    0x0d51
#define    RTL8370_SVLAN_C2SCFG27_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG27_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG27_CTRL1    0x0d52

#define    RTL8370_REG_SVLAN_C2SCFG27_CTRL2    0x0d53
#define    RTL8370_SVLAN_C2SCFG27_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG27_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG28_CTRL0    0x0d54
#define    RTL8370_SVLAN_C2SCFG28_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG28_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG28_CTRL1    0x0d55

#define    RTL8370_REG_SVLAN_C2SCFG28_CTRL2    0x0d56
#define    RTL8370_SVLAN_C2SCFG28_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG28_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG29_CTRL0    0x0d57
#define    RTL8370_SVLAN_C2SCFG29_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG29_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG29_CTRL1    0x0d58

#define    RTL8370_REG_SVLAN_C2SCFG29_CTRL2    0x0d59
#define    RTL8370_SVLAN_C2SCFG29_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG29_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG30_CTRL0    0x0d5a
#define    RTL8370_SVLAN_C2SCFG30_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG30_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG30_CTRL1    0x0d5b

#define    RTL8370_REG_SVLAN_C2SCFG30_CTRL2    0x0d5c
#define    RTL8370_SVLAN_C2SCFG30_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG30_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG31_CTRL0    0x0d5d
#define    RTL8370_SVLAN_C2SCFG31_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG31_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG31_CTRL1    0x0d5e

#define    RTL8370_REG_SVLAN_C2SCFG31_CTRL2    0x0d5f
#define    RTL8370_SVLAN_C2SCFG31_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG31_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG32_CTRL0    0x0d60
#define    RTL8370_SVLAN_C2SCFG32_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG32_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG32_CTRL1    0x0d61

#define    RTL8370_REG_SVLAN_C2SCFG32_CTRL2    0x0d62
#define    RTL8370_SVLAN_C2SCFG32_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG32_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG33_CTRL0    0x0d63
#define    RTL8370_SVLAN_C2SCFG33_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG33_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG33_CTRL1    0x0d64

#define    RTL8370_REG_SVLAN_C2SCFG33_CTRL2    0x0d65
#define    RTL8370_SVLAN_C2SCFG33_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG33_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG34_CTRL0    0x0d66
#define    RTL8370_SVLAN_C2SCFG34_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG34_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG34_CTRL1    0x0d67

#define    RTL8370_REG_SVLAN_C2SCFG34_CTRL2    0x0d68
#define    RTL8370_SVLAN_C2SCFG34_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG34_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG35_CTRL0    0x0d69
#define    RTL8370_SVLAN_C2SCFG35_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG35_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG35_CTRL1    0x0d6a

#define    RTL8370_REG_SVLAN_C2SCFG35_CTRL2    0x0d6b
#define    RTL8370_SVLAN_C2SCFG35_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG35_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG36_CTRL0    0x0d6c
#define    RTL8370_SVLAN_C2SCFG36_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG36_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG36_CTRL1    0x0d6d

#define    RTL8370_REG_SVLAN_C2SCFG36_CTRL2    0x0d6e
#define    RTL8370_SVLAN_C2SCFG36_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG36_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG37_CTRL0    0x0d6f
#define    RTL8370_SVLAN_C2SCFG37_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG37_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG37_CTRL1    0x0d70

#define    RTL8370_REG_SVLAN_C2SCFG37_CTRL2    0x0d71
#define    RTL8370_SVLAN_C2SCFG37_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG37_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG38_CTRL0    0x0d72
#define    RTL8370_SVLAN_C2SCFG38_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG38_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG38_CTRL1    0x0d73

#define    RTL8370_REG_SVLAN_C2SCFG38_CTRL2    0x0d74
#define    RTL8370_SVLAN_C2SCFG38_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG38_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG39_CTRL0    0x0d75
#define    RTL8370_SVLAN_C2SCFG39_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG39_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG39_CTRL1    0x0d76

#define    RTL8370_REG_SVLAN_C2SCFG39_CTRL2    0x0d77
#define    RTL8370_SVLAN_C2SCFG39_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG39_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG40_CTRL0    0x0d78
#define    RTL8370_SVLAN_C2SCFG40_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG40_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG40_CTRL1    0x0d79

#define    RTL8370_REG_SVLAN_C2SCFG40_CTRL2    0x0d7a
#define    RTL8370_SVLAN_C2SCFG40_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG40_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG41_CTRL0    0x0d7b
#define    RTL8370_SVLAN_C2SCFG41_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG41_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG41_CTRL1    0x0d7c

#define    RTL8370_REG_SVLAN_C2SCFG41_CTRL2    0x0d7d
#define    RTL8370_SVLAN_C2SCFG41_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG41_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG42_CTRL0    0x0d7e
#define    RTL8370_SVLAN_C2SCFG42_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG42_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG42_CTRL1    0x0d7f

#define    RTL8370_REG_SVLAN_C2SCFG42_CTRL2    0x0d80
#define    RTL8370_SVLAN_C2SCFG42_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG42_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG43_CTRL0    0x0d81
#define    RTL8370_SVLAN_C2SCFG43_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG43_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG43_CTRL1    0x0d82

#define    RTL8370_REG_SVLAN_C2SCFG43_CTRL2    0x0d83
#define    RTL8370_SVLAN_C2SCFG43_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG43_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG44_CTRL0    0x0d84
#define    RTL8370_SVLAN_C2SCFG44_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG44_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG44_CTRL1    0x0d85

#define    RTL8370_REG_SVLAN_C2SCFG44_CTRL2    0x0d86
#define    RTL8370_SVLAN_C2SCFG44_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG44_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG45_CTRL0    0x0d87
#define    RTL8370_SVLAN_C2SCFG45_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG45_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG45_CTRL1    0x0d88

#define    RTL8370_REG_SVLAN_C2SCFG45_CTRL2    0x0d89
#define    RTL8370_SVLAN_C2SCFG45_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG45_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG46_CTRL0    0x0d8a
#define    RTL8370_SVLAN_C2SCFG46_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG46_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG46_CTRL1    0x0d8b

#define    RTL8370_REG_SVLAN_C2SCFG46_CTRL2    0x0d8c
#define    RTL8370_SVLAN_C2SCFG46_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG46_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG47_CTRL0    0x0d8d
#define    RTL8370_SVLAN_C2SCFG47_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG47_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG47_CTRL1    0x0d8e

#define    RTL8370_REG_SVLAN_C2SCFG47_CTRL2    0x0d8f
#define    RTL8370_SVLAN_C2SCFG47_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG47_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG48_CTRL0    0x0d90
#define    RTL8370_SVLAN_C2SCFG48_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG48_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG48_CTRL1    0x0d91

#define    RTL8370_REG_SVLAN_C2SCFG48_CTRL2    0x0d92
#define    RTL8370_SVLAN_C2SCFG48_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG48_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG49_CTRL0    0x0d93
#define    RTL8370_SVLAN_C2SCFG49_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG49_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG49_CTRL1    0x0d94

#define    RTL8370_REG_SVLAN_C2SCFG49_CTRL2    0x0d95
#define    RTL8370_SVLAN_C2SCFG49_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG49_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG50_CTRL0    0x0d96
#define    RTL8370_SVLAN_C2SCFG50_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG50_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG50_CTRL1    0x0d97

#define    RTL8370_REG_SVLAN_C2SCFG50_CTRL2    0x0d98
#define    RTL8370_SVLAN_C2SCFG50_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG50_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG51_CTRL0    0x0d99
#define    RTL8370_SVLAN_C2SCFG51_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG51_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG51_CTRL1    0x0d9a

#define    RTL8370_REG_SVLAN_C2SCFG51_CTRL2    0x0d9b
#define    RTL8370_SVLAN_C2SCFG51_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG51_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG52_CTRL0    0x0d9c
#define    RTL8370_SVLAN_C2SCFG52_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG52_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG52_CTRL1    0x0d9d

#define    RTL8370_REG_SVLAN_C2SCFG52_CTRL2    0x0d9e
#define    RTL8370_SVLAN_C2SCFG52_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG52_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG53_CTRL0    0x0d9f
#define    RTL8370_SVLAN_C2SCFG53_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG53_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG53_CTRL1    0x0da0

#define    RTL8370_REG_SVLAN_C2SCFG53_CTRL2    0x0da1
#define    RTL8370_SVLAN_C2SCFG53_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG53_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG54_CTRL0    0x0da2
#define    RTL8370_SVLAN_C2SCFG54_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG54_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG54_CTRL1    0x0da3

#define    RTL8370_REG_SVLAN_C2SCFG54_CTRL2    0x0da4
#define    RTL8370_SVLAN_C2SCFG54_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG54_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG55_CTRL0    0x0da5
#define    RTL8370_SVLAN_C2SCFG55_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG55_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG55_CTRL1    0x0da6

#define    RTL8370_REG_SVLAN_C2SCFG55_CTRL2    0x0da7
#define    RTL8370_SVLAN_C2SCFG55_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG55_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG56_CTRL0    0x0da8
#define    RTL8370_SVLAN_C2SCFG56_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG56_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG56_CTRL1    0x0da9

#define    RTL8370_REG_SVLAN_C2SCFG56_CTRL2    0x0daa
#define    RTL8370_SVLAN_C2SCFG56_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG56_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG57_CTRL0    0x0dab
#define    RTL8370_SVLAN_C2SCFG57_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG57_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG57_CTRL1    0x0dac

#define    RTL8370_REG_SVLAN_C2SCFG57_CTRL2    0x0dad
#define    RTL8370_SVLAN_C2SCFG57_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG57_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG58_CTRL0    0x0dae
#define    RTL8370_SVLAN_C2SCFG58_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG58_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG58_CTRL1    0x0daf

#define    RTL8370_REG_SVLAN_C2SCFG58_CTRL2    0x0db0
#define    RTL8370_SVLAN_C2SCFG58_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG58_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG59_CTRL0    0x0db1
#define    RTL8370_SVLAN_C2SCFG59_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG59_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG59_CTRL1    0x0db2

#define    RTL8370_REG_SVLAN_C2SCFG59_CTRL2    0x0db3
#define    RTL8370_SVLAN_C2SCFG59_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG59_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG60_CTRL0    0x0db4
#define    RTL8370_SVLAN_C2SCFG60_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG60_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG60_CTRL1    0x0db5

#define    RTL8370_REG_SVLAN_C2SCFG60_CTRL2    0x0db6
#define    RTL8370_SVLAN_C2SCFG60_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG60_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG61_CTRL0    0x0db7
#define    RTL8370_SVLAN_C2SCFG61_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG61_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG61_CTRL1    0x0db8

#define    RTL8370_REG_SVLAN_C2SCFG61_CTRL2    0x0db9
#define    RTL8370_SVLAN_C2SCFG61_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG61_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG62_CTRL0    0x0dba
#define    RTL8370_SVLAN_C2SCFG62_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG62_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG62_CTRL1    0x0dbb

#define    RTL8370_REG_SVLAN_C2SCFG62_CTRL2    0x0dbc
#define    RTL8370_SVLAN_C2SCFG62_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG62_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG63_CTRL0    0x0dbd
#define    RTL8370_SVLAN_C2SCFG63_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG63_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG63_CTRL1    0x0dbe

#define    RTL8370_REG_SVLAN_C2SCFG63_CTRL2    0x0dbf
#define    RTL8370_SVLAN_C2SCFG63_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG63_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG64_CTRL0    0x0dc0
#define    RTL8370_SVLAN_C2SCFG64_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG64_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG64_CTRL1    0x0dc1

#define    RTL8370_REG_SVLAN_C2SCFG64_CTRL2    0x0dc2
#define    RTL8370_SVLAN_C2SCFG64_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG64_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG65_CTRL0    0x0dc3
#define    RTL8370_SVLAN_C2SCFG65_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG65_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG65_CTRL1    0x0dc4

#define    RTL8370_REG_SVLAN_C2SCFG65_CTRL2    0x0dc5
#define    RTL8370_SVLAN_C2SCFG65_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG65_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG66_CTRL0    0x0dc6
#define    RTL8370_SVLAN_C2SCFG66_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG66_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG66_CTRL1    0x0dc7

#define    RTL8370_REG_SVLAN_C2SCFG66_CTRL2    0x0dc8
#define    RTL8370_SVLAN_C2SCFG66_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG66_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG67_CTRL0    0x0dc9
#define    RTL8370_SVLAN_C2SCFG67_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG67_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG67_CTRL1    0x0dca

#define    RTL8370_REG_SVLAN_C2SCFG67_CTRL2    0x0dcb
#define    RTL8370_SVLAN_C2SCFG67_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG67_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG68_CTRL0    0x0dcc
#define    RTL8370_SVLAN_C2SCFG68_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG68_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG68_CTRL1    0x0dcd

#define    RTL8370_REG_SVLAN_C2SCFG68_CTRL2    0x0dce
#define    RTL8370_SVLAN_C2SCFG68_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG68_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG69_CTRL0    0x0dcf
#define    RTL8370_SVLAN_C2SCFG69_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG69_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG69_CTRL1    0x0dd0

#define    RTL8370_REG_SVLAN_C2SCFG69_CTRL2    0x0dd1
#define    RTL8370_SVLAN_C2SCFG69_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG69_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG70_CTRL0    0x0dd2
#define    RTL8370_SVLAN_C2SCFG70_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG70_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG70_CTRL1    0x0dd3

#define    RTL8370_REG_SVLAN_C2SCFG70_CTRL2    0x0dd4
#define    RTL8370_SVLAN_C2SCFG70_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG70_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG71_CTRL0    0x0dd5
#define    RTL8370_SVLAN_C2SCFG71_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG71_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG71_CTRL1    0x0dd6

#define    RTL8370_REG_SVLAN_C2SCFG71_CTRL2    0x0dd7
#define    RTL8370_SVLAN_C2SCFG71_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG71_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG72_CTRL0    0x0dd8
#define    RTL8370_SVLAN_C2SCFG72_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG72_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG72_CTRL1    0x0dd9

#define    RTL8370_REG_SVLAN_C2SCFG72_CTRL2    0x0dda
#define    RTL8370_SVLAN_C2SCFG72_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG72_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG73_CTRL0    0x0ddb
#define    RTL8370_SVLAN_C2SCFG73_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG73_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG73_CTRL1    0x0ddc

#define    RTL8370_REG_SVLAN_C2SCFG73_CTRL2    0x0ddd
#define    RTL8370_SVLAN_C2SCFG73_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG73_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG74_CTRL0    0x0dde
#define    RTL8370_SVLAN_C2SCFG74_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG74_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG74_CTRL1    0x0ddf

#define    RTL8370_REG_SVLAN_C2SCFG74_CTRL2    0x0de0
#define    RTL8370_SVLAN_C2SCFG74_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG74_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG75_CTRL0    0x0de1
#define    RTL8370_SVLAN_C2SCFG75_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG75_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG75_CTRL1    0x0de2

#define    RTL8370_REG_SVLAN_C2SCFG75_CTRL2    0x0de3
#define    RTL8370_SVLAN_C2SCFG75_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG75_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG76_CTRL0    0x0de4
#define    RTL8370_SVLAN_C2SCFG76_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG76_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG76_CTRL1    0x0de5

#define    RTL8370_REG_SVLAN_C2SCFG76_CTRL2    0x0de6
#define    RTL8370_SVLAN_C2SCFG76_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG76_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG77_CTRL0    0x0de7
#define    RTL8370_SVLAN_C2SCFG77_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG77_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG77_CTRL1    0x0de8

#define    RTL8370_REG_SVLAN_C2SCFG77_CTRL2    0x0de9
#define    RTL8370_SVLAN_C2SCFG77_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG77_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG78_CTRL0    0x0dea
#define    RTL8370_SVLAN_C2SCFG78_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG78_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG78_CTRL1    0x0deb

#define    RTL8370_REG_SVLAN_C2SCFG78_CTRL2    0x0dec
#define    RTL8370_SVLAN_C2SCFG78_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG78_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG79_CTRL0    0x0ded
#define    RTL8370_SVLAN_C2SCFG79_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG79_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG79_CTRL1    0x0dee

#define    RTL8370_REG_SVLAN_C2SCFG79_CTRL2    0x0def
#define    RTL8370_SVLAN_C2SCFG79_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG79_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG80_CTRL0    0x0df0
#define    RTL8370_SVLAN_C2SCFG80_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG80_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG80_CTRL1    0x0df1

#define    RTL8370_REG_SVLAN_C2SCFG80_CTRL2    0x0df2
#define    RTL8370_SVLAN_C2SCFG80_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG80_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG81_CTRL0    0x0df3
#define    RTL8370_SVLAN_C2SCFG81_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG81_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG81_CTRL1    0x0df4

#define    RTL8370_REG_SVLAN_C2SCFG81_CTRL2    0x0df5
#define    RTL8370_SVLAN_C2SCFG81_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG81_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG82_CTRL0    0x0df6
#define    RTL8370_SVLAN_C2SCFG82_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG82_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG82_CTRL1    0x0df7

#define    RTL8370_REG_SVLAN_C2SCFG82_CTRL2    0x0df8
#define    RTL8370_SVLAN_C2SCFG82_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG82_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG83_CTRL0    0x0df9
#define    RTL8370_SVLAN_C2SCFG83_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG83_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG83_CTRL1    0x0dfa

#define    RTL8370_REG_SVLAN_C2SCFG83_CTRL2    0x0dfb
#define    RTL8370_SVLAN_C2SCFG83_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG83_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG84_CTRL0    0x0dfc
#define    RTL8370_SVLAN_C2SCFG84_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG84_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG84_CTRL1    0x0dfd

#define    RTL8370_REG_SVLAN_C2SCFG84_CTRL2    0x0dfe
#define    RTL8370_SVLAN_C2SCFG84_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG84_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG85_CTRL0    0x0dff
#define    RTL8370_SVLAN_C2SCFG85_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG85_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG85_CTRL1    0x0e00

#define    RTL8370_REG_SVLAN_C2SCFG85_CTRL2    0x0e01
#define    RTL8370_SVLAN_C2SCFG85_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG85_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG86_CTRL0    0x0e02
#define    RTL8370_SVLAN_C2SCFG86_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG86_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG86_CTRL1    0x0e03

#define    RTL8370_REG_SVLAN_C2SCFG86_CTRL2    0x0e04
#define    RTL8370_SVLAN_C2SCFG86_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG86_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG87_CTRL0    0x0e05
#define    RTL8370_SVLAN_C2SCFG87_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG87_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG87_CTRL1    0x0e06

#define    RTL8370_REG_SVLAN_C2SCFG87_CTRL2    0x0e07
#define    RTL8370_SVLAN_C2SCFG87_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG87_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG88_CTRL0    0x0e08
#define    RTL8370_SVLAN_C2SCFG88_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG88_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG88_CTRL1    0x0e09

#define    RTL8370_REG_SVLAN_C2SCFG88_CTRL2    0x0e0a
#define    RTL8370_SVLAN_C2SCFG88_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG88_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG89_CTRL0    0x0e0b
#define    RTL8370_SVLAN_C2SCFG89_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG89_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG89_CTRL1    0x0e0c

#define    RTL8370_REG_SVLAN_C2SCFG89_CTRL2    0x0e0d
#define    RTL8370_SVLAN_C2SCFG89_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG89_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG90_CTRL0    0x0e0e
#define    RTL8370_SVLAN_C2SCFG90_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG90_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG90_CTRL1    0x0e0f

#define    RTL8370_REG_SVLAN_C2SCFG90_CTRL2    0x0e10
#define    RTL8370_SVLAN_C2SCFG90_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG90_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG91_CTRL0    0x0e11
#define    RTL8370_SVLAN_C2SCFG91_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG91_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG91_CTRL1    0x0e12

#define    RTL8370_REG_SVLAN_C2SCFG91_CTRL2    0x0e13
#define    RTL8370_SVLAN_C2SCFG91_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG91_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG92_CTRL0    0x0e14
#define    RTL8370_SVLAN_C2SCFG92_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG92_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG92_CTRL1    0x0e15

#define    RTL8370_REG_SVLAN_C2SCFG92_CTRL2    0x0e16
#define    RTL8370_SVLAN_C2SCFG92_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG92_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG93_CTRL0    0x0e17
#define    RTL8370_SVLAN_C2SCFG93_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG93_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG93_CTRL1    0x0e18

#define    RTL8370_REG_SVLAN_C2SCFG93_CTRL2    0x0e19
#define    RTL8370_SVLAN_C2SCFG93_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG93_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG94_CTRL0    0x0e1a
#define    RTL8370_SVLAN_C2SCFG94_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG94_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG94_CTRL1    0x0e1b

#define    RTL8370_REG_SVLAN_C2SCFG94_CTRL2    0x0e1c
#define    RTL8370_SVLAN_C2SCFG94_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG94_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG95_CTRL0    0x0e1d
#define    RTL8370_SVLAN_C2SCFG95_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG95_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG95_CTRL1    0x0e1e

#define    RTL8370_REG_SVLAN_C2SCFG95_CTRL2    0x0e1f
#define    RTL8370_SVLAN_C2SCFG95_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG95_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG96_CTRL0    0x0e20
#define    RTL8370_SVLAN_C2SCFG96_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG96_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG96_CTRL1    0x0e21

#define    RTL8370_REG_SVLAN_C2SCFG96_CTRL2    0x0e22
#define    RTL8370_SVLAN_C2SCFG96_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG96_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG97_CTRL0    0x0e23
#define    RTL8370_SVLAN_C2SCFG97_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG97_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG97_CTRL1    0x0e24

#define    RTL8370_REG_SVLAN_C2SCFG97_CTRL2    0x0e25
#define    RTL8370_SVLAN_C2SCFG97_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG97_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG98_CTRL0    0x0e26
#define    RTL8370_SVLAN_C2SCFG98_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG98_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG98_CTRL1    0x0e27

#define    RTL8370_REG_SVLAN_C2SCFG98_CTRL2    0x0e28
#define    RTL8370_SVLAN_C2SCFG98_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG98_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG99_CTRL0    0x0e29
#define    RTL8370_SVLAN_C2SCFG99_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG99_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG99_CTRL1    0x0e2a

#define    RTL8370_REG_SVLAN_C2SCFG99_CTRL2    0x0e2b
#define    RTL8370_SVLAN_C2SCFG99_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG99_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG100_CTRL0    0x0e2c
#define    RTL8370_SVLAN_C2SCFG100_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG100_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG100_CTRL1    0x0e2d

#define    RTL8370_REG_SVLAN_C2SCFG100_CTRL2    0x0e2e
#define    RTL8370_SVLAN_C2SCFG100_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG100_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG101_CTRL0    0x0e2f
#define    RTL8370_SVLAN_C2SCFG101_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG101_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG101_CTRL1    0x0e30

#define    RTL8370_REG_SVLAN_C2SCFG101_CTRL2    0x0e31
#define    RTL8370_SVLAN_C2SCFG101_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG101_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG102_CTRL0    0x0e32
#define    RTL8370_SVLAN_C2SCFG102_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG102_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG102_CTRL1    0x0e33

#define    RTL8370_REG_SVLAN_C2SCFG102_CTRL2    0x0e34
#define    RTL8370_SVLAN_C2SCFG102_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG102_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG103_CTRL0    0x0e35
#define    RTL8370_SVLAN_C2SCFG103_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG103_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG103_CTRL1    0x0e36

#define    RTL8370_REG_SVLAN_C2SCFG103_CTRL2    0x0e37
#define    RTL8370_SVLAN_C2SCFG103_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG103_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG104_CTRL0    0x0e38
#define    RTL8370_SVLAN_C2SCFG104_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG104_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG104_CTRL1    0x0e39

#define    RTL8370_REG_SVLAN_C2SCFG104_CTRL2    0x0e3a
#define    RTL8370_SVLAN_C2SCFG104_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG104_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG105_CTRL0    0x0e3b
#define    RTL8370_SVLAN_C2SCFG105_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG105_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG105_CTRL1    0x0e3c

#define    RTL8370_REG_SVLAN_C2SCFG105_CTRL2    0x0e3d
#define    RTL8370_SVLAN_C2SCFG105_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG105_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG106_CTRL0    0x0e3e
#define    RTL8370_SVLAN_C2SCFG106_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG106_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG106_CTRL1    0x0e3f

#define    RTL8370_REG_SVLAN_C2SCFG106_CTRL2    0x0e40
#define    RTL8370_SVLAN_C2SCFG106_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG106_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG107_CTRL0    0x0e41
#define    RTL8370_SVLAN_C2SCFG107_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG107_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG107_CTRL1    0x0e42

#define    RTL8370_REG_SVLAN_C2SCFG107_CTRL2    0x0e43
#define    RTL8370_SVLAN_C2SCFG107_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG107_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG108_CTRL0    0x0e44
#define    RTL8370_SVLAN_C2SCFG108_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG108_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG108_CTRL1    0x0e45

#define    RTL8370_REG_SVLAN_C2SCFG108_CTRL2    0x0e46
#define    RTL8370_SVLAN_C2SCFG108_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG108_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG109_CTRL0    0x0e47
#define    RTL8370_SVLAN_C2SCFG109_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG109_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG109_CTRL1    0x0e48

#define    RTL8370_REG_SVLAN_C2SCFG109_CTRL2    0x0e49
#define    RTL8370_SVLAN_C2SCFG109_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG109_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG110_CTRL0    0x0e4a
#define    RTL8370_SVLAN_C2SCFG110_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG110_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG110_CTRL1    0x0e4b

#define    RTL8370_REG_SVLAN_C2SCFG110_CTRL2    0x0e4c
#define    RTL8370_SVLAN_C2SCFG110_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG110_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG111_CTRL0    0x0e4d
#define    RTL8370_SVLAN_C2SCFG111_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG111_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG111_CTRL1    0x0e4e

#define    RTL8370_REG_SVLAN_C2SCFG111_CTRL2    0x0e4f
#define    RTL8370_SVLAN_C2SCFG111_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG111_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG112_CTRL0    0x0e50
#define    RTL8370_SVLAN_C2SCFG112_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG112_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG112_CTRL1    0x0e51

#define    RTL8370_REG_SVLAN_C2SCFG112_CTRL2    0x0e52
#define    RTL8370_SVLAN_C2SCFG112_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG112_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG113_CTRL0    0x0e53
#define    RTL8370_SVLAN_C2SCFG113_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG113_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG113_CTRL1    0x0e54

#define    RTL8370_REG_SVLAN_C2SCFG113_CTRL2    0x0e55
#define    RTL8370_SVLAN_C2SCFG113_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG113_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG114_CTRL0    0x0e56
#define    RTL8370_SVLAN_C2SCFG114_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG114_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG114_CTRL1    0x0e57

#define    RTL8370_REG_SVLAN_C2SCFG114_CTRL2    0x0e58
#define    RTL8370_SVLAN_C2SCFG114_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG114_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG115_CTRL0    0x0e59
#define    RTL8370_SVLAN_C2SCFG115_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG115_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG115_CTRL1    0x0e5a

#define    RTL8370_REG_SVLAN_C2SCFG115_CTRL2    0x0e5b
#define    RTL8370_SVLAN_C2SCFG115_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG115_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG116_CTRL0    0x0e5c
#define    RTL8370_SVLAN_C2SCFG116_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG116_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG116_CTRL1    0x0e5d

#define    RTL8370_REG_SVLAN_C2SCFG116_CTRL2    0x0e5e
#define    RTL8370_SVLAN_C2SCFG116_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG116_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG117_CTRL0    0x0e5f
#define    RTL8370_SVLAN_C2SCFG117_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG117_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG117_CTRL1    0x0e60

#define    RTL8370_REG_SVLAN_C2SCFG117_CTRL2    0x0e61
#define    RTL8370_SVLAN_C2SCFG117_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG117_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG118_CTRL0    0x0e62
#define    RTL8370_SVLAN_C2SCFG118_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG118_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG118_CTRL1    0x0e63

#define    RTL8370_REG_SVLAN_C2SCFG118_CTRL2    0x0e64
#define    RTL8370_SVLAN_C2SCFG118_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG118_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG119_CTRL0    0x0e65
#define    RTL8370_SVLAN_C2SCFG119_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG119_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG119_CTRL1    0x0e66

#define    RTL8370_REG_SVLAN_C2SCFG119_CTRL2    0x0e67
#define    RTL8370_SVLAN_C2SCFG119_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG119_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG120_CTRL0    0x0e68
#define    RTL8370_SVLAN_C2SCFG120_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG120_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG120_CTRL1    0x0e69

#define    RTL8370_REG_SVLAN_C2SCFG120_CTRL2    0x0e6a
#define    RTL8370_SVLAN_C2SCFG120_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG120_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG121_CTRL0    0x0e6b
#define    RTL8370_SVLAN_C2SCFG121_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG121_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG121_CTRL1    0x0e6c

#define    RTL8370_REG_SVLAN_C2SCFG121_CTRL2    0x0e6d
#define    RTL8370_SVLAN_C2SCFG121_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG121_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG122_CTRL0    0x0e6e
#define    RTL8370_SVLAN_C2SCFG122_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG122_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG122_CTRL1    0x0e6f

#define    RTL8370_REG_SVLAN_C2SCFG122_CTRL2    0x0e70
#define    RTL8370_SVLAN_C2SCFG122_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG122_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG123_CTRL0    0x0e71
#define    RTL8370_SVLAN_C2SCFG123_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG123_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG123_CTRL1    0x0e72

#define    RTL8370_REG_SVLAN_C2SCFG123_CTRL2    0x0e73
#define    RTL8370_SVLAN_C2SCFG123_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG123_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG124_CTRL0    0x0e74
#define    RTL8370_SVLAN_C2SCFG124_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG124_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG124_CTRL1    0x0e75

#define    RTL8370_REG_SVLAN_C2SCFG124_CTRL2    0x0e76
#define    RTL8370_SVLAN_C2SCFG124_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG124_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG125_CTRL0    0x0e77
#define    RTL8370_SVLAN_C2SCFG125_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG125_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG125_CTRL1    0x0e78

#define    RTL8370_REG_SVLAN_C2SCFG125_CTRL2    0x0e79
#define    RTL8370_SVLAN_C2SCFG125_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG125_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG126_CTRL0    0x0e7a
#define    RTL8370_SVLAN_C2SCFG126_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG126_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG126_CTRL1    0x0e7b

#define    RTL8370_REG_SVLAN_C2SCFG126_CTRL2    0x0e7c
#define    RTL8370_SVLAN_C2SCFG126_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG126_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_C2SCFG127_CTRL0    0x0e7d
#define    RTL8370_SVLAN_C2SCFG127_CTRL0_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG127_CTRL0_MASK    0x3F

#define    RTL8370_REG_SVLAN_C2SCFG127_CTRL1    0x0e7e

#define    RTL8370_REG_SVLAN_C2SCFG127_CTRL2    0x0e7f
#define    RTL8370_SVLAN_C2SCFG127_CTRL2_OFFSET    0
#define    RTL8370_SVLAN_C2SCFG127_CTRL2_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_CFG    0x0e80
#define    RTL8370_VS_UIFSEG_OFFSET    10
#define    RTL8370_VS_UIFSEG_MASK    0x400
#define    RTL8370_VS_UNMAT_OFFSET    9
#define    RTL8370_VS_UNMAT_MASK    0x200
#define    RTL8370_VS_UNTAG_OFFSET    8
#define    RTL8370_VS_UNTAG_MASK    0x100
#define    RTL8370_VS_SPRISEL_OFFSET    6
#define    RTL8370_VS_SPRISEL_MASK    0xC0
#define    RTL8370_VS_CPSVIDX_OFFSET    0
#define    RTL8370_VS_CPSVIDX_MASK    0x3F

/* (16'h0f00) hsactrl_reg */

#define    RTL8370_REG_SVLAN_SP2C_ENTRY0_CTRL0    0x0f00
#define    RTL8370_SVLAN_SP2C_ENTRY0_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY0_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY0_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY0_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY0_CTRL1    0x0f01
#define    RTL8370_SVLAN_SP2C_ENTRY0_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY0_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY1_CTRL0    0x0f02
#define    RTL8370_SVLAN_SP2C_ENTRY1_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY1_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY1_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY1_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY1_CTRL1    0x0f03
#define    RTL8370_SVLAN_SP2C_ENTRY1_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY1_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY2_CTRL0    0x0f04
#define    RTL8370_SVLAN_SP2C_ENTRY2_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY2_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY2_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY2_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY2_CTRL1    0x0f05
#define    RTL8370_SVLAN_SP2C_ENTRY2_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY2_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY3_CTRL0    0x0f06
#define    RTL8370_SVLAN_SP2C_ENTRY3_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY3_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY3_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY3_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY3_CTRL1    0x0f07
#define    RTL8370_SVLAN_SP2C_ENTRY3_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY3_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY4_CTRL0    0x0f08
#define    RTL8370_SVLAN_SP2C_ENTRY4_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY4_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY4_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY4_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY4_CTRL1    0x0f09
#define    RTL8370_SVLAN_SP2C_ENTRY4_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY4_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY5_CTRL0    0x0f0a
#define    RTL8370_SVLAN_SP2C_ENTRY5_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY5_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY5_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY5_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY5_CTRL1    0x0f0b
#define    RTL8370_SVLAN_SP2C_ENTRY5_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY5_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY6_CTRL0    0x0f0c
#define    RTL8370_SVLAN_SP2C_ENTRY6_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY6_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY6_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY6_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY6_CTRL1    0x0f0d
#define    RTL8370_SVLAN_SP2C_ENTRY6_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY6_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY7_CTRL0    0x0f0e
#define    RTL8370_SVLAN_SP2C_ENTRY7_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY7_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY7_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY7_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY7_CTRL1    0x0f0f
#define    RTL8370_SVLAN_SP2C_ENTRY7_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY7_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY8_CTRL0    0x0f10
#define    RTL8370_SVLAN_SP2C_ENTRY8_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY8_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY8_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY8_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY8_CTRL1    0x0f11
#define    RTL8370_SVLAN_SP2C_ENTRY8_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY8_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY9_CTRL0    0x0f12
#define    RTL8370_SVLAN_SP2C_ENTRY9_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY9_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY9_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY9_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY9_CTRL1    0x0f13
#define    RTL8370_SVLAN_SP2C_ENTRY9_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY9_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY10_CTRL0    0x0f14
#define    RTL8370_SVLAN_SP2C_ENTRY10_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY10_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY10_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY10_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY10_CTRL1    0x0f15
#define    RTL8370_SVLAN_SP2C_ENTRY10_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY10_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY11_CTRL0    0x0f16
#define    RTL8370_SVLAN_SP2C_ENTRY11_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY11_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY11_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY11_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY11_CTRL1    0x0f17
#define    RTL8370_SVLAN_SP2C_ENTRY11_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY11_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY12_CTRL0    0x0f18
#define    RTL8370_SVLAN_SP2C_ENTRY12_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY12_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY12_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY12_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY12_CTRL1    0x0f19
#define    RTL8370_SVLAN_SP2C_ENTRY12_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY12_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY13_CTRL0    0x0f1a
#define    RTL8370_SVLAN_SP2C_ENTRY13_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY13_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY13_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY13_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY13_CTRL1    0x0f1b
#define    RTL8370_SVLAN_SP2C_ENTRY13_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY13_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY14_CTRL0    0x0f1c
#define    RTL8370_SVLAN_SP2C_ENTRY14_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY14_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY14_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY14_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY14_CTRL1    0x0f1d
#define    RTL8370_SVLAN_SP2C_ENTRY14_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY14_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY15_CTRL0    0x0f1e
#define    RTL8370_SVLAN_SP2C_ENTRY15_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY15_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY15_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY15_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY15_CTRL1    0x0f1f
#define    RTL8370_SVLAN_SP2C_ENTRY15_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY15_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY16_CTRL0    0x0f20
#define    RTL8370_SVLAN_SP2C_ENTRY16_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY16_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY16_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY16_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY16_CTRL1    0x0f21
#define    RTL8370_SVLAN_SP2C_ENTRY16_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY16_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY17_CTRL0    0x0f22
#define    RTL8370_SVLAN_SP2C_ENTRY17_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY17_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY17_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY17_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY17_CTRL1    0x0f23
#define    RTL8370_SVLAN_SP2C_ENTRY17_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY17_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY18_CTRL0    0x0f24
#define    RTL8370_SVLAN_SP2C_ENTRY18_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY18_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY18_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY18_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY18_CTRL1    0x0f25
#define    RTL8370_SVLAN_SP2C_ENTRY18_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY18_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY19_CTRL0    0x0f26
#define    RTL8370_SVLAN_SP2C_ENTRY19_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY19_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY19_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY19_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY19_CTRL1    0x0f27
#define    RTL8370_SVLAN_SP2C_ENTRY19_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY19_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY20_CTRL0    0x0f28
#define    RTL8370_SVLAN_SP2C_ENTRY20_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY20_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY20_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY20_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY20_CTRL1    0x0f29
#define    RTL8370_SVLAN_SP2C_ENTRY20_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY20_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY21_CTRL0    0x0f2a
#define    RTL8370_SVLAN_SP2C_ENTRY21_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY21_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY21_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY21_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY21_CTRL1    0x0f2b
#define    RTL8370_SVLAN_SP2C_ENTRY21_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY21_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY22_CTRL0    0x0f2c
#define    RTL8370_SVLAN_SP2C_ENTRY22_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY22_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY22_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY22_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY22_CTRL1    0x0f2d
#define    RTL8370_SVLAN_SP2C_ENTRY22_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY22_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY23_CTRL0    0x0f2e
#define    RTL8370_SVLAN_SP2C_ENTRY23_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY23_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY23_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY23_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY23_CTRL1    0x0f2f
#define    RTL8370_SVLAN_SP2C_ENTRY23_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY23_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY24_CTRL0    0x0f30
#define    RTL8370_SVLAN_SP2C_ENTRY24_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY24_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY24_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY24_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY24_CTRL1    0x0f31
#define    RTL8370_SVLAN_SP2C_ENTRY24_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY24_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY25_CTRL0    0x0f32
#define    RTL8370_SVLAN_SP2C_ENTRY25_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY25_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY25_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY25_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY25_CTRL1    0x0f33
#define    RTL8370_SVLAN_SP2C_ENTRY25_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY25_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY26_CTRL0    0x0f34
#define    RTL8370_SVLAN_SP2C_ENTRY26_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY26_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY26_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY26_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY26_CTRL1    0x0f35
#define    RTL8370_SVLAN_SP2C_ENTRY26_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY26_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY27_CTRL0    0x0f36
#define    RTL8370_SVLAN_SP2C_ENTRY27_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY27_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY27_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY27_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY27_CTRL1    0x0f37
#define    RTL8370_SVLAN_SP2C_ENTRY27_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY27_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY28_CTRL0    0x0f38
#define    RTL8370_SVLAN_SP2C_ENTRY28_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY28_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY28_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY28_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY28_CTRL1    0x0f39
#define    RTL8370_SVLAN_SP2C_ENTRY28_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY28_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY29_CTRL0    0x0f3a
#define    RTL8370_SVLAN_SP2C_ENTRY29_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY29_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY29_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY29_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY29_CTRL1    0x0f3b
#define    RTL8370_SVLAN_SP2C_ENTRY29_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY29_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY30_CTRL0    0x0f3c
#define    RTL8370_SVLAN_SP2C_ENTRY30_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY30_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY30_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY30_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY30_CTRL1    0x0f3d
#define    RTL8370_SVLAN_SP2C_ENTRY30_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY30_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY31_CTRL0    0x0f3e
#define    RTL8370_SVLAN_SP2C_ENTRY31_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY31_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY31_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY31_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY31_CTRL1    0x0f3f
#define    RTL8370_SVLAN_SP2C_ENTRY31_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY31_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY32_CTRL0    0x0f40
#define    RTL8370_SVLAN_SP2C_ENTRY32_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY32_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY32_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY32_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY32_CTRL1    0x0f41
#define    RTL8370_SVLAN_SP2C_ENTRY32_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY32_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY33_CTRL0    0x0f42
#define    RTL8370_SVLAN_SP2C_ENTRY33_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY33_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY33_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY33_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY33_CTRL1    0x0f43
#define    RTL8370_SVLAN_SP2C_ENTRY33_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY33_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY34_CTRL0    0x0f44
#define    RTL8370_SVLAN_SP2C_ENTRY34_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY34_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY34_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY34_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY34_CTRL1    0x0f45
#define    RTL8370_SVLAN_SP2C_ENTRY34_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY34_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY35_CTRL0    0x0f46
#define    RTL8370_SVLAN_SP2C_ENTRY35_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY35_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY35_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY35_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY35_CTRL1    0x0f47
#define    RTL8370_SVLAN_SP2C_ENTRY35_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY35_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY36_CTRL0    0x0f48
#define    RTL8370_SVLAN_SP2C_ENTRY36_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY36_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY36_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY36_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY36_CTRL1    0x0f49
#define    RTL8370_SVLAN_SP2C_ENTRY36_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY36_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY37_CTRL0    0x0f4a
#define    RTL8370_SVLAN_SP2C_ENTRY37_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY37_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY37_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY37_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY37_CTRL1    0x0f4b
#define    RTL8370_SVLAN_SP2C_ENTRY37_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY37_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY38_CTRL0    0x0f4c
#define    RTL8370_SVLAN_SP2C_ENTRY38_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY38_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY38_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY38_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY38_CTRL1    0x0f4d
#define    RTL8370_SVLAN_SP2C_ENTRY38_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY38_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY39_CTRL0    0x0f4e
#define    RTL8370_SVLAN_SP2C_ENTRY39_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY39_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY39_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY39_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY39_CTRL1    0x0f4f
#define    RTL8370_SVLAN_SP2C_ENTRY39_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY39_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY40_CTRL0    0x0f50
#define    RTL8370_SVLAN_SP2C_ENTRY40_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY40_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY40_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY40_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY40_CTRL1    0x0f51
#define    RTL8370_SVLAN_SP2C_ENTRY40_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY40_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY41_CTRL0    0x0f52
#define    RTL8370_SVLAN_SP2C_ENTRY41_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY41_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY41_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY41_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY41_CTRL1    0x0f53
#define    RTL8370_SVLAN_SP2C_ENTRY41_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY41_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY42_CTRL0    0x0f54
#define    RTL8370_SVLAN_SP2C_ENTRY42_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY42_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY42_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY42_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY42_CTRL1    0x0f55
#define    RTL8370_SVLAN_SP2C_ENTRY42_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY42_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY43_CTRL0    0x0f56
#define    RTL8370_SVLAN_SP2C_ENTRY43_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY43_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY43_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY43_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY43_CTRL1    0x0f57
#define    RTL8370_SVLAN_SP2C_ENTRY43_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY43_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY44_CTRL0    0x0f58
#define    RTL8370_SVLAN_SP2C_ENTRY44_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY44_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY44_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY44_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY44_CTRL1    0x0f59
#define    RTL8370_SVLAN_SP2C_ENTRY44_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY44_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY45_CTRL0    0x0f5a
#define    RTL8370_SVLAN_SP2C_ENTRY45_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY45_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY45_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY45_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY45_CTRL1    0x0f5b
#define    RTL8370_SVLAN_SP2C_ENTRY45_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY45_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY46_CTRL0    0x0f5c
#define    RTL8370_SVLAN_SP2C_ENTRY46_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY46_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY46_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY46_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY46_CTRL1    0x0f5d
#define    RTL8370_SVLAN_SP2C_ENTRY46_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY46_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY47_CTRL0    0x0f5e
#define    RTL8370_SVLAN_SP2C_ENTRY47_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY47_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY47_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY47_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY47_CTRL1    0x0f5f
#define    RTL8370_SVLAN_SP2C_ENTRY47_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY47_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY48_CTRL0    0x0f60
#define    RTL8370_SVLAN_SP2C_ENTRY48_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY48_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY48_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY48_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY48_CTRL1    0x0f61
#define    RTL8370_SVLAN_SP2C_ENTRY48_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY48_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY49_CTRL0    0x0f62
#define    RTL8370_SVLAN_SP2C_ENTRY49_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY49_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY49_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY49_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY49_CTRL1    0x0f63
#define    RTL8370_SVLAN_SP2C_ENTRY49_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY49_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY50_CTRL0    0x0f64
#define    RTL8370_SVLAN_SP2C_ENTRY50_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY50_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY50_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY50_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY50_CTRL1    0x0f65
#define    RTL8370_SVLAN_SP2C_ENTRY50_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY50_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY51_CTRL0    0x0f66
#define    RTL8370_SVLAN_SP2C_ENTRY51_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY51_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY51_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY51_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY51_CTRL1    0x0f67
#define    RTL8370_SVLAN_SP2C_ENTRY51_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY51_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY52_CTRL0    0x0f68
#define    RTL8370_SVLAN_SP2C_ENTRY52_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY52_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY52_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY52_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY52_CTRL1    0x0f69
#define    RTL8370_SVLAN_SP2C_ENTRY52_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY52_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY53_CTRL0    0x0f6a
#define    RTL8370_SVLAN_SP2C_ENTRY53_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY53_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY53_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY53_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY53_CTRL1    0x0f6b
#define    RTL8370_SVLAN_SP2C_ENTRY53_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY53_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY54_CTRL0    0x0f6c
#define    RTL8370_SVLAN_SP2C_ENTRY54_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY54_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY54_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY54_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY54_CTRL1    0x0f6d
#define    RTL8370_SVLAN_SP2C_ENTRY54_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY54_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY55_CTRL0    0x0f6e
#define    RTL8370_SVLAN_SP2C_ENTRY55_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY55_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY55_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY55_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY55_CTRL1    0x0f6f
#define    RTL8370_SVLAN_SP2C_ENTRY55_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY55_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY56_CTRL0    0x0f70
#define    RTL8370_SVLAN_SP2C_ENTRY56_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY56_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY56_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY56_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY56_CTRL1    0x0f71
#define    RTL8370_SVLAN_SP2C_ENTRY56_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY56_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY57_CTRL0    0x0f72
#define    RTL8370_SVLAN_SP2C_ENTRY57_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY57_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY57_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY57_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY57_CTRL1    0x0f73
#define    RTL8370_SVLAN_SP2C_ENTRY57_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY57_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY58_CTRL0    0x0f74
#define    RTL8370_SVLAN_SP2C_ENTRY58_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY58_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY58_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY58_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY58_CTRL1    0x0f75
#define    RTL8370_SVLAN_SP2C_ENTRY58_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY58_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY59_CTRL0    0x0f76
#define    RTL8370_SVLAN_SP2C_ENTRY59_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY59_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY59_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY59_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY59_CTRL1    0x0f77
#define    RTL8370_SVLAN_SP2C_ENTRY59_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY59_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY60_CTRL0    0x0f78
#define    RTL8370_SVLAN_SP2C_ENTRY60_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY60_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY60_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY60_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY60_CTRL1    0x0f79
#define    RTL8370_SVLAN_SP2C_ENTRY60_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY60_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY61_CTRL0    0x0f7a
#define    RTL8370_SVLAN_SP2C_ENTRY61_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY61_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY61_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY61_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY61_CTRL1    0x0f7b
#define    RTL8370_SVLAN_SP2C_ENTRY61_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY61_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY62_CTRL0    0x0f7c
#define    RTL8370_SVLAN_SP2C_ENTRY62_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY62_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY62_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY62_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY62_CTRL1    0x0f7d
#define    RTL8370_SVLAN_SP2C_ENTRY62_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY62_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY63_CTRL0    0x0f7e
#define    RTL8370_SVLAN_SP2C_ENTRY63_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY63_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY63_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY63_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY63_CTRL1    0x0f7f
#define    RTL8370_SVLAN_SP2C_ENTRY63_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY63_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY64_CTRL0    0x0f80
#define    RTL8370_SVLAN_SP2C_ENTRY64_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY64_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY64_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY64_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY64_CTRL1    0x0f81
#define    RTL8370_SVLAN_SP2C_ENTRY64_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY64_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY65_CTRL0    0x0f82
#define    RTL8370_SVLAN_SP2C_ENTRY65_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY65_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY65_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY65_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY65_CTRL1    0x0f83
#define    RTL8370_SVLAN_SP2C_ENTRY65_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY65_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY66_CTRL0    0x0f84
#define    RTL8370_SVLAN_SP2C_ENTRY66_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY66_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY66_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY66_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY66_CTRL1    0x0f85
#define    RTL8370_SVLAN_SP2C_ENTRY66_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY66_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY67_CTRL0    0x0f86
#define    RTL8370_SVLAN_SP2C_ENTRY67_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY67_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY67_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY67_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY67_CTRL1    0x0f87
#define    RTL8370_SVLAN_SP2C_ENTRY67_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY67_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY68_CTRL0    0x0f88
#define    RTL8370_SVLAN_SP2C_ENTRY68_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY68_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY68_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY68_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY68_CTRL1    0x0f89
#define    RTL8370_SVLAN_SP2C_ENTRY68_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY68_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY69_CTRL0    0x0f8a
#define    RTL8370_SVLAN_SP2C_ENTRY69_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY69_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY69_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY69_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY69_CTRL1    0x0f8b
#define    RTL8370_SVLAN_SP2C_ENTRY69_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY69_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY70_CTRL0    0x0f8c
#define    RTL8370_SVLAN_SP2C_ENTRY70_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY70_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY70_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY70_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY70_CTRL1    0x0f8d
#define    RTL8370_SVLAN_SP2C_ENTRY70_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY70_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY71_CTRL0    0x0f8e
#define    RTL8370_SVLAN_SP2C_ENTRY71_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY71_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY71_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY71_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY71_CTRL1    0x0f8f
#define    RTL8370_SVLAN_SP2C_ENTRY71_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY71_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY72_CTRL0    0x0f90
#define    RTL8370_SVLAN_SP2C_ENTRY72_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY72_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY72_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY72_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY72_CTRL1    0x0f91
#define    RTL8370_SVLAN_SP2C_ENTRY72_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY72_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY73_CTRL0    0x0f92
#define    RTL8370_SVLAN_SP2C_ENTRY73_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY73_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY73_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY73_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY73_CTRL1    0x0f93
#define    RTL8370_SVLAN_SP2C_ENTRY73_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY73_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY74_CTRL0    0x0f94
#define    RTL8370_SVLAN_SP2C_ENTRY74_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY74_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY74_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY74_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY74_CTRL1    0x0f95
#define    RTL8370_SVLAN_SP2C_ENTRY74_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY74_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY75_CTRL0    0x0f96
#define    RTL8370_SVLAN_SP2C_ENTRY75_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY75_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY75_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY75_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY75_CTRL1    0x0f97
#define    RTL8370_SVLAN_SP2C_ENTRY75_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY75_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY76_CTRL0    0x0f98
#define    RTL8370_SVLAN_SP2C_ENTRY76_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY76_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY76_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY76_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY76_CTRL1    0x0f99
#define    RTL8370_SVLAN_SP2C_ENTRY76_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY76_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY77_CTRL0    0x0f9a
#define    RTL8370_SVLAN_SP2C_ENTRY77_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY77_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY77_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY77_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY77_CTRL1    0x0f9b
#define    RTL8370_SVLAN_SP2C_ENTRY77_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY77_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY78_CTRL0    0x0f9c
#define    RTL8370_SVLAN_SP2C_ENTRY78_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY78_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY78_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY78_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY78_CTRL1    0x0f9d
#define    RTL8370_SVLAN_SP2C_ENTRY78_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY78_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY79_CTRL0    0x0f9e
#define    RTL8370_SVLAN_SP2C_ENTRY79_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY79_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY79_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY79_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY79_CTRL1    0x0f9f
#define    RTL8370_SVLAN_SP2C_ENTRY79_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY79_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY80_CTRL0    0x0fa0
#define    RTL8370_SVLAN_SP2C_ENTRY80_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY80_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY80_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY80_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY80_CTRL1    0x0fa1
#define    RTL8370_SVLAN_SP2C_ENTRY80_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY80_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY81_CTRL0    0x0fa2
#define    RTL8370_SVLAN_SP2C_ENTRY81_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY81_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY81_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY81_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY81_CTRL1    0x0fa3
#define    RTL8370_SVLAN_SP2C_ENTRY81_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY81_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY82_CTRL0    0x0fa4
#define    RTL8370_SVLAN_SP2C_ENTRY82_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY82_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY82_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY82_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY82_CTRL1    0x0fa5
#define    RTL8370_SVLAN_SP2C_ENTRY82_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY82_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY83_CTRL0    0x0fa6
#define    RTL8370_SVLAN_SP2C_ENTRY83_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY83_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY83_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY83_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY83_CTRL1    0x0fa7
#define    RTL8370_SVLAN_SP2C_ENTRY83_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY83_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY84_CTRL0    0x0fa8
#define    RTL8370_SVLAN_SP2C_ENTRY84_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY84_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY84_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY84_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY84_CTRL1    0x0fa9
#define    RTL8370_SVLAN_SP2C_ENTRY84_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY84_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY85_CTRL0    0x0faa
#define    RTL8370_SVLAN_SP2C_ENTRY85_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY85_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY85_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY85_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY85_CTRL1    0x0fab
#define    RTL8370_SVLAN_SP2C_ENTRY85_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY85_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY86_CTRL0    0x0fac
#define    RTL8370_SVLAN_SP2C_ENTRY86_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY86_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY86_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY86_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY86_CTRL1    0x0fad
#define    RTL8370_SVLAN_SP2C_ENTRY86_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY86_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY87_CTRL0    0x0fae
#define    RTL8370_SVLAN_SP2C_ENTRY87_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY87_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY87_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY87_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY87_CTRL1    0x0faf
#define    RTL8370_SVLAN_SP2C_ENTRY87_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY87_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY88_CTRL0    0x0fb0
#define    RTL8370_SVLAN_SP2C_ENTRY88_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY88_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY88_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY88_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY88_CTRL1    0x0fb1
#define    RTL8370_SVLAN_SP2C_ENTRY88_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY88_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY89_CTRL0    0x0fb2
#define    RTL8370_SVLAN_SP2C_ENTRY89_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY89_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY89_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY89_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY89_CTRL1    0x0fb3
#define    RTL8370_SVLAN_SP2C_ENTRY89_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY89_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY90_CTRL0    0x0fb4
#define    RTL8370_SVLAN_SP2C_ENTRY90_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY90_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY90_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY90_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY90_CTRL1    0x0fb5
#define    RTL8370_SVLAN_SP2C_ENTRY90_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY90_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY91_CTRL0    0x0fb6
#define    RTL8370_SVLAN_SP2C_ENTRY91_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY91_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY91_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY91_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY91_CTRL1    0x0fb7
#define    RTL8370_SVLAN_SP2C_ENTRY91_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY91_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY92_CTRL0    0x0fb8
#define    RTL8370_SVLAN_SP2C_ENTRY92_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY92_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY92_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY92_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY92_CTRL1    0x0fb9
#define    RTL8370_SVLAN_SP2C_ENTRY92_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY92_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY93_CTRL0    0x0fba
#define    RTL8370_SVLAN_SP2C_ENTRY93_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY93_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY93_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY93_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY93_CTRL1    0x0fbb
#define    RTL8370_SVLAN_SP2C_ENTRY93_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY93_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY94_CTRL0    0x0fbc
#define    RTL8370_SVLAN_SP2C_ENTRY94_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY94_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY94_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY94_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY94_CTRL1    0x0fbd
#define    RTL8370_SVLAN_SP2C_ENTRY94_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY94_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY95_CTRL0    0x0fbe
#define    RTL8370_SVLAN_SP2C_ENTRY95_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY95_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY95_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY95_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY95_CTRL1    0x0fbf
#define    RTL8370_SVLAN_SP2C_ENTRY95_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY95_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY96_CTRL0    0x0fc0
#define    RTL8370_SVLAN_SP2C_ENTRY96_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY96_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY96_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY96_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY96_CTRL1    0x0fc1
#define    RTL8370_SVLAN_SP2C_ENTRY96_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY96_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY97_CTRL0    0x0fc2
#define    RTL8370_SVLAN_SP2C_ENTRY97_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY97_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY97_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY97_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY97_CTRL1    0x0fc3
#define    RTL8370_SVLAN_SP2C_ENTRY97_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY97_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY98_CTRL0    0x0fc4
#define    RTL8370_SVLAN_SP2C_ENTRY98_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY98_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY98_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY98_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY98_CTRL1    0x0fc5
#define    RTL8370_SVLAN_SP2C_ENTRY98_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY98_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY99_CTRL0    0x0fc6
#define    RTL8370_SVLAN_SP2C_ENTRY99_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY99_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY99_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY99_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY99_CTRL1    0x0fc7
#define    RTL8370_SVLAN_SP2C_ENTRY99_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY99_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY100_CTRL0    0x0fc8
#define    RTL8370_SVLAN_SP2C_ENTRY100_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY100_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY100_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY100_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY100_CTRL1    0x0fc9
#define    RTL8370_SVLAN_SP2C_ENTRY100_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY100_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY101_CTRL0    0x0fca
#define    RTL8370_SVLAN_SP2C_ENTRY101_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY101_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY101_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY101_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY101_CTRL1    0x0fcb
#define    RTL8370_SVLAN_SP2C_ENTRY101_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY101_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY102_CTRL0    0x0fcc
#define    RTL8370_SVLAN_SP2C_ENTRY102_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY102_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY102_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY102_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY102_CTRL1    0x0fcd
#define    RTL8370_SVLAN_SP2C_ENTRY102_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY102_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY103_CTRL0    0x0fce
#define    RTL8370_SVLAN_SP2C_ENTRY103_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY103_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY103_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY103_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY103_CTRL1    0x0fcf
#define    RTL8370_SVLAN_SP2C_ENTRY103_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY103_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY104_CTRL0    0x0fd0
#define    RTL8370_SVLAN_SP2C_ENTRY104_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY104_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY104_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY104_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY104_CTRL1    0x0fd1
#define    RTL8370_SVLAN_SP2C_ENTRY104_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY104_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY105_CTRL0    0x0fd2
#define    RTL8370_SVLAN_SP2C_ENTRY105_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY105_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY105_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY105_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY105_CTRL1    0x0fd3
#define    RTL8370_SVLAN_SP2C_ENTRY105_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY105_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY106_CTRL0    0x0fd4
#define    RTL8370_SVLAN_SP2C_ENTRY106_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY106_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY106_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY106_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY106_CTRL1    0x0fd5
#define    RTL8370_SVLAN_SP2C_ENTRY106_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY106_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY107_CTRL0    0x0fd6
#define    RTL8370_SVLAN_SP2C_ENTRY107_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY107_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY107_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY107_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY107_CTRL1    0x0fd7
#define    RTL8370_SVLAN_SP2C_ENTRY107_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY107_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY108_CTRL0    0x0fd8
#define    RTL8370_SVLAN_SP2C_ENTRY108_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY108_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY108_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY108_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY108_CTRL1    0x0fd9
#define    RTL8370_SVLAN_SP2C_ENTRY108_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY108_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY109_CTRL0    0x0fda
#define    RTL8370_SVLAN_SP2C_ENTRY109_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY109_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY109_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY109_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY109_CTRL1    0x0fdb
#define    RTL8370_SVLAN_SP2C_ENTRY109_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY109_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY110_CTRL0    0x0fdc
#define    RTL8370_SVLAN_SP2C_ENTRY110_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY110_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY110_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY110_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY110_CTRL1    0x0fdd
#define    RTL8370_SVLAN_SP2C_ENTRY110_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY110_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY111_CTRL0    0x0fde
#define    RTL8370_SVLAN_SP2C_ENTRY111_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY111_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY111_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY111_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY111_CTRL1    0x0fdf
#define    RTL8370_SVLAN_SP2C_ENTRY111_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY111_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY112_CTRL0    0x0fe0
#define    RTL8370_SVLAN_SP2C_ENTRY112_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY112_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY112_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY112_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY112_CTRL1    0x0fe1
#define    RTL8370_SVLAN_SP2C_ENTRY112_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY112_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY113_CTRL0    0x0fe2
#define    RTL8370_SVLAN_SP2C_ENTRY113_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY113_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY113_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY113_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY113_CTRL1    0x0fe3
#define    RTL8370_SVLAN_SP2C_ENTRY113_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY113_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY114_CTRL0    0x0fe4
#define    RTL8370_SVLAN_SP2C_ENTRY114_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY114_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY114_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY114_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY114_CTRL1    0x0fe5
#define    RTL8370_SVLAN_SP2C_ENTRY114_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY114_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY115_CTRL0    0x0fe6
#define    RTL8370_SVLAN_SP2C_ENTRY115_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY115_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY115_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY115_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY115_CTRL1    0x0fe7
#define    RTL8370_SVLAN_SP2C_ENTRY115_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY115_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY116_CTRL0    0x0fe8
#define    RTL8370_SVLAN_SP2C_ENTRY116_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY116_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY116_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY116_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY116_CTRL1    0x0fe9
#define    RTL8370_SVLAN_SP2C_ENTRY116_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY116_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY117_CTRL0    0x0fea
#define    RTL8370_SVLAN_SP2C_ENTRY117_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY117_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY117_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY117_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY117_CTRL1    0x0feb
#define    RTL8370_SVLAN_SP2C_ENTRY117_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY117_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY118_CTRL0    0x0fec
#define    RTL8370_SVLAN_SP2C_ENTRY118_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY118_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY118_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY118_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY118_CTRL1    0x0fed
#define    RTL8370_SVLAN_SP2C_ENTRY118_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY118_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY119_CTRL0    0x0fee
#define    RTL8370_SVLAN_SP2C_ENTRY119_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY119_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY119_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY119_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY119_CTRL1    0x0fef
#define    RTL8370_SVLAN_SP2C_ENTRY119_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY119_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY120_CTRL0    0x0ff0
#define    RTL8370_SVLAN_SP2C_ENTRY120_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY120_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY120_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY120_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY120_CTRL1    0x0ff1
#define    RTL8370_SVLAN_SP2C_ENTRY120_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY120_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY121_CTRL0    0x0ff2
#define    RTL8370_SVLAN_SP2C_ENTRY121_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY121_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY121_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY121_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY121_CTRL1    0x0ff3
#define    RTL8370_SVLAN_SP2C_ENTRY121_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY121_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY122_CTRL0    0x0ff4
#define    RTL8370_SVLAN_SP2C_ENTRY122_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY122_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY122_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY122_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY122_CTRL1    0x0ff5
#define    RTL8370_SVLAN_SP2C_ENTRY122_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY122_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY123_CTRL0    0x0ff6
#define    RTL8370_SVLAN_SP2C_ENTRY123_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY123_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY123_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY123_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY123_CTRL1    0x0ff7
#define    RTL8370_SVLAN_SP2C_ENTRY123_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY123_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY124_CTRL0    0x0ff8
#define    RTL8370_SVLAN_SP2C_ENTRY124_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY124_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY124_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY124_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY124_CTRL1    0x0ff9
#define    RTL8370_SVLAN_SP2C_ENTRY124_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY124_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY125_CTRL0    0x0ffa
#define    RTL8370_SVLAN_SP2C_ENTRY125_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY125_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY125_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY125_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY125_CTRL1    0x0ffb
#define    RTL8370_SVLAN_SP2C_ENTRY125_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY125_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY126_CTRL0    0x0ffc
#define    RTL8370_SVLAN_SP2C_ENTRY126_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY126_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY126_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY126_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY126_CTRL1    0x0ffd
#define    RTL8370_SVLAN_SP2C_ENTRY126_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY126_CTRL1_MASK    0x1FFF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY127_CTRL0    0x0ffe
#define    RTL8370_SVLAN_SP2C_ENTRY127_CTRL0_SVID_OFFSET    4
#define    RTL8370_SVLAN_SP2C_ENTRY127_CTRL0_SVID_MASK    0xFFF0
#define    RTL8370_SVLAN_SP2C_ENTRY127_CTRL0_DST_PORT_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY127_CTRL0_DST_PORT_MASK    0xF

#define    RTL8370_REG_SVLAN_SP2C_ENTRY127_CTRL1    0x0fff
#define    RTL8370_SVLAN_SP2C_ENTRY127_CTRL1_OFFSET    0
#define    RTL8370_SVLAN_SP2C_ENTRY127_CTRL1_MASK    0x1FFF

/* (16'h1000) mib_reg */

#define    RTL8370_REG_MIB_COUNTER0    0x1000

#define    RTL8370_REG_MIB_COUNTER1    0x1001

#define    RTL8370_REG_MIB_COUNTER2    0x1002

#define    RTL8370_REG_MIB_COUNTER3    0x1003

#define    RTL8370_REG_MIB_ADDRESS    0x1004
#define    RTL8370_MIB_ADDRESS_OFFSET    0
#define    RTL8370_MIB_ADDRESS_MASK    0x1FF

#define    RTL8370_REG_MIB_CTRL0    0x1005
#define    RTL8370_GLOBAL_RESET_OFFSET    11
#define    RTL8370_GLOBAL_RESET_MASK    0x800
#define    RTL8370_QM_RESET_OFFSET    10
#define    RTL8370_QM_RESET_MASK    0x400
#define    RTL8370_PORT7_RESET_OFFSET    9
#define    RTL8370_PORT7_RESET_MASK    0x200
#define    RTL8370_PORT6_RESET_OFFSET    8
#define    RTL8370_PORT6_RESET_MASK    0x100
#define    RTL8370_PORT5_RESET_OFFSET    7
#define    RTL8370_PORT5_RESET_MASK    0x80
#define    RTL8370_PORT4_RESET_OFFSET    6
#define    RTL8370_PORT4_RESET_MASK    0x40
#define    RTL8370_PORT3_RESET_OFFSET    5
#define    RTL8370_PORT3_RESET_MASK    0x20
#define    RTL8370_PORT2_RESET_OFFSET    4
#define    RTL8370_PORT2_RESET_MASK    0x10
#define    RTL8370_PORT1_RESET_OFFSET    3
#define    RTL8370_PORT1_RESET_MASK    0x8
#define    RTL8370_PORT0_RESET_OFFSET    2
#define    RTL8370_PORT0_RESET_MASK    0x4
#define    RTL8370_RESET_FLAG_OFFSET    1
#define    RTL8370_RESET_FLAG_MASK    0x2
#define    RTL8370_BUSY_FLAG_OFFSET    0
#define    RTL8370_BUSY_FLAG_MASK    0x1

#define    RTL8370_REG_MIB_CTRL1    0x1006
#define    RTL8370_PORT15_RESET_OFFSET    9
#define    RTL8370_PORT15_RESET_MASK    0x200
#define    RTL8370_PORT14_RESET_OFFSET    8
#define    RTL8370_PORT14_RESET_MASK    0x100
#define    RTL8370_PORT13_RESET_OFFSET    7
#define    RTL8370_PORT13_RESET_MASK    0x80
#define    RTL8370_PORT12_RESET_OFFSET    6
#define    RTL8370_PORT12_RESET_MASK    0x40
#define    RTL8370_PORT11_RESET_OFFSET    5
#define    RTL8370_PORT11_RESET_MASK    0x20
#define    RTL8370_PORT10_RESET_OFFSET    4
#define    RTL8370_PORT10_RESET_MASK    0x10
#define    RTL8370_PORT9_RESET_OFFSET    3
#define    RTL8370_PORT9_RESET_MASK    0x8
#define    RTL8370_PORT8_RESET_OFFSET    2
#define    RTL8370_PORT8_RESET_MASK    0x4

/* (16'h1100) intrpt_reg */

#define    RTL8370_REG_INTR_CTRL    0x1100
#define    RTL8370_INTR_POLARITY_8051_OFFSET    1
#define    RTL8370_INTR_POLARITY_8051_MASK    0x2
#define    RTL8370_INTR_POLARITY_OFFSET    0
#define    RTL8370_INTR_POLARITY_MASK    0x1

#define    RTL8370_REG_INTR_IMR    0x1101
#define    RTL8370_INTR_IMR_DUMMY_0_OFFSET    8
#define    RTL8370_INTR_IMR_DUMMY_0_MASK    0xFF00
#define    RTL8370_INTR_IMR_INTERRUPT_8051_OFFSET    7
#define    RTL8370_INTR_IMR_INTERRUPT_8051_MASK    0x80
#define    RTL8370_INTR_IMR_LOOP_DETECTION_OFFSET    6
#define    RTL8370_INTR_IMR_LOOP_DETECTION_MASK    0x40
#define    RTL8370_INTR_IMR_GREEN_TIMER_OFFSET    5
#define    RTL8370_INTR_IMR_GREEN_TIMER_MASK    0x20
#define    RTL8370_INTR_IMR_SPECIAL_CONGEST_OFFSET    4
#define    RTL8370_INTR_IMR_SPECIAL_CONGEST_MASK    0x10
#define    RTL8370_INTR_IMR_SPEED_CHANGE_OFFSET    3
#define    RTL8370_INTR_IMR_SPEED_CHANGE_MASK    0x8
#define    RTL8370_INTR_IMR_LEARN_OVER_OFFSET    2
#define    RTL8370_INTR_IMR_LEARN_OVER_MASK    0x4
#define    RTL8370_INTR_IMR_METER_EXCEEDED_OFFSET    1
#define    RTL8370_INTR_IMR_METER_EXCEEDED_MASK    0x2
#define    RTL8370_INTR_IMR_LINK_CHANGE_OFFSET    0
#define    RTL8370_INTR_IMR_LINK_CHANGE_MASK    0x1

#define    RTL8370_REG_INTR_IMS    0x1102
#define    RTL8370_INTR_IMS_INTERRUPT_8051_OFFSET    7
#define    RTL8370_INTR_IMS_INTERRUPT_8051_MASK    0x80
#define    RTL8370_INTR_IMS_LOOP_DETECTION_OFFSET    6
#define    RTL8370_INTR_IMS_LOOP_DETECTION_MASK    0x40
#define    RTL8370_INTR_IMS_GREEN_TIMER_OFFSET    5
#define    RTL8370_INTR_IMS_GREEN_TIMER_MASK    0x20
#define    RTL8370_INTR_IMS_SPECIAL_CONGEST_OFFSET    4
#define    RTL8370_INTR_IMS_SPECIAL_CONGEST_MASK    0x10
#define    RTL8370_INTR_IMS_SPEED_CHANGE_OFFSET    3
#define    RTL8370_INTR_IMS_SPEED_CHANGE_MASK    0x8
#define    RTL8370_INTR_IMS_LEARN_OVER_OFFSET    2
#define    RTL8370_INTR_IMS_LEARN_OVER_MASK    0x4
#define    RTL8370_INTR_IMS_METER_EXCEEDED_OFFSET    1
#define    RTL8370_INTR_IMS_METER_EXCEEDED_MASK    0x2
#define    RTL8370_INTR_IMS_LINK_CHANGE_OFFSET    0
#define    RTL8370_INTR_IMS_LINK_CHANGE_MASK    0x1

#define    RTL8370_REG_LEARN_OVER_INDICATOR    0x1103

#define    RTL8370_REG_SPEED_CHANGE_INDICATOR    0x1104

#define    RTL8370_REG_SPECIAL_CONGEST_INDICATOR    0x1105

#define    RTL8370_REG_PORT_LINKDOWN_INDICATOR    0x1106

#define    RTL8370_REG_PORT_LINKUP_INDICATOR    0x1107

#define    RTL8370_REG_METER_EXCEED_INDICATOR0    0x1108
#define    RTL8370_METER15_OFFSET    15
#define    RTL8370_METER15_MASK    0x8000
#define    RTL8370_METER14_OFFSET    14
#define    RTL8370_METER14_MASK    0x4000
#define    RTL8370_METER13_OFFSET    13
#define    RTL8370_METER13_MASK    0x2000
#define    RTL8370_METER12_OFFSET    12
#define    RTL8370_METER12_MASK    0x1000
#define    RTL8370_METER11_OFFSET    11
#define    RTL8370_METER11_MASK    0x800
#define    RTL8370_METER10_OFFSET    10
#define    RTL8370_METER10_MASK    0x400
#define    RTL8370_METER9_OFFSET    9
#define    RTL8370_METER9_MASK    0x200
#define    RTL8370_METER8_OFFSET    8
#define    RTL8370_METER8_MASK    0x100
#define    RTL8370_METER7_OFFSET    7
#define    RTL8370_METER7_MASK    0x80
#define    RTL8370_METER6_OFFSET    6
#define    RTL8370_METER6_MASK    0x40
#define    RTL8370_METER5_OFFSET    5
#define    RTL8370_METER5_MASK    0x20
#define    RTL8370_METER4_OFFSET    4
#define    RTL8370_METER4_MASK    0x10
#define    RTL8370_METER3_OFFSET    3
#define    RTL8370_METER3_MASK    0x8
#define    RTL8370_METER2_OFFSET    2
#define    RTL8370_METER2_MASK    0x4
#define    RTL8370_METER1_OFFSET    1
#define    RTL8370_METER1_MASK    0x2
#define    RTL8370_METER0_OFFSET    0
#define    RTL8370_METER0_MASK    0x1

#define    RTL8370_REG_METER_EXCEED_INDICATOR1    0x1109
#define    RTL8370_METER31_OFFSET    15
#define    RTL8370_METER31_MASK    0x8000
#define    RTL8370_METER30_OFFSET    14
#define    RTL8370_METER30_MASK    0x4000
#define    RTL8370_METER29_OFFSET    13
#define    RTL8370_METER29_MASK    0x2000
#define    RTL8370_METER28_OFFSET    12
#define    RTL8370_METER28_MASK    0x1000
#define    RTL8370_METER27_OFFSET    11
#define    RTL8370_METER27_MASK    0x800
#define    RTL8370_METER26_OFFSET    10
#define    RTL8370_METER26_MASK    0x400
#define    RTL8370_METER25_OFFSET    9
#define    RTL8370_METER25_MASK    0x200
#define    RTL8370_METER24_OFFSET    8
#define    RTL8370_METER24_MASK    0x100
#define    RTL8370_METER23_OFFSET    7
#define    RTL8370_METER23_MASK    0x80
#define    RTL8370_METER22_OFFSET    6
#define    RTL8370_METER22_MASK    0x40
#define    RTL8370_METER21_OFFSET    5
#define    RTL8370_METER21_MASK    0x20
#define    RTL8370_METER20_OFFSET    4
#define    RTL8370_METER20_MASK    0x10
#define    RTL8370_METER19_OFFSET    3
#define    RTL8370_METER19_MASK    0x8
#define    RTL8370_METER18_OFFSET    2
#define    RTL8370_METER18_MASK    0x4
#define    RTL8370_METER17_OFFSET    1
#define    RTL8370_METER17_MASK    0x2
#define    RTL8370_METER16_OFFSET    0
#define    RTL8370_METER16_MASK    0x1

#define    RTL8370_REG_METER_EXCEED_INDICATOR2    0x110a
#define    RTL8370_METER47_OFFSET    15
#define    RTL8370_METER47_MASK    0x8000
#define    RTL8370_METER46_OFFSET    14
#define    RTL8370_METER46_MASK    0x4000
#define    RTL8370_METER45_OFFSET    13
#define    RTL8370_METER45_MASK    0x2000
#define    RTL8370_METER44_OFFSET    12
#define    RTL8370_METER44_MASK    0x1000
#define    RTL8370_METER43_OFFSET    11
#define    RTL8370_METER43_MASK    0x800
#define    RTL8370_METER42_OFFSET    10
#define    RTL8370_METER42_MASK    0x400
#define    RTL8370_METER41_OFFSET    9
#define    RTL8370_METER41_MASK    0x200
#define    RTL8370_METER40_OFFSET    8
#define    RTL8370_METER40_MASK    0x100
#define    RTL8370_METER39_OFFSET    7
#define    RTL8370_METER39_MASK    0x80
#define    RTL8370_METER38_OFFSET    6
#define    RTL8370_METER38_MASK    0x40
#define    RTL8370_METER37_OFFSET    5
#define    RTL8370_METER37_MASK    0x20
#define    RTL8370_METER36_OFFSET    4
#define    RTL8370_METER36_MASK    0x10
#define    RTL8370_METER35_OFFSET    3
#define    RTL8370_METER35_MASK    0x8
#define    RTL8370_METER34_OFFSET    2
#define    RTL8370_METER34_MASK    0x4
#define    RTL8370_METER33_OFFSET    1
#define    RTL8370_METER33_MASK    0x2
#define    RTL8370_METER32_OFFSET    0
#define    RTL8370_METER32_MASK    0x1

#define    RTL8370_REG_METER_EXCEED_INDICATOR3    0x110b
#define    RTL8370_METER63_OFFSET    15
#define    RTL8370_METER63_MASK    0x8000
#define    RTL8370_METER62_OFFSET    14
#define    RTL8370_METER62_MASK    0x4000
#define    RTL8370_METER61_OFFSET    13
#define    RTL8370_METER61_MASK    0x2000
#define    RTL8370_METER60_OFFSET    12
#define    RTL8370_METER60_MASK    0x1000
#define    RTL8370_METER59_OFFSET    11
#define    RTL8370_METER59_MASK    0x800
#define    RTL8370_METER58_OFFSET    10
#define    RTL8370_METER58_MASK    0x400
#define    RTL8370_METER57_OFFSET    9
#define    RTL8370_METER57_MASK    0x200
#define    RTL8370_METER56_OFFSET    8
#define    RTL8370_METER56_MASK    0x100
#define    RTL8370_METER55_OFFSET    7
#define    RTL8370_METER55_MASK    0x80
#define    RTL8370_METER54_OFFSET    6
#define    RTL8370_METER54_MASK    0x40
#define    RTL8370_METER53_OFFSET    5
#define    RTL8370_METER53_MASK    0x20
#define    RTL8370_METER52_OFFSET    4
#define    RTL8370_METER52_MASK    0x10
#define    RTL8370_METER51_OFFSET    3
#define    RTL8370_METER51_MASK    0x8
#define    RTL8370_METER50_OFFSET    2
#define    RTL8370_METER50_MASK    0x4
#define    RTL8370_METER49_OFFSET    1
#define    RTL8370_METER49_MASK    0x2
#define    RTL8370_METER48_OFFSET    0
#define    RTL8370_METER48_MASK    0x1

#define    RTL8370_REG_METER_EXCEED_INDICATOR4    0x110c
#define    RTL8370_METER79_OFFSET    15
#define    RTL8370_METER79_MASK    0x8000
#define    RTL8370_METER78_OFFSET    14
#define    RTL8370_METER78_MASK    0x4000
#define    RTL8370_METER77_OFFSET    13
#define    RTL8370_METER77_MASK    0x2000
#define    RTL8370_METER76_OFFSET    12
#define    RTL8370_METER76_MASK    0x1000
#define    RTL8370_METER75_OFFSET    11
#define    RTL8370_METER75_MASK    0x800
#define    RTL8370_METER74_OFFSET    10
#define    RTL8370_METER74_MASK    0x400
#define    RTL8370_METER73_OFFSET    9
#define    RTL8370_METER73_MASK    0x200
#define    RTL8370_METER72_OFFSET    8
#define    RTL8370_METER72_MASK    0x100
#define    RTL8370_METER71_OFFSET    7
#define    RTL8370_METER71_MASK    0x80
#define    RTL8370_METER70_OFFSET    6
#define    RTL8370_METER70_MASK    0x40
#define    RTL8370_METER69_OFFSET    5
#define    RTL8370_METER69_MASK    0x20
#define    RTL8370_METER68_OFFSET    4
#define    RTL8370_METER68_MASK    0x10
#define    RTL8370_METER67_OFFSET    3
#define    RTL8370_METER67_MASK    0x8
#define    RTL8370_METER66_OFFSET    2
#define    RTL8370_METER66_MASK    0x4
#define    RTL8370_METER65_OFFSET    1
#define    RTL8370_METER65_MASK    0x2
#define    RTL8370_METER64_OFFSET    0
#define    RTL8370_METER64_MASK    0x1

#define    RTL8370_REG_METER_EXCEED_INDICATOR5    0x110d
#define    RTL8370_METER95_OFFSET    15
#define    RTL8370_METER95_MASK    0x8000
#define    RTL8370_METER94_OFFSET    14
#define    RTL8370_METER94_MASK    0x4000
#define    RTL8370_METER93_OFFSET    13
#define    RTL8370_METER93_MASK    0x2000
#define    RTL8370_METER92_OFFSET    12
#define    RTL8370_METER92_MASK    0x1000
#define    RTL8370_METER91_OFFSET    11
#define    RTL8370_METER91_MASK    0x800
#define    RTL8370_METER90_OFFSET    10
#define    RTL8370_METER90_MASK    0x400
#define    RTL8370_METER89_OFFSET    9
#define    RTL8370_METER89_MASK    0x200
#define    RTL8370_METER88_OFFSET    8
#define    RTL8370_METER88_MASK    0x100
#define    RTL8370_METER87_OFFSET    7
#define    RTL8370_METER87_MASK    0x80
#define    RTL8370_METER86_OFFSET    6
#define    RTL8370_METER86_MASK    0x40
#define    RTL8370_METER85_OFFSET    5
#define    RTL8370_METER85_MASK    0x20
#define    RTL8370_METER84_OFFSET    4
#define    RTL8370_METER84_MASK    0x10
#define    RTL8370_METER83_OFFSET    3
#define    RTL8370_METER83_MASK    0x8
#define    RTL8370_METER82_OFFSET    2
#define    RTL8370_METER82_MASK    0x4
#define    RTL8370_METER81_OFFSET    1
#define    RTL8370_METER81_MASK    0x2
#define    RTL8370_METER80_OFFSET    0
#define    RTL8370_METER80_MASK    0x1

#define    RTL8370_REG_METER_EXCEED_INDICATOR6    0x110e
#define    RTL8370_METER111_OFFSET    15
#define    RTL8370_METER111_MASK    0x8000
#define    RTL8370_METER110_OFFSET    14
#define    RTL8370_METER110_MASK    0x4000
#define    RTL8370_METER109_OFFSET    13
#define    RTL8370_METER109_MASK    0x2000
#define    RTL8370_METER108_OFFSET    12
#define    RTL8370_METER108_MASK    0x1000
#define    RTL8370_METER107_OFFSET    11
#define    RTL8370_METER107_MASK    0x800
#define    RTL8370_METER106_OFFSET    10
#define    RTL8370_METER106_MASK    0x400
#define    RTL8370_METER105_OFFSET    9
#define    RTL8370_METER105_MASK    0x200
#define    RTL8370_METER104_OFFSET    8
#define    RTL8370_METER104_MASK    0x100
#define    RTL8370_METER103_OFFSET    7
#define    RTL8370_METER103_MASK    0x80
#define    RTL8370_METER102_OFFSET    6
#define    RTL8370_METER102_MASK    0x40
#define    RTL8370_METER101_OFFSET    5
#define    RTL8370_METER101_MASK    0x20
#define    RTL8370_METER100_OFFSET    4
#define    RTL8370_METER100_MASK    0x10
#define    RTL8370_METER99_OFFSET    3
#define    RTL8370_METER99_MASK    0x8
#define    RTL8370_METER98_OFFSET    2
#define    RTL8370_METER98_MASK    0x4
#define    RTL8370_METER97_OFFSET    1
#define    RTL8370_METER97_MASK    0x2
#define    RTL8370_METER96_OFFSET    0
#define    RTL8370_METER96_MASK    0x1

#define    RTL8370_REG_METER_EXCEED_INDICATOR7    0x110f
#define    RTL8370_METER127_OFFSET    15
#define    RTL8370_METER127_MASK    0x8000
#define    RTL8370_METER126_OFFSET    14
#define    RTL8370_METER126_MASK    0x4000
#define    RTL8370_METER125_OFFSET    13
#define    RTL8370_METER125_MASK    0x2000
#define    RTL8370_METER124_OFFSET    12
#define    RTL8370_METER124_MASK    0x1000
#define    RTL8370_METER123_OFFSET    11
#define    RTL8370_METER123_MASK    0x800
#define    RTL8370_METER122_OFFSET    10
#define    RTL8370_METER122_MASK    0x400
#define    RTL8370_METER121_OFFSET    9
#define    RTL8370_METER121_MASK    0x200
#define    RTL8370_METER120_OFFSET    8
#define    RTL8370_METER120_MASK    0x100
#define    RTL8370_METER119_OFFSET    7
#define    RTL8370_METER119_MASK    0x80
#define    RTL8370_METER118_OFFSET    6
#define    RTL8370_METER118_MASK    0x40
#define    RTL8370_METER117_OFFSET    5
#define    RTL8370_METER117_MASK    0x20
#define    RTL8370_METER116_OFFSET    4
#define    RTL8370_METER116_MASK    0x10
#define    RTL8370_METER115_OFFSET    3
#define    RTL8370_METER115_MASK    0x8
#define    RTL8370_METER114_OFFSET    2
#define    RTL8370_METER114_MASK    0x4
#define    RTL8370_METER113_OFFSET    1
#define    RTL8370_METER113_MASK    0x2
#define    RTL8370_METER112_OFFSET    0
#define    RTL8370_METER112_MASK    0x1

#define    RTL8370_REG_METER_EXCEED_INDICATOR8    0x1110
#define    RTL8370_METER143_OFFSET    15
#define    RTL8370_METER143_MASK    0x8000
#define    RTL8370_METER142_OFFSET    14
#define    RTL8370_METER142_MASK    0x4000
#define    RTL8370_METER141_OFFSET    13
#define    RTL8370_METER141_MASK    0x2000
#define    RTL8370_METER140_OFFSET    12
#define    RTL8370_METER140_MASK    0x1000
#define    RTL8370_METER139_OFFSET    11
#define    RTL8370_METER139_MASK    0x800
#define    RTL8370_METER138_OFFSET    10
#define    RTL8370_METER138_MASK    0x400
#define    RTL8370_METER137_OFFSET    9
#define    RTL8370_METER137_MASK    0x200
#define    RTL8370_METER136_OFFSET    8
#define    RTL8370_METER136_MASK    0x100
#define    RTL8370_METER135_OFFSET    7
#define    RTL8370_METER135_MASK    0x80
#define    RTL8370_METER134_OFFSET    6
#define    RTL8370_METER134_MASK    0x40
#define    RTL8370_METER133_OFFSET    5
#define    RTL8370_METER133_MASK    0x20
#define    RTL8370_METER132_OFFSET    4
#define    RTL8370_METER132_MASK    0x10
#define    RTL8370_METER131_OFFSET    3
#define    RTL8370_METER131_MASK    0x8
#define    RTL8370_METER130_OFFSET    2
#define    RTL8370_METER130_MASK    0x4
#define    RTL8370_METER129_OFFSET    1
#define    RTL8370_METER129_MASK    0x2
#define    RTL8370_METER128_OFFSET    0
#define    RTL8370_METER128_MASK    0x1

#define    RTL8370_REG_METER_EXCEED_INDICATOR9    0x1111
#define    RTL8370_METER159_OFFSET    15
#define    RTL8370_METER159_MASK    0x8000
#define    RTL8370_METER158_OFFSET    14
#define    RTL8370_METER158_MASK    0x4000
#define    RTL8370_METER157_OFFSET    13
#define    RTL8370_METER157_MASK    0x2000
#define    RTL8370_METER156_OFFSET    12
#define    RTL8370_METER156_MASK    0x1000
#define    RTL8370_METER155_OFFSET    11
#define    RTL8370_METER155_MASK    0x800
#define    RTL8370_METER154_OFFSET    10
#define    RTL8370_METER154_MASK    0x400
#define    RTL8370_METER153_OFFSET    9
#define    RTL8370_METER153_MASK    0x200
#define    RTL8370_METER152_OFFSET    8
#define    RTL8370_METER152_MASK    0x100
#define    RTL8370_METER151_OFFSET    7
#define    RTL8370_METER151_MASK    0x80
#define    RTL8370_METER150_OFFSET    6
#define    RTL8370_METER150_MASK    0x40
#define    RTL8370_METER149_OFFSET    5
#define    RTL8370_METER149_MASK    0x20
#define    RTL8370_METER148_OFFSET    4
#define    RTL8370_METER148_MASK    0x10
#define    RTL8370_METER147_OFFSET    3
#define    RTL8370_METER147_MASK    0x8
#define    RTL8370_METER146_OFFSET    2
#define    RTL8370_METER146_MASK    0x4
#define    RTL8370_METER145_OFFSET    1
#define    RTL8370_METER145_MASK    0x2
#define    RTL8370_METER144_OFFSET    0
#define    RTL8370_METER144_MASK    0x1

#define    RTL8370_REG_METER_EXCEED_INDICATOR10    0x1112
#define    RTL8370_METER175_OFFSET    15
#define    RTL8370_METER175_MASK    0x8000
#define    RTL8370_METER174_OFFSET    14
#define    RTL8370_METER174_MASK    0x4000
#define    RTL8370_METER173_OFFSET    13
#define    RTL8370_METER173_MASK    0x2000
#define    RTL8370_METER172_OFFSET    12
#define    RTL8370_METER172_MASK    0x1000
#define    RTL8370_METER171_OFFSET    11
#define    RTL8370_METER171_MASK    0x800
#define    RTL8370_METER170_OFFSET    10
#define    RTL8370_METER170_MASK    0x400
#define    RTL8370_METER169_OFFSET    9
#define    RTL8370_METER169_MASK    0x200
#define    RTL8370_METER168_OFFSET    8
#define    RTL8370_METER168_MASK    0x100
#define    RTL8370_METER167_OFFSET    7
#define    RTL8370_METER167_MASK    0x80
#define    RTL8370_METER166_OFFSET    6
#define    RTL8370_METER166_MASK    0x40
#define    RTL8370_METER165_OFFSET    5
#define    RTL8370_METER165_MASK    0x20
#define    RTL8370_METER164_OFFSET    4
#define    RTL8370_METER164_MASK    0x10
#define    RTL8370_METER163_OFFSET    3
#define    RTL8370_METER163_MASK    0x8
#define    RTL8370_METER162_OFFSET    2
#define    RTL8370_METER162_MASK    0x4
#define    RTL8370_METER161_OFFSET    1
#define    RTL8370_METER161_MASK    0x2
#define    RTL8370_METER160_OFFSET    0
#define    RTL8370_METER160_MASK    0x1

#define    RTL8370_REG_METER_EXCEED_INDICATOR11    0x1113
#define    RTL8370_METER191_OFFSET    15
#define    RTL8370_METER191_MASK    0x8000
#define    RTL8370_METER190_OFFSET    14
#define    RTL8370_METER190_MASK    0x4000
#define    RTL8370_METER189_OFFSET    13
#define    RTL8370_METER189_MASK    0x2000
#define    RTL8370_METER188_OFFSET    12
#define    RTL8370_METER188_MASK    0x1000
#define    RTL8370_METER187_OFFSET    11
#define    RTL8370_METER187_MASK    0x800
#define    RTL8370_METER186_OFFSET    10
#define    RTL8370_METER186_MASK    0x400
#define    RTL8370_METER185_OFFSET    9
#define    RTL8370_METER185_MASK    0x200
#define    RTL8370_METER184_OFFSET    8
#define    RTL8370_METER184_MASK    0x100
#define    RTL8370_METER183_OFFSET    7
#define    RTL8370_METER183_MASK    0x80
#define    RTL8370_METER182_OFFSET    6
#define    RTL8370_METER182_MASK    0x40
#define    RTL8370_METER181_OFFSET    5
#define    RTL8370_METER181_MASK    0x20
#define    RTL8370_METER180_OFFSET    4
#define    RTL8370_METER180_MASK    0x10
#define    RTL8370_METER179_OFFSET    3
#define    RTL8370_METER179_MASK    0x8
#define    RTL8370_METER178_OFFSET    2
#define    RTL8370_METER178_MASK    0x4
#define    RTL8370_METER177_OFFSET    1
#define    RTL8370_METER177_MASK    0x2
#define    RTL8370_METER176_OFFSET    0
#define    RTL8370_METER176_MASK    0x1

#define    RTL8370_REG_METER_EXCEED_INDICATOR12    0x1114
#define    RTL8370_METER207_OFFSET    15
#define    RTL8370_METER207_MASK    0x8000
#define    RTL8370_METER206_OFFSET    14
#define    RTL8370_METER206_MASK    0x4000
#define    RTL8370_METER205_OFFSET    13
#define    RTL8370_METER205_MASK    0x2000
#define    RTL8370_METER204_OFFSET    12
#define    RTL8370_METER204_MASK    0x1000
#define    RTL8370_METER203_OFFSET    11
#define    RTL8370_METER203_MASK    0x800
#define    RTL8370_METER202_OFFSET    10
#define    RTL8370_METER202_MASK    0x400
#define    RTL8370_METER201_OFFSET    9
#define    RTL8370_METER201_MASK    0x200
#define    RTL8370_METER200_OFFSET    8
#define    RTL8370_METER200_MASK    0x100
#define    RTL8370_METER199_OFFSET    7
#define    RTL8370_METER199_MASK    0x80
#define    RTL8370_METER198_OFFSET    6
#define    RTL8370_METER198_MASK    0x40
#define    RTL8370_METER197_OFFSET    5
#define    RTL8370_METER197_MASK    0x20
#define    RTL8370_METER196_OFFSET    4
#define    RTL8370_METER196_MASK    0x10
#define    RTL8370_METER195_OFFSET    3
#define    RTL8370_METER195_MASK    0x8
#define    RTL8370_METER194_OFFSET    2
#define    RTL8370_METER194_MASK    0x4
#define    RTL8370_METER193_OFFSET    1
#define    RTL8370_METER193_MASK    0x2
#define    RTL8370_METER192_OFFSET    0
#define    RTL8370_METER192_MASK    0x1

#define    RTL8370_REG_METER_EXCEED_INDICATOR13    0x1115
#define    RTL8370_METER223_OFFSET    15
#define    RTL8370_METER223_MASK    0x8000
#define    RTL8370_METER222_OFFSET    14
#define    RTL8370_METER222_MASK    0x4000
#define    RTL8370_METER221_OFFSET    13
#define    RTL8370_METER221_MASK    0x2000
#define    RTL8370_METER220_OFFSET    12
#define    RTL8370_METER220_MASK    0x1000
#define    RTL8370_METER219_OFFSET    11
#define    RTL8370_METER219_MASK    0x800
#define    RTL8370_METER218_OFFSET    10
#define    RTL8370_METER218_MASK    0x400
#define    RTL8370_METER217_OFFSET    9
#define    RTL8370_METER217_MASK    0x200
#define    RTL8370_METER216_OFFSET    8
#define    RTL8370_METER216_MASK    0x100
#define    RTL8370_METER215_OFFSET    7
#define    RTL8370_METER215_MASK    0x80
#define    RTL8370_METER214_OFFSET    6
#define    RTL8370_METER214_MASK    0x40
#define    RTL8370_METER213_OFFSET    5
#define    RTL8370_METER213_MASK    0x20
#define    RTL8370_METER212_OFFSET    4
#define    RTL8370_METER212_MASK    0x10
#define    RTL8370_METER211_OFFSET    3
#define    RTL8370_METER211_MASK    0x8
#define    RTL8370_METER210_OFFSET    2
#define    RTL8370_METER210_MASK    0x4
#define    RTL8370_METER209_OFFSET    1
#define    RTL8370_METER209_MASK    0x2
#define    RTL8370_METER208_OFFSET    0
#define    RTL8370_METER208_MASK    0x1

#define    RTL8370_REG_METER_EXCEED_INDICATOR14    0x1116
#define    RTL8370_METER239_OFFSET    15
#define    RTL8370_METER239_MASK    0x8000
#define    RTL8370_METER238_OFFSET    14
#define    RTL8370_METER238_MASK    0x4000
#define    RTL8370_METER237_OFFSET    13
#define    RTL8370_METER237_MASK    0x2000
#define    RTL8370_METER236_OFFSET    12
#define    RTL8370_METER236_MASK    0x1000
#define    RTL8370_METER235_OFFSET    11
#define    RTL8370_METER235_MASK    0x800
#define    RTL8370_METER234_OFFSET    10
#define    RTL8370_METER234_MASK    0x400
#define    RTL8370_METER233_OFFSET    9
#define    RTL8370_METER233_MASK    0x200
#define    RTL8370_METER232_OFFSET    8
#define    RTL8370_METER232_MASK    0x100
#define    RTL8370_METER231_OFFSET    7
#define    RTL8370_METER231_MASK    0x80
#define    RTL8370_METER230_OFFSET    6
#define    RTL8370_METER230_MASK    0x40
#define    RTL8370_METER229_OFFSET    5
#define    RTL8370_METER229_MASK    0x20
#define    RTL8370_METER228_OFFSET    4
#define    RTL8370_METER228_MASK    0x10
#define    RTL8370_METER227_OFFSET    3
#define    RTL8370_METER227_MASK    0x8
#define    RTL8370_METER226_OFFSET    2
#define    RTL8370_METER226_MASK    0x4
#define    RTL8370_METER225_OFFSET    1
#define    RTL8370_METER225_MASK    0x2
#define    RTL8370_METER224_OFFSET    0
#define    RTL8370_METER224_MASK    0x1

#define    RTL8370_REG_METER_EXCEED_INDICATOR15    0x1117
#define    RTL8370_METER255_OFFSET    15
#define    RTL8370_METER255_MASK    0x8000
#define    RTL8370_METER254_OFFSET    14
#define    RTL8370_METER254_MASK    0x4000
#define    RTL8370_METER253_OFFSET    13
#define    RTL8370_METER253_MASK    0x2000
#define    RTL8370_METER252_OFFSET    12
#define    RTL8370_METER252_MASK    0x1000
#define    RTL8370_METER251_OFFSET    11
#define    RTL8370_METER251_MASK    0x800
#define    RTL8370_METER250_OFFSET    10
#define    RTL8370_METER250_MASK    0x400
#define    RTL8370_METER249_OFFSET    9
#define    RTL8370_METER249_MASK    0x200
#define    RTL8370_METER248_OFFSET    8
#define    RTL8370_METER248_MASK    0x100
#define    RTL8370_METER247_OFFSET    7
#define    RTL8370_METER247_MASK    0x80
#define    RTL8370_METER246_OFFSET    6
#define    RTL8370_METER246_MASK    0x40
#define    RTL8370_METER245_OFFSET    5
#define    RTL8370_METER245_MASK    0x20
#define    RTL8370_METER244_OFFSET    4
#define    RTL8370_METER244_MASK    0x10
#define    RTL8370_METER243_OFFSET    3
#define    RTL8370_METER243_MASK    0x8
#define    RTL8370_METER242_OFFSET    2
#define    RTL8370_METER242_MASK    0x4
#define    RTL8370_METER241_OFFSET    1
#define    RTL8370_METER241_MASK    0x2
#define    RTL8370_METER240_OFFSET    0
#define    RTL8370_METER240_MASK    0x1

#define    RTL8370_REG_DW8051_IMR    0x1118
#define    RTL8370_DW8051_IMR_DUMMY_0_OFFSET    4
#define    RTL8370_DW8051_IMR_DUMMY_0_MASK    0xFFF0
#define    RTL8370_IMR_DW8051_GREENFEATURE_OFFSET    3
#define    RTL8370_IMR_DW8051_GREENFEATURE_MASK    0x8
#define    RTL8370_IMR_DW8051_SAMOVING_OFFSET    2
#define    RTL8370_IMR_DW8051_SAMOVING_MASK    0x4
#define    RTL8370_IMR_DW8051_LOOPEXIST_OFFSET    1
#define    RTL8370_IMR_DW8051_LOOPEXIST_MASK    0x2
#define    RTL8370_IMR_DW8051_EEELLDP_OFFSET    0
#define    RTL8370_IMR_DW8051_EEELLDP_MASK    0x1

#define    RTL8370_REG_DW8051_IMS    0x1119
#define    RTL8370_IMS_DW8051_GREENFEATURE_OFFSET    3
#define    RTL8370_IMS_DW8051_GREENFEATURE_MASK    0x8
#define    RTL8370_IMS_DW8051_SAMOVING_OFFSET    2
#define    RTL8370_IMS_DW8051_SAMOVING_MASK    0x4
#define    RTL8370_IMS_DW8051_LOOPEXIST_OFFSET    1
#define    RTL8370_IMS_DW8051_LOOPEXIST_MASK    0x2
#define    RTL8370_IMS_DW8051_EEELLDP_OFFSET    0
#define    RTL8370_IMS_DW8051_EEELLDP_MASK    0x1

#define    RTL8370_REG_DW8051_INT_CPU    0x111a
#define    RTL8370_DW8051_INT_CPU_OFFSET    0
#define    RTL8370_DW8051_INT_CPU_MASK    0x1

/* (16'h1200) swcore_reg */

#define    RTL8370_REG_MAX_LENGTH_LIMINT_IPG    0x1200
#define    RTL8370_PTKGEN_LENGTH_FIELD_SEL_OFFSET    15
#define    RTL8370_PTKGEN_LENGTH_FIELD_SEL_MASK    0x8000
#define    RTL8370_MAX_LENTH_CTRL_OFFSET    13
#define    RTL8370_MAX_LENTH_CTRL_MASK    0x6000
#define    RTL8370_EGSFC_SHARE_PKT_THRESHOLD_OFFSET    6
#define    RTL8370_EGSFC_SHARE_PKT_THRESHOLD_MASK    0x1FC0
#define    RTL8370_CHECK_MIN_IPG_RXDV_OFFSET    5
#define    RTL8370_CHECK_MIN_IPG_RXDV_MASK    0x20
#define    RTL8370_LIMIT_IPG_CFG_OFFSET    0
#define    RTL8370_LIMIT_IPG_CFG_MASK    0x1F

#define    RTL8370_REG_IOL_RXDROP_CFG    0x1201
#define    RTL8370_RX_IOL_MAX_LENGTH_CFG_OFFSET    13
#define    RTL8370_RX_IOL_MAX_LENGTH_CFG_MASK    0x2000
#define    RTL8370_RX_IOL_ERROR_LENGTH_CFG_OFFSET    12
#define    RTL8370_RX_IOL_ERROR_LENGTH_CFG_MASK    0x1000
#define    RTL8370_RX_NODROP_PAUSE_CFG_OFFSET    8
#define    RTL8370_RX_NODROP_PAUSE_CFG_MASK    0x100
#define    RTL8370_RX_DV_CNT_CFG_OFFSET    0
#define    RTL8370_RX_DV_CNT_CFG_MASK    0x3F

#define    RTL8370_REG_VS_TPID    0x1202

#define    RTL8370_REG_INBW_LBOUND_L    0x1203

#define    RTL8370_REG_INBW_LBOUND_M    0x1204

#define    RTL8370_REG_INBW_HBOUND_L    0x1205

#define    RTL8370_REG_INBW_HBOUND_M    0x1206

#define    RTL8370_REG_CFG_BACKPRESSURE    0x1207
#define    RTL8370_LONGTXE_OFFSET    12
#define    RTL8370_LONGTXE_MASK    0x1000
#define    RTL8370_EN_BYPASS_ERROR_OFFSET    8
#define    RTL8370_EN_BYPASS_ERROR_MASK    0x100
#define    RTL8370_EN_BACLPRESSURE_OFFSET    4
#define    RTL8370_EN_BACLPRESSURE_MASK    0x10
#define    RTL8370_EN_48_PASS_1_OFFSET    0
#define    RTL8370_EN_48_PASS_1_MASK    0x1

#define    RTL8370_REG_CFG_UNHIOL    0x1208
#define    RTL8370_IOL_BACKOFF_OFFSET    12
#define    RTL8370_IOL_BACKOFF_MASK    0x1000
#define    RTL8370_BACKOFF_RANDOM_TIME_OFFSET    8
#define    RTL8370_BACKOFF_RANDOM_TIME_MASK    0x100
#define    RTL8370_DISABLE_BACK_OFF_OFFSET    4
#define    RTL8370_DISABLE_BACK_OFF_MASK    0x10
#define    RTL8370_IPG_COMPENSATION_OFFSET    0
#define    RTL8370_IPG_COMPENSATION_MASK    0x1

#define    RTL8370_REG_SWITCH_MAC0    0x1209

#define    RTL8370_REG_SWITCH_MAC1    0x120a

#define    RTL8370_REG_SWITCH_MAC2    0x120b

#define    RTL8370_REG_SWITCH_CTRL0    0x120c
#define    RTL8370_REMARKING_1Q_ENABLE_OFFSET    12
#define    RTL8370_REMARKING_1Q_ENABLE_MASK    0x1000
#define    RTL8370_REMARKING_DSCP_ENABLE_OFFSET    8
#define    RTL8370_REMARKING_DSCP_ENABLE_MASK    0x100
#define    RTL8370_SHORT_IPG_OFFSET    4
#define    RTL8370_SHORT_IPG_MASK    0x10
#define    RTL8370_PAUSE_MAX128_OFFSET    0
#define    RTL8370_PAUSE_MAX128_MASK    0x1

#define    RTL8370_REG_QOS_DSCP_REMARK_CTRL0    0x120d
#define    RTL8370_INTPRI1_DSCP_OFFSET    8
#define    RTL8370_INTPRI1_DSCP_MASK    0x3F00
#define    RTL8370_INTPRI0_DSCP_OFFSET    0
#define    RTL8370_INTPRI0_DSCP_MASK    0x3F

#define    RTL8370_REG_QOS_DSCP_REMARK_CTRL1    0x120e
#define    RTL8370_INTPRI3_DSCP_OFFSET    8
#define    RTL8370_INTPRI3_DSCP_MASK    0x3F00
#define    RTL8370_INTPRI2_DSCP_OFFSET    0
#define    RTL8370_INTPRI2_DSCP_MASK    0x3F

#define    RTL8370_REG_QOS_DSCP_REMARK_CTRL2    0x120f
#define    RTL8370_INTPRI5_DSCP_OFFSET    8
#define    RTL8370_INTPRI5_DSCP_MASK    0x3F00
#define    RTL8370_INTPRI4_DSCP_OFFSET    0
#define    RTL8370_INTPRI4_DSCP_MASK    0x3F

#define    RTL8370_REG_QOS_DSCP_REMARK_CTRL3    0x1210
#define    RTL8370_INTPRI7_DSCP_OFFSET    8
#define    RTL8370_INTPRI7_DSCP_MASK    0x3F00
#define    RTL8370_INTPRI6_DSCP_OFFSET    0
#define    RTL8370_INTPRI6_DSCP_MASK    0x3F

#define    RTL8370_REG_QOS_1Q_REMARK_CTRL0    0x1211
#define    RTL8370_INTPRI3_PRI_OFFSET    12
#define    RTL8370_INTPRI3_PRI_MASK    0x7000
#define    RTL8370_INTPRI2_PRI_OFFSET    8
#define    RTL8370_INTPRI2_PRI_MASK    0x700
#define    RTL8370_INTPRI1_PRI_OFFSET    4
#define    RTL8370_INTPRI1_PRI_MASK    0x70
#define    RTL8370_INTPRI0_PRI_OFFSET    0
#define    RTL8370_INTPRI0_PRI_MASK    0x7

#define    RTL8370_REG_QOS_1Q_REMARK_CTRL1    0x1212
#define    RTL8370_INTPRI7_PRI_OFFSET    12
#define    RTL8370_INTPRI7_PRI_MASK    0x7000
#define    RTL8370_INTPRI6_PRI_OFFSET    8
#define    RTL8370_INTPRI6_PRI_MASK    0x700
#define    RTL8370_INTPRI5_PRI_OFFSET    4
#define    RTL8370_INTPRI5_PRI_MASK    0x70
#define    RTL8370_INTPRI4_PRI_OFFSET    0
#define    RTL8370_INTPRI4_PRI_MASK    0x7

#define    RTL8370_REG_PTKGEN_COMMAND    0x1213
#define    RTL8370_PTKGEN_START_OFFSET    8
#define    RTL8370_PTKGEN_START_MASK    0x100
#define    RTL8370_PTKGEN_STOP_OFFSET    4
#define    RTL8370_PTKGEN_STOP_MASK    0x10
#define    RTL8370_PTKGEN_BYPASS_FLOWCONTROL_OFFSET    0
#define    RTL8370_PTKGEN_BYPASS_FLOWCONTROL_MASK    0x1

#define    RTL8370_REG_PTKGEN_PAUSE_TIME    0x1216

#define    RTL8370_REG_TX_STOP    0x1217

#define    RTL8370_REG_SVLAN_UPLINK_PORTMASK    0x1218

#define    RTL8370_REG_CPU_PORT_MASK    0x1219

#define    RTL8370_REG_CPU_CTRL    0x121a
#define    RTL8370_IOL_16DROP_OFFSET    8
#define    RTL8370_IOL_16DROP_MASK    0x100
#define    RTL8370_BYPASS_INQUEUE_OFFSET    7
#define    RTL8370_BYPASS_INQUEUE_MASK    0x80
#define    RTL8370_CPU_TRAP_PORT_OFFSET    3
#define    RTL8370_CPU_TRAP_PORT_MASK    0x78
#define    RTL8370_CPU_INSERTMODE_OFFSET    1
#define    RTL8370_CPU_INSERTMODE_MASK    0x6
#define    RTL8370_CPU_EN_OFFSET    0
#define    RTL8370_CPU_EN_MASK    0x1

#define    RTL8370_REG_DRF_BIST_MODE    0x121b

#define    RTL8370_REG_MIRROR_CTRL    0x121c
#define    RTL8370_MIRROR_CTRL_DUMMY_0_OFFSET    12
#define    RTL8370_MIRROR_CTRL_DUMMY_0_MASK    0xF000
#define    RTL8370_MIRROR_ISO_OFFSET    11
#define    RTL8370_MIRROR_ISO_MASK    0x800
#define    RTL8370_MIRROR_TX_OFFSET    10
#define    RTL8370_MIRROR_TX_MASK    0x400
#define    RTL8370_MIRROR_RX_OFFSET    9
#define    RTL8370_MIRROR_RX_MASK    0x200
#define    RTL8370_MIRROR_CTRL_DUMMY_1_OFFSET    8
#define    RTL8370_MIRROR_CTRL_DUMMY_1_MASK    0x100
#define    RTL8370_MIRROR_MONITOR_PORT_OFFSET    4
#define    RTL8370_MIRROR_MONITOR_PORT_MASK    0xF0
#define    RTL8370_MIRROR_SOURCE_PORT_OFFSET    0
#define    RTL8370_MIRROR_SOURCE_PORT_MASK    0xF

#define    RTL8370_REG_FLOWCTRL_CTRL0    0x121d
#define    RTL8370_DROP_ALL_THRESHOLD_OFFSET    5
#define    RTL8370_DROP_ALL_THRESHOLD_MASK    0xFFE0
#define    RTL8370_FLOWCTRL_TYPE_OFFSET    4
#define    RTL8370_FLOWCTRL_TYPE_MASK    0x10
#define    RTL8370_CLR_CTRLCKT_MAX_HOLD_OFFSET    3
#define    RTL8370_CLR_CTRLCKT_MAX_HOLD_MASK    0x8
#define    RTL8370_ITFSP_REG_OFFSET    0
#define    RTL8370_ITFSP_REG_MASK    0x7

#define    RTL8370_REG_FLOWCTRL_ALL_ON    0x121e
#define    RTL8370_FLOWCTRL_ALL_ON_DUMMY_0_OFFSET    11
#define    RTL8370_FLOWCTRL_ALL_ON_DUMMY_0_MASK    0xF800
#define    RTL8370_FLOWCTRL_ALL_ON_THRESHOLD_OFFSET    0
#define    RTL8370_FLOWCTRL_ALL_ON_THRESHOLD_MASK    0x7FF

#define    RTL8370_REG_FLOWCTRL_SYS_ON    0x121f
#define    RTL8370_FLOWCTRL_SYS_ON_OFFSET    0
#define    RTL8370_FLOWCTRL_SYS_ON_MASK    0x7FF

#define    RTL8370_REG_FLOWCTRL_SYS_OFF    0x1220
#define    RTL8370_FLOWCTRL_SYS_OFF_OFFSET    0
#define    RTL8370_FLOWCTRL_SYS_OFF_MASK    0x7FF

#define    RTL8370_REG_FLOWCTRL_SHARE_ON    0x1221
#define    RTL8370_FLOWCTRL_SHARE_ON_OFFSET    0
#define    RTL8370_FLOWCTRL_SHARE_ON_MASK    0x7FF

#define    RTL8370_REG_FLOWCTRL_SHARE_OFF    0x1222
#define    RTL8370_FLOWCTRL_SHARE_OFF_OFFSET    0
#define    RTL8370_FLOWCTRL_SHARE_OFF_MASK    0x7FF

#define    RTL8370_REG_FLOWCTRL_FCOFF_SYS_ON    0x1223
#define    RTL8370_FLOWCTRL_FCOFF_SYS_ON_OFFSET    0
#define    RTL8370_FLOWCTRL_FCOFF_SYS_ON_MASK    0x7FF

#define    RTL8370_REG_FLOWCTRL_FCOFF_SYS_OFF    0x1224
#define    RTL8370_FLOWCTRL_FCOFF_SYS_OFF_OFFSET    0
#define    RTL8370_FLOWCTRL_FCOFF_SYS_OFF_MASK    0x7FF

#define    RTL8370_REG_FLOWCTRL_FCOFF_SHARE_ON    0x1225
#define    RTL8370_FLOWCTRL_FCOFF_SHARE_ON_OFFSET    0
#define    RTL8370_FLOWCTRL_FCOFF_SHARE_ON_MASK    0x7FF

#define    RTL8370_REG_FLOWCTRL_FCOFF_SHARE_OFF    0x1226
#define    RTL8370_FLOWCTRL_FCOFF_SHARE_OFF_OFFSET    0
#define    RTL8370_FLOWCTRL_FCOFF_SHARE_OFF_MASK    0x7FF

#define    RTL8370_REG_FLOWCTRL_PORT_ON    0x1227
#define    RTL8370_FLOWCTRL_PORT_ON_OFFSET    0
#define    RTL8370_FLOWCTRL_PORT_ON_MASK    0x7FF

#define    RTL8370_REG_FLOWCTRL_PORT_OFF    0x1228
#define    RTL8370_FLOWCTRL_PORT_OFF_OFFSET    0
#define    RTL8370_FLOWCTRL_PORT_OFF_MASK    0x7FF

#define    RTL8370_REG_FLOWCTRL_PORT_PRIVATE_ON    0x1229
#define    RTL8370_FLOWCTRL_PORT_PRIVATE_ON_OFFSET    0
#define    RTL8370_FLOWCTRL_PORT_PRIVATE_ON_MASK    0x7FF

#define    RTL8370_REG_FLOWCTRL_PORT_PRIVATE_OFF    0x122a
#define    RTL8370_FLOWCTRL_PORT_PRIVATE_OFF_OFFSET    0
#define    RTL8370_FLOWCTRL_PORT_PRIVATE_OFF_MASK    0x7FF

#define    RTL8370_REG_SEL_CFG    0x122b
#define    RTL8370_COL_SEL_OFFSET    14
#define    RTL8370_COL_SEL_MASK    0x4000
#define    RTL8370_CRS_SEL_OFFSET    13
#define    RTL8370_CRS_SEL_MASK    0x2000
#define    RTL8370_TCAMSEL_OFFSET    12
#define    RTL8370_TCAMSEL_MASK    0x1000

#define    RTL8370_REG_FLOWCTRL_FCOFF_PORT_ON    0x122f
#define    RTL8370_FLOWCTRL_FCOFF_PORT_ON_OFFSET    0
#define    RTL8370_FLOWCTRL_FCOFF_PORT_ON_MASK    0x7FF

#define    RTL8370_REG_FLOWCTRL_FCOFF_PORT_OFF    0x1230
#define    RTL8370_FLOWCTRL_FCOFF_PORT_OFF_OFFSET    0
#define    RTL8370_FLOWCTRL_FCOFF_PORT_OFF_MASK    0x7FF

#define    RTL8370_REG_FLOWCTRL_FCOFF_PORT_PRIVATE_ON    0x1231
#define    RTL8370_FLOWCTRL_FCOFF_PORT_PRIVATE_ON_OFFSET    0
#define    RTL8370_FLOWCTRL_FCOFF_PORT_PRIVATE_ON_MASK    0x7FF

#define    RTL8370_REG_FLOWCTRL_FCOFF_PORT_PRIVATE_OFF    0x1232
#define    RTL8370_FLOWCTRL_FCOFF_PORT_PRIVATE_OFF_OFFSET    0
#define    RTL8370_FLOWCTRL_FCOFF_PORT_PRIVATE_OFF_MASK    0x7FF

#define    RTL8370_REG_FLOWCTRL_TOTAL_PAGE_COUNTER    0x124c
#define    RTL8370_INQ_OVER_OFFSET    13
#define    RTL8370_INQ_OVER_MASK    0x2000
#define    RTL8370_DSCRUNOUT_OFFSET    12
#define    RTL8370_DSCRUNOUT_MASK    0x1000
#define    RTL8370_FLOWCTRL_TOTAL_PAGE_COUNTER_COUNTER_OFFSET    0
#define    RTL8370_FLOWCTRL_TOTAL_PAGE_COUNTER_COUNTER_MASK    0x7FF

#define    RTL8370_REG_FLOWCTRL_PUBLIC_PAGE_COUNTER    0x124d
#define    RTL8370_FLOWCTRL_PUBLIC_PAGE_COUNTER_OFFSET    0
#define    RTL8370_FLOWCTRL_PUBLIC_PAGE_COUNTER_MASK    0x7FF

#define    RTL8370_REG_FLOWCTRL_TOTAL_PAGE_MAX    0x124e
#define    RTL8370_FLOWCTRL_TOTAL_PAGE_MAX_OFFSET    0
#define    RTL8370_FLOWCTRL_TOTAL_PAGE_MAX_MASK    0x7FF

#define    RTL8370_REG_FLOWCTRL_PUBLIC_PAGE_MAX    0x124f
#define    RTL8370_FLOWCTRL_PUBLIC_PAGE_MAX_OFFSET    0
#define    RTL8370_FLOWCTRL_PUBLIC_PAGE_MAX_MASK    0x7FF

#define    RTL8370_REG_FLOWCTRL_PORT0_PAGE_COUNTER    0x1250
#define    RTL8370_FLOWCTRL_PORT0_PAGE_COUNTER_OFFSET    0
#define    RTL8370_FLOWCTRL_PORT0_PAGE_COUNTER_MASK    0x7FF

#define    RTL8370_REG_FLOWCTRL_PORT1_PAGE_COUNTER    0x1251
#define    RTL8370_FLOWCTRL_PORT1_PAGE_COUNTER_OFFSET    0
#define    RTL8370_FLOWCTRL_PORT1_PAGE_COUNTER_MASK    0x7FF

#define    RTL8370_REG_FLOWCTRL_PORT2_PAGE_COUNTER    0x1252
#define    RTL8370_FLOWCTRL_PORT2_PAGE_COUNTER_OFFSET    0
#define    RTL8370_FLOWCTRL_PORT2_PAGE_COUNTER_MASK    0x7FF

#define    RTL8370_REG_FLOWCTRL_PORT3_PAGE_COUNTER    0x1253
#define    RTL8370_FLOWCTRL_PORT3_PAGE_COUNTER_OFFSET    0
#define    RTL8370_FLOWCTRL_PORT3_PAGE_COUNTER_MASK    0x7FF

#define    RTL8370_REG_FLOWCTRL_PORT4_PAGE_COUNTER    0x1254
#define    RTL8370_FLOWCTRL_PORT4_PAGE_COUNTER_OFFSET    0
#define    RTL8370_FLOWCTRL_PORT4_PAGE_COUNTER_MASK    0x7FF

#define    RTL8370_REG_FLOWCTRL_PORT5_PAGE_COUNTER    0x1255
#define    RTL8370_FLOWCTRL_PORT5_PAGE_COUNTER_OFFSET    0
#define    RTL8370_FLOWCTRL_PORT5_PAGE_COUNTER_MASK    0x7FF

#define    RTL8370_REG_FLOWCTRL_PORT6_PAGE_COUNTER    0x1256
#define    RTL8370_FLOWCTRL_PORT6_PAGE_COUNTER_OFFSET    0
#define    RTL8370_FLOWCTRL_PORT6_PAGE_COUNTER_MASK    0x7FF

#define    RTL8370_REG_FLOWCTRL_PORT7_PAGE_COUNTER    0x1257
#define    RTL8370_FLOWCTRL_PORT7_PAGE_COUNTER_OFFSET    0
#define    RTL8370_FLOWCTRL_PORT7_PAGE_COUNTER_MASK    0x7FF

#define    RTL8370_REG_FLOWCTRL_PORT8_PAGE_COUNTER    0x1258
#define    RTL8370_FLOWCTRL_PORT8_PAGE_COUNTER_OFFSET    0
#define    RTL8370_FLOWCTRL_PORT8_PAGE_COUNTER_MASK    0x7FF

#define    RTL8370_REG_FLOWCTRL_PORT9_PAGE_COUNTER    0x1259
#define    RTL8370_FLOWCTRL_PORT9_PAGE_COUNTER_OFFSET    0
#define    RTL8370_FLOWCTRL_PORT9_PAGE_COUNTER_MASK    0x7FF

#define    RTL8370_REG_FLOWCTRL_PORT10_PAGE_COUNTER    0x125a
#define    RTL8370_FLOWCTRL_PORT10_PAGE_COUNTER_OFFSET    0
#define    RTL8370_FLOWCTRL_PORT10_PAGE_COUNTER_MASK    0x7FF

#define    RTL8370_REG_FLOWCTRL_PORT11_PAGE_COUNTER    0x125b
#define    RTL8370_FLOWCTRL_PORT11_PAGE_COUNTER_OFFSET    0
#define    RTL8370_FLOWCTRL_PORT11_PAGE_COUNTER_MASK    0x7FF

#define    RTL8370_REG_FLOWCTRL_PORT12_PAGE_COUNTER    0x125c
#define    RTL8370_FLOWCTRL_PORT12_PAGE_COUNTER_OFFSET    0
#define    RTL8370_FLOWCTRL_PORT12_PAGE_COUNTER_MASK    0x7FF

#define    RTL8370_REG_FLOWCTRL_PORT13_PAGE_COUNTER    0x125d
#define    RTL8370_FLOWCTRL_PORT13_PAGE_COUNTER_OFFSET    0
#define    RTL8370_FLOWCTRL_PORT13_PAGE_COUNTER_MASK    0x7FF

#define    RTL8370_REG_FLOWCTRL_PORT14_PAGE_COUNTER    0x125e
#define    RTL8370_FLOWCTRL_PORT14_PAGE_COUNTER_OFFSET    0
#define    RTL8370_FLOWCTRL_PORT14_PAGE_COUNTER_MASK    0x7FF

#define    RTL8370_REG_FLOWCTRL_PORT15_PAGE_COUNTER    0x125f
#define    RTL8370_FLOWCTRL_PORT15_PAGE_COUNTER_OFFSET    0
#define    RTL8370_FLOWCTRL_PORT15_PAGE_COUNTER_MASK    0x7FF

#define    RTL8370_REG_FLOWCTRL_PORT0_PAGE_MAX    0x1260
#define    RTL8370_FLOWCTRL_PORT0_PAGE_MAX_OFFSET    0
#define    RTL8370_FLOWCTRL_PORT0_PAGE_MAX_MASK    0x7FF

#define    RTL8370_REG_FLOWCTRL_PORT1_PAGE_MAX    0x1261
#define    RTL8370_FLOWCTRL_PORT1_PAGE_MAX_OFFSET    0
#define    RTL8370_FLOWCTRL_PORT1_PAGE_MAX_MASK    0x7FF

#define    RTL8370_REG_FLOWCTRL_PORT2_PAGE_MAX    0x1262
#define    RTL8370_FLOWCTRL_PORT2_PAGE_MAX_OFFSET    0
#define    RTL8370_FLOWCTRL_PORT2_PAGE_MAX_MASK    0x7FF

#define    RTL8370_REG_FLOWCTRL_PORT3_PAGE_MAX    0x1263
#define    RTL8370_FLOWCTRL_PORT3_PAGE_MAX_OFFSET    0
#define    RTL8370_FLOWCTRL_PORT3_PAGE_MAX_MASK    0x7FF

#define    RTL8370_REG_FLOWCTRL_PORT4_PAGE_MAX    0x1264
#define    RTL8370_FLOWCTRL_PORT4_PAGE_MAX_OFFSET    0
#define    RTL8370_FLOWCTRL_PORT4_PAGE_MAX_MASK    0x7FF

#define    RTL8370_REG_FLOWCTRL_PORT5_PAGE_MAX    0x1265
#define    RTL8370_FLOWCTRL_PORT5_PAGE_MAX_OFFSET    0
#define    RTL8370_FLOWCTRL_PORT5_PAGE_MAX_MASK    0x7FF

#define    RTL8370_REG_FLOWCTRL_PORT6_PAGE_MAX    0x1266
#define    RTL8370_FLOWCTRL_PORT6_PAGE_MAX_OFFSET    0
#define    RTL8370_FLOWCTRL_PORT6_PAGE_MAX_MASK    0x7FF

#define    RTL8370_REG_FLOWCTRL_PORT7_PAGE_MAX    0x1267
#define    RTL8370_FLOWCTRL_PORT7_PAGE_MAX_OFFSET    0
#define    RTL8370_FLOWCTRL_PORT7_PAGE_MAX_MASK    0x7FF

#define    RTL8370_REG_FLOWCTRL_PORT8_PAGE_MAX    0x1268
#define    RTL8370_FLOWCTRL_PORT8_PAGE_MAX_OFFSET    0
#define    RTL8370_FLOWCTRL_PORT8_PAGE_MAX_MASK    0x7FF

#define    RTL8370_REG_FLOWCTRL_PORT9_PAGE_MAX    0x1269
#define    RTL8370_FLOWCTRL_PORT9_PAGE_MAX_OFFSET    0
#define    RTL8370_FLOWCTRL_PORT9_PAGE_MAX_MASK    0x7FF

#define    RTL8370_REG_FLOWCTRL_PORT10_PAGE_MAX    0x126a
#define    RTL8370_FLOWCTRL_PORT10_PAGE_MAX_OFFSET    0
#define    RTL8370_FLOWCTRL_PORT10_PAGE_MAX_MASK    0x7FF

#define    RTL8370_REG_FLOWCTRL_PORT11_PAGE_MAX    0x126b
#define    RTL8370_FLOWCTRL_PORT11_PAGE_MAX_OFFSET    0
#define    RTL8370_FLOWCTRL_PORT11_PAGE_MAX_MASK    0x7FF

#define    RTL8370_REG_FLOWCTRL_PORT12_PAGE_MAX    0x126c
#define    RTL8370_FLOWCTRL_PORT12_PAGE_MAX_OFFSET    0
#define    RTL8370_FLOWCTRL_PORT12_PAGE_MAX_MASK    0x7FF

#define    RTL8370_REG_FLOWCTRL_PORT13_PAGE_MAX    0x126d
#define    RTL8370_FLOWCTRL_PORT13_PAGE_MAX_OFFSET    0
#define    RTL8370_FLOWCTRL_PORT13_PAGE_MAX_MASK    0x7FF

#define    RTL8370_REG_FLOWCTRL_PORT14_PAGE_MAX    0x126e
#define    RTL8370_FLOWCTRL_PORT14_PAGE_MAX_OFFSET    0
#define    RTL8370_FLOWCTRL_PORT14_PAGE_MAX_MASK    0x7FF

#define    RTL8370_REG_FLOWCTRL_PORT15_PAGE_MAX    0x126f
#define    RTL8370_FLOWCTRL_PORT15_PAGE_MAX_OFFSET    0
#define    RTL8370_FLOWCTRL_PORT15_PAGE_MAX_MASK    0x7FF

#define    RTL8370_REG_EMA_CRTL0    0x1270

#define    RTL8370_REG_EMA_CRTL1    0x1271

#define    RTL8370_REG_EMA_CRTL2    0x1272

#define    RTL8370_REG_BIST_MODE    0x1273

#define    RTL8370_REG_DIAG_MODE    0x1274

#define    RTL8370_REG_STS_BIST_DONE    0x1275

#define    RTL8370_REG_COND0_BIST_FAIL_W0    0x1276

#define    RTL8370_REG_COND0_BIST_FAIL_W1    0x1277

#define    RTL8370_REG_COND0_DRF_BIST_FAIL_W0    0x1278

#define    RTL8370_REG_COND0_DRF_BIST_FAIL_W1    0x1279

#define    RTL8370_REG_COND0_DRF_BIST_FAIL_W2    0x127a

#define    RTL8370_REG_COND0_BISR_L2RAM_W0    0x127b

#define    RTL8370_REG_COND0_BISR_L2RAM_W1    0x127c

#define    RTL8370_REG_COND0_BISR_CVLANRAM_W0    0x127d

#define    RTL8370_REG_COND0_BISR_HSARAM    0x127e

#define    RTL8370_REG_COND0_BISR_PBRAM_W0    0x127f

#define    RTL8370_REG_COND0_BISR_PBRAM_W1    0x1280

#define    RTL8370_REG_COND0_BISR_PBRAM_W2    0x1281

#define    RTL8370_REG_COND0_BISR_PBRAM_W3    0x1282

#define    RTL8370_REG_COND1_BIST_FAIL_W0    0x1283

#define    RTL8370_REG_COND1_BIST_FAIL_W1    0x1284

#define    RTL8370_REG_COND1_DRF_BIST_FAIL_W0    0x1285

#define    RTL8370_REG_COND1_DRF_BIST_FAIL_W1    0x1286

#define    RTL8370_REG_COND1_DRF_BIST_FAIL_W2    0x1287

#define    RTL8370_REG_COND1_BISR_L2RAM_W0    0x1288

#define    RTL8370_REG_COND1_BISR_L2RAM_W1    0x1289

#define    RTL8370_REG_COND1_BISR_CVLANRAM_W0    0x128a

#define    RTL8370_REG_COND1_BISR_HSARAM    0x128b

#define    RTL8370_REG_COND1_BISR_PBRAM_W0    0x128c

#define    RTL8370_REG_COND1_BISR_PBRAM_W1    0x128d

#define    RTL8370_REG_COND1_BISR_PBRAM_W2    0x128e

#define    RTL8370_REG_COND1_BISR_PBRAM_W3    0x128f

#define    RTL8370_REG_COND2_BIST_FAIL_W0    0x1290

#define    RTL8370_REG_COND2_BIST_FAIL_W1    0x1291

#define    RTL8370_REG_COND2_DRF_BIST_FAIL_W0    0x1292

#define    RTL8370_REG_COND2_DRF_BIST_FAIL_W1    0x1293

#define    RTL8370_REG_COND2_DRF_BIST_FAIL_W2    0x1294

#define    RTL8370_REG_COND2_BISR_L2RAM_W0    0x1295

#define    RTL8370_REG_COND2_BISR_L2RAM_W1    0x1296

#define    RTL8370_REG_COND2_BISR_CVLANRAM_W0    0x1297

#define    RTL8370_REG_COND2_BISR_HSARAM    0x1298

#define    RTL8370_REG_COND2_BISR_PBRAM_W0    0x1299

#define    RTL8370_REG_COND2_BISR_PBRAM_W1    0x129a

#define    RTL8370_REG_COND2_BISR_PBRAM_W2    0x129b

#define    RTL8370_REG_COND2_BISR_PBRAM_W3    0x129c

#define    RTL8370_REG_EAV_SYS_COUNTER    0x129f

#define    RTL8370_REG_EEE_TX_RATE_GIGA    0x12a0

#define    RTL8370_REG_EEE_TX_RATE_100m    0x12a1

#define    RTL8370_REG_EEE_TX_RATE_10m    0x12a2

#define    RTL8370_REG_EEE_MISC    0x12a3
#define    RTL8370_EEE_MISC_DUMMY_0_OFFSET    15
#define    RTL8370_EEE_MISC_DUMMY_0_MASK    0x8000
#define    RTL8370_EEE_REQ_SET_OFFSET    12
#define    RTL8370_EEE_REQ_SET_MASK    0x7000
#define    RTL8370_EEE_MISC_DUMMY_1_OFFSET    10
#define    RTL8370_EEE_MISC_DUMMY_1_MASK    0xC00
#define    RTL8370_EEE_WAKE_SET_OFFSET    8
#define    RTL8370_EEE_WAKE_SET_MASK    0x300
#define    RTL8370_EEE_MISC_DUMMY_2_OFFSET    6
#define    RTL8370_EEE_MISC_DUMMY_2_MASK    0xC0
#define    RTL8370_EEE_TU_GIGA_OFFSET    4
#define    RTL8370_EEE_TU_GIGA_MASK    0x30
#define    RTL8370_EEE_TU_100M_OFFSET    2
#define    RTL8370_EEE_TU_100M_MASK    0xC
#define    RTL8370_EEE_TU_10M_OFFSET    0
#define    RTL8370_EEE_TU_10M_MASK    0x3

#define    RTL8370_REG_EEE_GIGA_CTRL0    0x12a4
#define    RTL8370_EEE_TW_GIGA_OFFSET    8
#define    RTL8370_EEE_TW_GIGA_MASK    0xFF00
#define    RTL8370_EEE_TR_GIGA_OFFSET    0
#define    RTL8370_EEE_TR_GIGA_MASK    0xFF

#define    RTL8370_REG_EEE_GIGA_CTRL1    0x12a5
#define    RTL8370_EEE_TD_GIGA_OFFSET    8
#define    RTL8370_EEE_TD_GIGA_MASK    0xFF00
#define    RTL8370_EEE_TP_GIGA_OFFSET    0
#define    RTL8370_EEE_TP_GIGA_MASK    0xFF

#define    RTL8370_REG_EEE_100M_CTRL0    0x12a6
#define    RTL8370_EEE_TW_100M_OFFSET    8
#define    RTL8370_EEE_TW_100M_MASK    0xFF00
#define    RTL8370_EEE_TR_100M_OFFSET    0
#define    RTL8370_EEE_TR_100M_MASK    0xFF

#define    RTL8370_REG_EEE_100M_CTRL1    0x12a7
#define    RTL8370_EEE_TD_100M_OFFSET    8
#define    RTL8370_EEE_TD_100M_MASK    0xFF00
#define    RTL8370_EEE_TP_100M_OFFSET    0
#define    RTL8370_EEE_TP_100M_MASK    0xFF

#define    RTL8370_REG_EEE_10M_CTRL0    0x12a8
#define    RTL8370_EEE_TW_10M_OFFSET    8
#define    RTL8370_EEE_TW_10M_MASK    0xFF00
#define    RTL8370_EEE_TR_10M_OFFSET    0
#define    RTL8370_EEE_TR_10M_MASK    0xFF

#define    RTL8370_REG_EEE_10M_CTRL1    0x12a9
#define    RTL8370_EEE_TD_10M_OFFSET    8
#define    RTL8370_EEE_TD_10M_MASK    0xFF00
#define    RTL8370_EEE_TP_10M_OFFSET    0
#define    RTL8370_EEE_TP_10M_MASK    0xFF

#define    RTL8370_REG_RX_FC_REG    0x12aa
#define    RTL8370_RX_FC_REG_DUMMY_0_OFFSET    8
#define    RTL8370_RX_FC_REG_DUMMY_0_MASK    0xFF00
#define    RTL8370_PAGES_BEFORE_FCDROP_OFFSET    0
#define    RTL8370_PAGES_BEFORE_FCDROP_MASK    0xFF

#define    RTL8370_REG_MAX_FIFO_SIZE    0x12af
#define    RTL8370_MAX_FIFO_SIZE_OFFSET    0
#define    RTL8370_MAX_FIFO_SIZE_MASK    0x1F

#define    RTL8370_REG_EEEP_RX_RATE_GIGA    0x12b0

#define    RTL8370_REG_EEEP_RX_RATE_100M    0x12b1

#define    RTL8370_REG_DUMMY_REG_12_2    0x12b2

#define    RTL8370_REG_EEEP_TX_RATE_GIGA    0x12b3

#define    RTL8370_REG_EEEP_TX_RATE_100M    0x12b4

#define    RTL8370_REG_DUMMY_REG_12_3    0x12b5

#define    RTL8370_REG_EEEP_GIGA_CTRL0    0x12b6
#define    RTL8370_EEEP_TR_GIGA_OFFSET    8
#define    RTL8370_EEEP_TR_GIGA_MASK    0xFF00
#define    RTL8370_EEEP_TA_GIGA_OFFSET    0
#define    RTL8370_EEEP_TA_GIGA_MASK    0xFF

#define    RTL8370_REG_EEEP_GIGA_CTRL1    0x12b7
#define    RTL8370_EEEP_TW_GIGA_OFFSET    8
#define    RTL8370_EEEP_TW_GIGA_MASK    0xFF00
#define    RTL8370_EEEP_TP_GIGA_OFFSET    0
#define    RTL8370_EEEP_TP_GIGA_MASK    0xFF

#define    RTL8370_REG_EEEP_GIGA_CTRL2    0x12b8
#define    RTL8370_EEEP_GIGA_CTRL2_DUMMY_0_OFFSET    13
#define    RTL8370_EEEP_GIGA_CTRL2_DUMMY_0_MASK    0xE000
#define    RTL8370_EEEP_TXEN_GIGA_OFFSET    12
#define    RTL8370_EEEP_TXEN_GIGA_MASK    0x1000
#define    RTL8370_EEEP_GIGA_CTRL2_DUMMY_1_OFFSET    10
#define    RTL8370_EEEP_GIGA_CTRL2_DUMMY_1_MASK    0xC00
#define    RTL8370_EEEP_TU_GIGA_OFFSET    8
#define    RTL8370_EEEP_TU_GIGA_MASK    0x300
#define    RTL8370_EEEP_TS_GIGA_OFFSET    0
#define    RTL8370_EEEP_TS_GIGA_MASK    0xFF

#define    RTL8370_REG_EEEP_100M_CTRL0    0x12b9
#define    RTL8370_EEEP_TR_100M_OFFSET    8
#define    RTL8370_EEEP_TR_100M_MASK    0xFF00
#define    RTL8370_EEEP_TA_100M_OFFSET    0
#define    RTL8370_EEEP_TA_100M_MASK    0xFF

#define    RTL8370_REG_EEEP_100M_CTRL1    0x12ba
#define    RTL8370_EEEP_TW_100M_OFFSET    8
#define    RTL8370_EEEP_TW_100M_MASK    0xFF00
#define    RTL8370_EEEP_TP_100M_OFFSET    0
#define    RTL8370_EEEP_TP_100M_MASK    0xFF

#define    RTL8370_REG_EEEP_100M_CTRL2    0x12bb
#define    RTL8370_EEEP_100M_CTRL2_DUMMY_0_OFFSET    13
#define    RTL8370_EEEP_100M_CTRL2_DUMMY_0_MASK    0xE000
#define    RTL8370_EEEP_TXEN_100M_OFFSET    12
#define    RTL8370_EEEP_TXEN_100M_MASK    0x1000
#define    RTL8370_EEEP_100M_CTRL2_DUMMY_1_OFFSET    10
#define    RTL8370_EEEP_100M_CTRL2_DUMMY_1_MASK    0xC00
#define    RTL8370_EEEP_TU_100M_OFFSET    8
#define    RTL8370_EEEP_TU_100M_MASK    0x300
#define    RTL8370_EEEP_TS_100M_OFFSET    0
#define    RTL8370_EEEP_TS_100M_MASK    0xFF

#define    RTL8370_REG_EEEP_CTRL0    0x12bc
#define    RTL8370_EEEP_CTRL0_DUMMY_0_OFFSET    8
#define    RTL8370_EEEP_CTRL0_DUMMY_0_MASK    0xFF00
#define    RTL8370_EEEP_SLEEP_STEP_OFFSET    0
#define    RTL8370_EEEP_SLEEP_STEP_MASK    0xFF

#define    RTL8370_REG_EEEP_CTRL1    0x12bd
#define    RTL8370_EEEP_TXR_GIGA_OFFSET    8
#define    RTL8370_EEEP_TXR_GIGA_MASK    0xFF00
#define    RTL8370_EEEP_TXR_100M_OFFSET    0
#define    RTL8370_EEEP_TXR_100M_MASK    0xFF

#define    RTL8370_REG_DUMMY_REG_12_0    0x12be

#define    RTL8370_REG_DUMMY_REG_12_1    0x12bf

#define    RTL8370_REG_PTKGEN_PAYLOAD_CTRL0    0x12c0

#define    RTL8370_REG_PTKGEN_PAYLOAD_CTRL1    0x12c1

#define    RTL8370_REG_PTKGEN_PAYLOAD_CTRL2    0x12c2

#define    RTL8370_REG_PTKGEN_PAYLOAD_CTRL3    0x12c3

#define    RTL8370_REG_PTKGEN_PAYLOAD_CTRL4    0x12c4

#define    RTL8370_REG_PTKGEN_PAYLOAD_CTRL5    0x12c5

#define    RTL8370_REG_PTKGEN_PAYLOAD_CTRL6    0x12c6

#define    RTL8370_REG_PTKGEN_PAYLOAD_CTRL7    0x12c7

#define    RTL8370_REG_PTKGEN_PAYLOAD_CTRL8    0x12c8

#define    RTL8370_REG_PTKGEN_PAYLOAD_CTRL9    0x12c9

#define    RTL8370_REG_PTKGEN_PAYLOAD_CTRL10    0x12ca

#define    RTL8370_REG_PTKGEN_PAYLOAD_CTRL11    0x12cb

#define    RTL8370_REG_PTKGEN_PAYLOAD_CTRL12    0x12cc

#define    RTL8370_REG_PTKGEN_PAYLOAD_CTRL13    0x12cd

#define    RTL8370_REG_PTKGEN_PAYLOAD_CTRL14    0x12ce

#define    RTL8370_REG_PTKGEN_PAYLOAD_CTRL15    0x12cf

#define    RTL8370_REG_PTKGEN_PAYLOAD_CTRL16    0x12d0

#define    RTL8370_REG_PTKGEN_PAYLOAD_CTRL17    0x12d1

#define    RTL8370_REG_PTKGEN_PAYLOAD_CTRL18    0x12d2

#define    RTL8370_REG_PTKGEN_PAYLOAD_CTRL19    0x12d3

#define    RTL8370_REG_PTKGEN_PAYLOAD_CTRL20    0x12d4

#define    RTL8370_REG_PTKGEN_PAYLOAD_CTRL21    0x12d5

#define    RTL8370_REG_PTKGEN_PAYLOAD_CTRL22    0x12d6

#define    RTL8370_REG_PTKGEN_PAYLOAD_CTRL23    0x12d7

/* (16'h1300) chip_reg */

#define    RTL8370_REG_CHIP_NUMBER    0x1300

#define    RTL8370_REG_CHIP_VER    0x1301
#define    RTL8370_RLVID_OFFSET    12
#define    RTL8370_RLVID_MASK    0xF000
#define    RTL8370_MCID_OFFSET    8
#define    RTL8370_MCID_MASK    0xF00
#define    RTL8370_BOID_OFFSET    4
#define    RTL8370_BOID_MASK    0xF0

#define    RTL8370_REG_CHIP_MODE    0x1302
#define    RTL8370_PLL_250_FROM_SDS_OFFSET    5
#define    RTL8370_PLL_250_FROM_SDS_MASK    0x20
#define    RTL8370_MODE_DEBUG_PACKAGE_OFFSET    4
#define    RTL8370_MODE_DEBUG_PACKAGE_MASK    0x10
#define    RTL8370_ROUTER_MODE_OFFSET    3
#define    RTL8370_ROUTER_MODE_MASK    0x8
#define    RTL8370_CHIP_MODE_OFFSET    0
#define    RTL8370_CHIP_MODE_MASK    0x7

#define    RTL8370_REG_CHIP_DEBUG0    0x1303
#define    RTL8370_CHIP_DEBUG0_DUMMY_0_OFFSET    8
#define    RTL8370_CHIP_DEBUG0_DUMMY_0_MASK    0xFF00
#define    RTL8370_DRI_OTHER_OFFSET    7
#define    RTL8370_DRI_OTHER_MASK    0x80
#define    RTL8370_DRI_EXT1_RG_OFFSET    6
#define    RTL8370_DRI_EXT1_RG_MASK    0x40
#define    RTL8370_DRI_EXT0_RG_OFFSET    5
#define    RTL8370_DRI_EXT0_RG_MASK    0x20
#define    RTL8370_DRI_EXT1_OFFSET    4
#define    RTL8370_DRI_EXT1_MASK    0x10
#define    RTL8370_DRI_EXT0_OFFSET    3
#define    RTL8370_DRI_EXT0_MASK    0x8
#define    RTL8370_SLR_OTHER_OFFSET    2
#define    RTL8370_SLR_OTHER_MASK    0x4
#define    RTL8370_SLR_EXT1_OFFSET    1
#define    RTL8370_SLR_EXT1_MASK    0x2
#define    RTL8370_SLR_EXt0_OFFSET    0
#define    RTL8370_SLR_EXt0_MASK    0x1

#define    RTL8370_REG_CHIP_DEBUG1    0x1304
#define    RTL8370_CHIP_DEBUG1_DUMMY_0_OFFSET    15
#define    RTL8370_CHIP_DEBUG1_DUMMY_0_MASK    0x8000
#define    RTL8370_RG1_DN_OFFSET    12
#define    RTL8370_RG1_DN_MASK    0x7000
#define    RTL8370_CHIP_DEBUG1_DUMMY_1_OFFSET    11
#define    RTL8370_CHIP_DEBUG1_DUMMY_1_MASK    0x800
#define    RTL8370_RG1_DP_OFFSET    8
#define    RTL8370_RG1_DP_MASK    0x700
#define    RTL8370_CHIP_DEBUG1_DUMMY_2_OFFSET    7
#define    RTL8370_CHIP_DEBUG1_DUMMY_2_MASK    0x80
#define    RTL8370_RG0_DN_OFFSET    4
#define    RTL8370_RG0_DN_MASK    0x70
#define    RTL8370_CHIP_DEBUG1_DUMMY_3_OFFSET    3
#define    RTL8370_CHIP_DEBUG1_DUMMY_3_MASK    0x8
#define    RTL8370_RG0_DP_OFFSET    0
#define    RTL8370_RG0_DP_MASK    0x7

#define    RTL8370_REG_DIGITIAL_INTERFACE_SELECT    0x1305
#define    RTL8370_ORG_COL_OFFSET    15
#define    RTL8370_ORG_COL_MASK    0x8000
#define    RTL8370_ORG_CRS_OFFSET    14
#define    RTL8370_ORG_CRS_MASK    0x4000
#define    RTL8370_SKIP_MII_1_RXER_OFFSET    13
#define    RTL8370_SKIP_MII_1_RXER_MASK    0x2000
#define    RTL8370_SKIP_MII_0_RXER_OFFSET    12
#define    RTL8370_SKIP_MII_0_RXER_MASK    0x1000
#define    RTL8370_DIGITIAL_INTERFACE_SELECT_DUMMY_0_OFFSET    7
#define    RTL8370_DIGITIAL_INTERFACE_SELECT_DUMMY_0_MASK    0xF80
#define    RTL8370_SELECT_RGMII_1_OFFSET    4
#define    RTL8370_SELECT_RGMII_1_MASK    0x70
#define    RTL8370_DIGITIAL_INTERFACE_SELECT_DUMMY_1_OFFSET    3
#define    RTL8370_DIGITIAL_INTERFACE_SELECT_DUMMY_1_MASK    0x8
#define    RTL8370_SELECT_RGMII_0_OFFSET    0
#define    RTL8370_SELECT_RGMII_0_MASK    0x7

#define    RTL8370_REG_EXT0_RGMXF    0x1306
#define    RTL8370_EXT0_RGMXF_DUMMY_0_OFFSET    5
#define    RTL8370_EXT0_RGMXF_DUMMY_0_MASK    0xFFE0
#define    RTL8370_EXT0_RGMXF_OFFSET    0
#define    RTL8370_EXT0_RGMXF_MASK    0x1F

#define    RTL8370_REG_EXT1_RGMXF    0x1307
#define    RTL8370_EXT1_RGMXF_DUMMY_0_OFFSET    5
#define    RTL8370_EXT1_RGMXF_DUMMY_0_MASK    0xFFE0
#define    RTL8370_EXT1_RGMXF_OFFSET    0
#define    RTL8370_EXT1_RGMXF_MASK    0x1F

#define    RTL8370_REG_BISR_CTRL    0x1308
#define    RTL8370_BISR_CTRL_DUMMY_0_OFFSET    8
#define    RTL8370_BISR_CTRL_DUMMY_0_MASK    0xFF00
#define    RTL8370_SRAM_RDT_OFFSET    7
#define    RTL8370_SRAM_RDT_MASK    0x80
#define    RTL8370_SRAM_WBT_OFFSET    6
#define    RTL8370_SRAM_WBT_MASK    0x40
#define    RTL8370_BISR_COND_OFFSET    4
#define    RTL8370_BISR_COND_MASK    0x30
#define    RTL8370_BISR_CTRL_DUMMY_1_OFFSET    3
#define    RTL8370_BISR_CTRL_DUMMY_1_MASK    0x8
#define    RTL8370_BISR_COND_EN_OFFSET    0
#define    RTL8370_BISR_COND_EN_MASK    0x7

#define    RTL8370_REG_SLF_IF    0x1309
#define    RTL8370_SLF_IF_DUMMY_0_OFFSET    8
#define    RTL8370_SLF_IF_DUMMY_0_MASK    0xFF00
#define    RTL8370_LINK_DOWN_CLR_FIFO_OFFSET    7
#define    RTL8370_LINK_DOWN_CLR_FIFO_MASK    0x80
#define    RTL8370_LOOPBACK_OFFSET    6
#define    RTL8370_LOOPBACK_MASK    0x40
#define    RTL8370_WATER_LEVEL_OFFSET    4
#define    RTL8370_WATER_LEVEL_MASK    0x30
#define    RTL8370_SLF_IF_DUMMY_1_OFFSET    2
#define    RTL8370_SLF_IF_DUMMY_1_MASK    0xC
#define    RTL8370_SLF_IF_OFFSET    0
#define    RTL8370_SLF_IF_MASK    0x3

#define    RTL8370_REG_I2C_CLOCK_DIV    0x130a
#define    RTL8370_I2C_CLOCK_DIV_DUMMY_0_OFFSET    10
#define    RTL8370_I2C_CLOCK_DIV_DUMMY_0_MASK    0xFC00
#define    RTL8370_I2C_CLOCK_DIV_OFFSET    0
#define    RTL8370_I2C_CLOCK_DIV_MASK    0x3FF

#define    RTL8370_REG_MDX_MDC_DIV    0x130b
#define    RTL8370_MDX_MDC_DIV_DUMMY_0_OFFSET    10
#define    RTL8370_MDX_MDC_DIV_DUMMY_0_MASK    0xFC00
#define    RTL8370_MDX_MDC_DIV_OFFSET    0
#define    RTL8370_MDX_MDC_DIV_MASK    0x3FF

#define    RTL8370_REG_MISCELLANEOUS_CONFIGURE0    0x130c
#define    RTL8370_MISCELLANEOUS_CONFIGURE0_DUMMY_0_OFFSET    13
#define    RTL8370_MISCELLANEOUS_CONFIGURE0_DUMMY_0_MASK    0xE000
#define    RTL8370_FLASH_ENABLE_OFFSET    12
#define    RTL8370_FLASH_ENABLE_MASK    0x1000
#define    RTL8370_EEE_ENABLE_OFFSET    11
#define    RTL8370_EEE_ENABLE_MASK    0x800
#define    RTL8370_NIC_ENABLE_OFFSET    10
#define    RTL8370_NIC_ENABLE_MASK    0x400
#define    RTL8370_FT_ENABLE_OFFSET    9
#define    RTL8370_FT_ENABLE_MASK    0x200
#define    RTL8370_OLT_ENABLE_OFFSET    8
#define    RTL8370_OLT_ENABLE_MASK    0x100
#define    RTL8370_RTCT_EN_OFFSET    7
#define    RTL8370_RTCT_EN_MASK    0x80
#define    RTL8370_PON_LIGHT_EN_OFFSET    6
#define    RTL8370_PON_LIGHT_EN_MASK    0x40
#define    RTL8370_DW8051_EN_OFFSET    5
#define    RTL8370_DW8051_EN_MASK    0x20
#define    RTL8370_AUTOLOAD_EN_OFFSET    4
#define    RTL8370_AUTOLOAD_EN_MASK    0x10
#define    RTL8370_SDS_INBAND_EN_OFFSET    3
#define    RTL8370_SDS_INBAND_EN_MASK    0x8
#define    RTL8370_DIS_PON_TABLE_INIT_OFFSET    2
#define    RTL8370_DIS_PON_TABLE_INIT_MASK    0x4
#define    RTL8370_DIS_PON_BIST_OFFSET    1
#define    RTL8370_DIS_PON_BIST_MASK    0x2
#define    RTL8370_EFUSE_EN_OFFSET    0
#define    RTL8370_EFUSE_EN_MASK    0x1

#define    RTL8370_REG_MISCELLANEOUS_CONFIGURE1    0x130d
#define    RTL8370_MISCELLANEOUS_CONFIGURE1_DUMMY_0_OFFSET    15
#define    RTL8370_MISCELLANEOUS_CONFIGURE1_DUMMY_0_MASK    0x8000
#define    RTL8370_EEPROM_DEV_ADR_OFFSET    8
#define    RTL8370_EEPROM_DEV_ADR_MASK    0x7F00
#define    RTL8370_EEPROM_MSB_OFFSET    7
#define    RTL8370_EEPROM_MSB_MASK    0x80
#define    RTL8370_EEPROM_ADDRESS_16B_OFFSET    6
#define    RTL8370_EEPROM_ADDRESS_16B_MASK    0x40
#define    RTL8370_MDX_REQ_POS_OFFSET    0
#define    RTL8370_MDX_REQ_POS_MASK    0x3F

#define    RTL8370_REG_EXTERNAL_PHY_ACC_ENABLE    0x130e
#define    RTL8370_EXTERNAL_PHY_ACC_ENABLE_DUMMY_0_OFFSET    13
#define    RTL8370_EXTERNAL_PHY_ACC_ENABLE_DUMMY_0_MASK    0xE000
#define    RTL8370_INB_SLV_ABLTY_EN_OFFSET    12
#define    RTL8370_INB_SLV_ABLTY_EN_MASK    0x1000
#define    RTL8370_EXTERNAL_PHY_ACC_ENABLE_DUMMY_1_OFFSET    10
#define    RTL8370_EXTERNAL_PHY_ACC_ENABLE_DUMMY_1_MASK    0xC00
#define    RTL8370_RG_POLL_EN_OFFSET    8
#define    RTL8370_RG_POLL_EN_MASK    0x300
#define    RTL8370_SDS1_POLL_EN_OFFSET    4
#define    RTL8370_SDS1_POLL_EN_MASK    0xF0
#define    RTL8370_SDS0_POLL_EN_OFFSET    0
#define    RTL8370_SDS0_POLL_EN_MASK    0xF

#define    RTL8370_REG_PHY_AD    0x130f
#define    RTL8370_PHY_AD_DUMMY_0_OFFSET    13
#define    RTL8370_PHY_AD_DUMMY_0_MASK    0xE000
#define    RTL8370_EXTPHY_AD_OFFSET    8
#define    RTL8370_EXTPHY_AD_MASK    0x1F00
#define    RTL8370_PHY_AD_DUMMY_1_OFFSET    5
#define    RTL8370_PHY_AD_DUMMY_1_MASK    0xE0
#define    RTL8370_INTPHY_AD_OFFSET    0
#define    RTL8370_INTPHY_AD_MASK    0x1F

#define    RTL8370_REG_DIGITIAL_INTERFACE0_FORCE    0x1310
#define    RTL8370_DIGITIAL_INTERFACE0_FORCE_DUMMY_0_OFFSET    13
#define    RTL8370_DIGITIAL_INTERFACE0_FORCE_DUMMY_0_MASK    0xE000
#define    RTL8370_GMII_1_FORCE0_OFFSET    12
#define    RTL8370_GMII_1_FORCE0_MASK    0x1000
#define    RTL8370_RGMII_0_FORCE_OFFSET    0
#define    RTL8370_RGMII_0_FORCE_MASK    0xFFF

#define    RTL8370_REG_DIGITIAL_INTERFACE1_FORCE    0x1311
#define    RTL8370_DIGITIAL_INTERFACE1_FORCE_DUMMY_0_OFFSET    13
#define    RTL8370_DIGITIAL_INTERFACE1_FORCE_DUMMY_0_MASK    0xE000
#define    RTL8370_GMII_1_FORCE1_OFFSET    12
#define    RTL8370_GMII_1_FORCE1_MASK    0x1000
#define    RTL8370_RGMII_1_FORCE_OFFSET    0
#define    RTL8370_RGMII_1_FORCE_MASK    0xFFF

#define    RTL8370_REG_MAC0_FORCE_SELECT    0x1312
#define    RTL8370_MAC0_FORCE_SELECT_DUMMY_0_OFFSET    13
#define    RTL8370_MAC0_FORCE_SELECT_DUMMY_0_MASK    0xE000
#define    RTL8370_EN_MAC0_FORCE_OFFSET    12
#define    RTL8370_EN_MAC0_FORCE_MASK    0x1000
#define    RTL8370_MAC0_FORCE_SELECT_DUMMY_1_OFFSET    10
#define    RTL8370_MAC0_FORCE_SELECT_DUMMY_1_MASK    0xC00
#define    RTL8370_MAC0_FORCE_ABLTY_OFFSET    0
#define    RTL8370_MAC0_FORCE_ABLTY_MASK    0x3FF

#define    RTL8370_REG_MAC1_FORCE_SELECT    0x1313
#define    RTL8370_MAC1_FORCE_SELECT_DUMMY_0_OFFSET    13
#define    RTL8370_MAC1_FORCE_SELECT_DUMMY_0_MASK    0xE000
#define    RTL8370_EN_MAC1_FORCE_OFFSET    12
#define    RTL8370_EN_MAC1_FORCE_MASK    0x1000
#define    RTL8370_MAC1_FORCE_SELECT_DUMMY_1_OFFSET    10
#define    RTL8370_MAC1_FORCE_SELECT_DUMMY_1_MASK    0xC00
#define    RTL8370_MAC1_FORCE_ABLTY_OFFSET    0
#define    RTL8370_MAC1_FORCE_ABLTY_MASK    0x3FF

#define    RTL8370_REG_MAC2_FORCE_SELECT    0x1314
#define    RTL8370_MAC2_FORCE_SELECT_DUMMY_0_OFFSET    13
#define    RTL8370_MAC2_FORCE_SELECT_DUMMY_0_MASK    0xE000
#define    RTL8370_EN_MAC2_FORCE_OFFSET    12
#define    RTL8370_EN_MAC2_FORCE_MASK    0x1000
#define    RTL8370_MAC2_FORCE_SELECT_DUMMY_1_OFFSET    10
#define    RTL8370_MAC2_FORCE_SELECT_DUMMY_1_MASK    0xC00
#define    RTL8370_MAC2_FORCE_ABLTY_OFFSET    0
#define    RTL8370_MAC2_FORCE_ABLTY_MASK    0x3FF

#define    RTL8370_REG_MAC3_FORCE_SELECT    0x1315
#define    RTL8370_MAC3_FORCE_SELECT_DUMMY_0_OFFSET    13
#define    RTL8370_MAC3_FORCE_SELECT_DUMMY_0_MASK    0xE000
#define    RTL8370_EN_MAC3_FORCE_OFFSET    12
#define    RTL8370_EN_MAC3_FORCE_MASK    0x1000
#define    RTL8370_MAC3_FORCE_SELECT_DUMMY_1_OFFSET    10
#define    RTL8370_MAC3_FORCE_SELECT_DUMMY_1_MASK    0xC00
#define    RTL8370_MAC3_FORCE_ABLTY_OFFSET    0
#define    RTL8370_MAC3_FORCE_ABLTY_MASK    0x3FF

#define    RTL8370_REG_MAC4_FORCE_SELECT    0x1316
#define    RTL8370_MAC4_FORCE_SELECT_DUMMY_0_OFFSET    13
#define    RTL8370_MAC4_FORCE_SELECT_DUMMY_0_MASK    0xE000
#define    RTL8370_EN_MAC4_FORCE_OFFSET    12
#define    RTL8370_EN_MAC4_FORCE_MASK    0x1000
#define    RTL8370_MAC4_FORCE_SELECT_DUMMY_1_OFFSET    10
#define    RTL8370_MAC4_FORCE_SELECT_DUMMY_1_MASK    0xC00
#define    RTL8370_MAC4_FORCE_ABLTY_OFFSET    0
#define    RTL8370_MAC4_FORCE_ABLTY_MASK    0x3FF

#define    RTL8370_REG_MAC5_FORCE_SELECT    0x1317
#define    RTL8370_MAC5_FORCE_SELECT_DUMMY_0_OFFSET    13
#define    RTL8370_MAC5_FORCE_SELECT_DUMMY_0_MASK    0xE000
#define    RTL8370_EN_MAC5_FORCE_OFFSET    12
#define    RTL8370_EN_MAC5_FORCE_MASK    0x1000
#define    RTL8370_MAC5_FORCE_SELECT_DUMMY_1_OFFSET    10
#define    RTL8370_MAC5_FORCE_SELECT_DUMMY_1_MASK    0xC00
#define    RTL8370_MAC5_FORCE_ABLTY_OFFSET    0
#define    RTL8370_MAC5_FORCE_ABLTY_MASK    0x3FF

#define    RTL8370_REG_MAC6_FORCE_SELECT    0x1318
#define    RTL8370_MAC6_FORCE_SELECT_DUMMY_0_OFFSET    13
#define    RTL8370_MAC6_FORCE_SELECT_DUMMY_0_MASK    0xE000
#define    RTL8370_EN_MAC6_FORCE_OFFSET    12
#define    RTL8370_EN_MAC6_FORCE_MASK    0x1000
#define    RTL8370_MAC6_FORCE_SELECT_DUMMY_1_OFFSET    10
#define    RTL8370_MAC6_FORCE_SELECT_DUMMY_1_MASK    0xC00
#define    RTL8370_MAC6_FORCE_ABLTY_OFFSET    0
#define    RTL8370_MAC6_FORCE_ABLTY_MASK    0x3FF

#define    RTL8370_REG_MAC7_FORCE_SELECT    0x1319
#define    RTL8370_MAC7_FORCE_SELECT_DUMMY_0_OFFSET    13
#define    RTL8370_MAC7_FORCE_SELECT_DUMMY_0_MASK    0xE000
#define    RTL8370_EN_MAC7_FORCE_OFFSET    12
#define    RTL8370_EN_MAC7_FORCE_MASK    0x1000
#define    RTL8370_MAC7_FORCE_SELECT_DUMMY_1_OFFSET    10
#define    RTL8370_MAC7_FORCE_SELECT_DUMMY_1_MASK    0xC00
#define    RTL8370_MAC7_FORCE_ABLTY_OFFSET    0
#define    RTL8370_MAC7_FORCE_ABLTY_MASK    0x3FF

#define    RTL8370_REG_SDS0_FORCE_EXT_MAC0    0x131a
#define    RTL8370_SDS0_FORCE_EXT_MAC0_DUMMY_0_OFFSET    13
#define    RTL8370_SDS0_FORCE_EXT_MAC0_DUMMY_0_MASK    0xE000
#define    RTL8370_EN_SDS_EXT_MAC0_FORCE_OFFSET    12
#define    RTL8370_EN_SDS_EXT_MAC0_FORCE_MASK    0x1000
#define    RTL8370_SDS0_FORCE_EXT_MAC0_DUMMY_1_OFFSET    10
#define    RTL8370_SDS0_FORCE_EXT_MAC0_DUMMY_1_MASK    0xC00
#define    RTL8370_SDS0_EXT_MAC0_FORCE_ABLTY_OFFSET    0
#define    RTL8370_SDS0_EXT_MAC0_FORCE_ABLTY_MASK    0x3FF

#define    RTL8370_REG_SDS0_FORCE_EXT_MAC1    0x131b
#define    RTL8370_SDS0_FORCE_EXT_MAC1_DUMMY_0_OFFSET    13
#define    RTL8370_SDS0_FORCE_EXT_MAC1_DUMMY_0_MASK    0xE000
#define    RTL8370_EN_SDS_EXT_MAC1_FORCE_OFFSET    12
#define    RTL8370_EN_SDS_EXT_MAC1_FORCE_MASK    0x1000
#define    RTL8370_SDS0_FORCE_EXT_MAC1_DUMMY_1_OFFSET    10
#define    RTL8370_SDS0_FORCE_EXT_MAC1_DUMMY_1_MASK    0xC00
#define    RTL8370_SDS0_EXT_MAC1_FORCE_ABLTY_OFFSET    0
#define    RTL8370_SDS0_EXT_MAC1_FORCE_ABLTY_MASK    0x3FF

#define    RTL8370_REG_SDS0_FORCE_EXT_MAC2    0x131c
#define    RTL8370_SDS0_FORCE_EXT_MAC2_DUMMY_0_OFFSET    13
#define    RTL8370_SDS0_FORCE_EXT_MAC2_DUMMY_0_MASK    0xE000
#define    RTL8370_EN_SDS_EXT_MAC2_FORCE_OFFSET    12
#define    RTL8370_EN_SDS_EXT_MAC2_FORCE_MASK    0x1000
#define    RTL8370_SDS0_FORCE_EXT_MAC2_DUMMY_1_OFFSET    10
#define    RTL8370_SDS0_FORCE_EXT_MAC2_DUMMY_1_MASK    0xC00
#define    RTL8370_SDS0_EXT_MAC2_FORCE_ABLTY_OFFSET    0
#define    RTL8370_SDS0_EXT_MAC2_FORCE_ABLTY_MASK    0x3FF

#define    RTL8370_REG_SDS0_FORCE_EXT_MAC3    0x131d
#define    RTL8370_SDS0_FORCE_EXT_MAC3_DUMMY_0_OFFSET    13
#define    RTL8370_SDS0_FORCE_EXT_MAC3_DUMMY_0_MASK    0xE000
#define    RTL8370_EN_SDS_EXT_MAC3_FORCE_OFFSET    12
#define    RTL8370_EN_SDS_EXT_MAC3_FORCE_MASK    0x1000
#define    RTL8370_SDS0_FORCE_EXT_MAC3_DUMMY_1_OFFSET    10
#define    RTL8370_SDS0_FORCE_EXT_MAC3_DUMMY_1_MASK    0xC00
#define    RTL8370_SDS0_EXT_MAC3_FORCE_ABLTY_OFFSET    0
#define    RTL8370_SDS0_EXT_MAC3_FORCE_ABLTY_MASK    0x3FF

#define    RTL8370_REG_SDS1_FORCE_EXT_MAC4    0x131e
#define    RTL8370_SDS1_FORCE_EXT_MAC4_DUMMY_0_OFFSET    13
#define    RTL8370_SDS1_FORCE_EXT_MAC4_DUMMY_0_MASK    0xE000
#define    RTL8370_EN_SDS_EXT_MAC4_FORCE_OFFSET    12
#define    RTL8370_EN_SDS_EXT_MAC4_FORCE_MASK    0x1000
#define    RTL8370_SDS1_FORCE_EXT_MAC4_DUMMY_1_OFFSET    10
#define    RTL8370_SDS1_FORCE_EXT_MAC4_DUMMY_1_MASK    0xC00
#define    RTL8370_SDS1_EXT_MAC4_FORCE_ABLTY_OFFSET    0
#define    RTL8370_SDS1_EXT_MAC4_FORCE_ABLTY_MASK    0x3FF

#define    RTL8370_REG_SDS1_FORCE_EXT_MAC5    0x131f
#define    RTL8370_SDS1_FORCE_EXT_MAC5_DUMMY_0_OFFSET    13
#define    RTL8370_SDS1_FORCE_EXT_MAC5_DUMMY_0_MASK    0xE000
#define    RTL8370_EN_SDS_EXT_MAC5_FORCE_OFFSET    12
#define    RTL8370_EN_SDS_EXT_MAC5_FORCE_MASK    0x1000
#define    RTL8370_SDS1_FORCE_EXT_MAC5_DUMMY_1_OFFSET    10
#define    RTL8370_SDS1_FORCE_EXT_MAC5_DUMMY_1_MASK    0xC00
#define    RTL8370_SDS1_EXT_MAC5_FORCE_ABLTY_OFFSET    0
#define    RTL8370_SDS1_EXT_MAC5_FORCE_ABLTY_MASK    0x3FF

#define    RTL8370_REG_SDS1_FORCE_EXT_MAC6    0x1320
#define    RTL8370_SDS1_FORCE_EXT_MAC6_DUMMY_0_OFFSET    13
#define    RTL8370_SDS1_FORCE_EXT_MAC6_DUMMY_0_MASK    0xE000
#define    RTL8370_EN_SDS_EXT_MAC6_FORCE_OFFSET    12
#define    RTL8370_EN_SDS_EXT_MAC6_FORCE_MASK    0x1000
#define    RTL8370_SDS1_FORCE_EXT_MAC6_DUMMY_1_OFFSET    10
#define    RTL8370_SDS1_FORCE_EXT_MAC6_DUMMY_1_MASK    0xC00
#define    RTL8370_SDS1_EXT_MAC6_FORCE_ABLTY_OFFSET    0
#define    RTL8370_SDS1_EXT_MAC6_FORCE_ABLTY_MASK    0x3FF

#define    RTL8370_REG_SDS1_FORCE_EXT_MAC7    0x1321
#define    RTL8370_SDS1_FORCE_EXT_MAC7_DUMMY_0_OFFSET    13
#define    RTL8370_SDS1_FORCE_EXT_MAC7_DUMMY_0_MASK    0xE000
#define    RTL8370_EN_SDS_EXT_MAC7_FORCE_OFFSET    12
#define    RTL8370_EN_SDS_EXT_MAC7_FORCE_MASK    0x1000
#define    RTL8370_SDS1_FORCE_EXT_MAC7_DUMMY_1_OFFSET    10
#define    RTL8370_SDS1_FORCE_EXT_MAC7_DUMMY_1_MASK    0xC00
#define    RTL8370_SDS1_EXT_MAC7_FORCE_ABLTY_OFFSET    0
#define    RTL8370_SDS1_EXT_MAC7_FORCE_ABLTY_MASK    0x3FF

#define    RTL8370_REG_CHIP_RESET    0x1322
#define    RTL8370_CHIP_RESET_DUMMY_0_OFFSET    6
#define    RTL8370_CHIP_RESET_DUMMY_0_MASK    0xFFC0
#define    RTL8370_NIC_RST_OFFSET    5
#define    RTL8370_NIC_RST_MASK    0x20
#define    RTL8370_DW8051_RST_OFFSET    4
#define    RTL8370_DW8051_RST_MASK    0x10
#define    RTL8370_CONFIG_RST_OFFSET    2
#define    RTL8370_CONFIG_RST_MASK    0x4
#define    RTL8370_SW_RST_OFFSET    1
#define    RTL8370_SW_RST_MASK    0x2
#define    RTL8370_CHIP_RST_OFFSET    0
#define    RTL8370_CHIP_RST_MASK    0x1

#define    RTL8370_REG_DIGITIAL_DEBUG_0    0x1323

#define    RTL8370_REG_DIGITIAL_DEBUG_1    0x1324

#define    RTL8370_REG_INTERNAL_PHY_MDC_DRIVER    0x1325
#define    RTL8370_INTERNAL_PHY_MDC_DRIVER_DUMMY_0_OFFSET    10
#define    RTL8370_INTERNAL_PHY_MDC_DRIVER_DUMMY_0_MASK    0xFC00
#define    RTL8370_GPHY_MDX_MDC_DRV_OFFSET    0
#define    RTL8370_GPHY_MDX_MDC_DRV_MASK    0x3FF

#define    RTL8370_REG_LINKDOWN_TIME_CTRL    0x1326
#define    RTL8370_LINKDOWN_TIME_CTRL_DUMMY_0_OFFSET    9
#define    RTL8370_LINKDOWN_TIME_CTRL_DUMMY_0_MASK    0xFE00
#define    RTL8370_LINKDOWN_TIME_ENABLE_OFFSET    8
#define    RTL8370_LINKDOWN_TIME_ENABLE_MASK    0x100
#define    RTL8370_LINKDOWN_TIME_OFFSET    0
#define    RTL8370_LINKDOWN_TIME_MASK    0xFF

#define    RTL8370_REG_POLL_DELAY_CYCLE    0x1327

#define    RTL8370_REG_MEM_EMA    0x1330
#define    RTL8370_MEM_EMA_DUMMY_0_OFFSET    9
#define    RTL8370_MEM_EMA_DUMMY_0_MASK    0xFE00
#define    RTL8370_ERAM_EMA_OFFSET    6
#define    RTL8370_ERAM_EMA_MASK    0x1C0
#define    RTL8370_IRAM_EMA_OFFSET    3
#define    RTL8370_IRAM_EMA_MASK    0x38
#define    RTL8370_IROM_EMA_OFFSET    0
#define    RTL8370_IROM_EMA_MASK    0x7

#define    RTL8370_REG_PHYACK_TIMEOUT    0x1331

#define    RTL8370_REG_SDSACK_TIMEOUT    0x1332

#define    RTL8370_REG_MDXACK_TIMEOUT    0x1333

#define    RTL8370_REG_DRF_BIST_CTRL    0x1334
#define    RTL8370_DRF_BIST_CTRL_DUMMY_0_OFFSET    6
#define    RTL8370_DRF_BIST_CTRL_DUMMY_0_MASK    0xFFC0
#define    RTL8370_DRF_TEST_RESUME_PS_OFFSET    5
#define    RTL8370_DRF_TEST_RESUME_PS_MASK    0x20
#define    RTL8370_BIST_MODE_ALL_OFFSET    4
#define    RTL8370_BIST_MODE_ALL_MASK    0x10
#define    RTL8370_DRT_BIST_MODE_8051_OFFSET    1
#define    RTL8370_DRT_BIST_MODE_8051_MASK    0xE
#define    RTL8370_DRF_ENABLE_OFFSET    0
#define    RTL8370_DRF_ENABLE_MASK    0x1

#define    RTL8370_REG_BIST_STS_8051    0x1335

#define    RTL8370_REG_DW8051_RDY    0x1336
#define    RTL8370_DW8051_RDY_DUMMY_0_OFFSET    8
#define    RTL8370_DW8051_RDY_DUMMY_0_MASK    0xFF00
#define    RTL8370_RRCP_MDOE_OFFSET    7
#define    RTL8370_RRCP_MDOE_MASK    0x80
#define    RTL8370_DW8051_RATE_OFFSET    4
#define    RTL8370_DW8051_RATE_MASK    0x70
#define    RTL8370_IROM_MSB_OFFSET    2
#define    RTL8370_IROM_MSB_MASK    0xC
#define    RTL8370_ACS_IROM_ENABLE_OFFSET    1
#define    RTL8370_ACS_IROM_ENABLE_MASK    0x2
#define    RTL8370_DW8051_READY_OFFSET    0
#define    RTL8370_DW8051_READY_MASK    0x1

#define    RTL8370_REG_DW8051_MEM_MODE    0x1337
#define    RTL8370_DW8051_MEM_MODE_DUMMY_0_OFFSET    7
#define    RTL8370_DW8051_MEM_MODE_DUMMY_0_MASK    0xFF80
#define    RTL8370_DIAG_MODE_DW8051_EROM_OFFSET    6
#define    RTL8370_DIAG_MODE_DW8051_EROM_MASK    0x40
#define    RTL8370_DIAG_MODE_DW8051_IROM_OFFSET    5
#define    RTL8370_DIAG_MODE_DW8051_IROM_MASK    0x20
#define    RTL8370_DIAG_MODE_DW8051_IRAM_OFFSET    4
#define    RTL8370_DIAG_MODE_DW8051_IRAM_MASK    0x10
#define    RTL8370_DW8051_MEM_MODE_DUMMY_1_OFFSET    3
#define    RTL8370_DW8051_MEM_MODE_DUMMY_1_MASK    0x8
#define    RTL8370_BIST_MODE_DW8051_EROM_OFFSET    2
#define    RTL8370_BIST_MODE_DW8051_EROM_MASK    0x4
#define    RTL8370_BIST_MODE_DW8051_IROM_OFFSET    1
#define    RTL8370_BIST_MODE_DW8051_IROM_MASK    0x2
#define    RTL8370_BIST_MODE_DW8051_IRAM_OFFSET    0
#define    RTL8370_BIST_MODE_DW8051_IRAM_MASK    0x1

#define    RTL8370_REG_BIST_DONE    0x1338

#define    RTL8370_REG_COND0_BIST_FAIL    0x1339

#define    RTL8370_REG_COND1_BIST_FAIL    0x133a

#define    RTL8370_REG_COND2_BIST_FAIL    0x133b

#define    RTL8370_REG_BIST_PASS    0x133c
#define    RTL8370_BIST_PASS_OFFSET    0
#define    RTL8370_BIST_PASS_MASK    0x7

#define    RTL8370_REG_DIAG_MODE2    0x133d
#define    RTL8370_DIAG_MODE2_DUMMY_0_OFFSET    4
#define    RTL8370_DIAG_MODE2_DUMMY_0_MASK    0xFFF0
#define    RTL8370_DIAG_MODE2_DW8051RAM_OFFSET    3
#define    RTL8370_DIAG_MODE2_DW8051RAM_MASK    0x8
#define    RTL8370_DIAG_MODE2_MIBRAM_OFFSET    2
#define    RTL8370_DIAG_MODE2_MIBRAM_MASK    0x4
#define    RTL8370_DIAG_MODE2_ACTRAM_OFFSET    1
#define    RTL8370_DIAG_MODE2_ACTRAM_MASK    0x2
#define    RTL8370_DIAG_MODE2_BCAM_ACTION_OFFSET    0
#define    RTL8370_DIAG_MODE2_BCAM_ACTION_MASK    0x1

#define    RTL8370_REG_MDX_PHY_REG0    0x133e
#define    RTL8370_MDX_PHY_REG0_DUMMY_0_OFFSET    12
#define    RTL8370_MDX_PHY_REG0_DUMMY_0_MASK    0xF000
#define    RTL8370_PHY_BRD_MASK_OFFSET    4
#define    RTL8370_PHY_BRD_MASK_MASK    0xFF0
#define    RTL8370_MDX_INDACC_PAGE_OFFSET    0
#define    RTL8370_MDX_INDACC_PAGE_MASK    0xF

#define    RTL8370_REG_MDX_PHY_REG1    0x133f
#define    RTL8370_MDX_PHY_REG1_DUMMY_0_OFFSET    6
#define    RTL8370_MDX_PHY_REG1_DUMMY_0_MASK    0xFFC0
#define    RTL8370_PHY_BRD_MODE_OFFSET    5
#define    RTL8370_PHY_BRD_MODE_MASK    0x20
#define    RTL8370_BRD_PHYAD_OFFSET    0
#define    RTL8370_BRD_PHYAD_MASK    0x1F

#define    RTL8370_REG_DEBUG_SIGNAL_SELECT_A    0x1340

#define    RTL8370_REG_DEBUG_SIGNAL_SELECT_B    0x1341

#define    RTL8370_REG_DEBUG_SIGNAL_SELECT_C    0x1342

#define    RTL8370_REG_DEBUG_SIGNAL_I    0x1343

#define    RTL8370_REG_DEBUG_SIGNAL__H    0x1344

#define    RTL8370_REG_UNKNOWN_0    0x1345

#define    RTL8370_REG_UNKNOWN_1    0x1346

#define    RTL8370_REG_UNKNOWN_2    0x1347

#define    RTL8370_REG_UNKNOWN_3    0x1348

#define    RTL8370_REG_BYPASS_ABLTY_LOCK    0x1349
#define    RTL8370_BYPASS_SDS_1_OFFSET    12
#define    RTL8370_BYPASS_SDS_1_MASK    0xF000
#define    RTL8370_BYPASS_SDS_0_OFFSET    8
#define    RTL8370_BYPASS_SDS_0_MASK    0xF00
#define    RTL8370_BYPASS_PHY_OFFSET    0
#define    RTL8370_BYPASS_PHY_MASK    0xFF

#define    RTL8370_REG_EN_GPIO    0x1350
#define    RTL8370_EN_GPIO_DUMMY_0_OFFSET    8
#define    RTL8370_EN_GPIO_DUMMY_0_MASK    0xFF00
#define    RTL8370_EN_GPIO_7_OFFSET    7
#define    RTL8370_EN_GPIO_7_MASK    0x80
#define    RTL8370_EN_GPIO_6_OFFSET    6
#define    RTL8370_EN_GPIO_6_MASK    0x40
#define    RTL8370_EN_GPIO_5_OFFSET    5
#define    RTL8370_EN_GPIO_5_MASK    0x20
#define    RTL8370_EN_GPIO_4_OFFSET    4
#define    RTL8370_EN_GPIO_4_MASK    0x10
#define    RTL8370_EN_GPIO_3_OFFSET    3
#define    RTL8370_EN_GPIO_3_MASK    0x8
#define    RTL8370_EN_GPIO_2_OFFSET    2
#define    RTL8370_EN_GPIO_2_MASK    0x4
#define    RTL8370_EN_GPIO_1_OFFSET    1
#define    RTL8370_EN_GPIO_1_MASK    0x2
#define    RTL8370_EN_GPIO_0_OFFSET    0
#define    RTL8370_EN_GPIO_0_MASK    0x1

#define    RTL8370_REG_CFG_MULTI_PIN    0x1351
#define    RTL8370_CFG_MULTI_PIN_DUMMY_0_OFFSET    2
#define    RTL8370_CFG_MULTI_PIN_DUMMY_0_MASK    0xFFFC
#define    RTL8370_EN_8051_OFFSET    0
#define    RTL8370_EN_8051_MASK    0x3

#define    RTL8370_REG_PORT0_STATUS    0x1352
#define    RTL8370_PORT0_STATUS_EN_1000_LPI_OFFSET    11
#define    RTL8370_PORT0_STATUS_EN_1000_LPI_MASK    0x800
#define    RTL8370_PORT0_STATUS_EN_100_LPI_OFFSET    10
#define    RTL8370_PORT0_STATUS_EN_100_LPI_MASK    0x400
#define    RTL8370_PORT0_STATUS_NWAY_FAULT_OFFSET    9
#define    RTL8370_PORT0_STATUS_NWAY_FAULT_MASK    0x200
#define    RTL8370_PORT0_STATUS_LINK_ON_MASTER_OFFSET    8
#define    RTL8370_PORT0_STATUS_LINK_ON_MASTER_MASK    0x100
#define    RTL8370_PORT0_STATUS_NWAY_CAP_OFFSET    7
#define    RTL8370_PORT0_STATUS_NWAY_CAP_MASK    0x80
#define    RTL8370_PORT0_STATUS_TX_FLOWCTRL_CAP_OFFSET    6
#define    RTL8370_PORT0_STATUS_TX_FLOWCTRL_CAP_MASK    0x40
#define    RTL8370_PORT0_STATUS_RX_FLOWCTRL_CAP_OFFSET    5
#define    RTL8370_PORT0_STATUS_RX_FLOWCTRL_CAP_MASK    0x20
#define    RTL8370_PORT0_STATUS_LINK_STATE_OFFSET    4
#define    RTL8370_PORT0_STATUS_LINK_STATE_MASK    0x10
#define    RTL8370_PORT0_STATUS_FULL_DUPLUX_CAP_OFFSET    2
#define    RTL8370_PORT0_STATUS_FULL_DUPLUX_CAP_MASK    0x4
#define    RTL8370_PORT0_STATUS_LINK_SPEED_OFFSET    0
#define    RTL8370_PORT0_STATUS_LINK_SPEED_MASK    0x3

#define    RTL8370_REG_PORT1_STATUS    0x1353
#define    RTL8370_PORT1_STATUS_EN_1000_LPI_OFFSET    11
#define    RTL8370_PORT1_STATUS_EN_1000_LPI_MASK    0x800
#define    RTL8370_PORT1_STATUS_EN_100_LPI_OFFSET    10
#define    RTL8370_PORT1_STATUS_EN_100_LPI_MASK    0x400
#define    RTL8370_PORT1_STATUS_NWAY_FAULT_OFFSET    9
#define    RTL8370_PORT1_STATUS_NWAY_FAULT_MASK    0x200
#define    RTL8370_PORT1_STATUS_LINK_ON_MASTER_OFFSET    8
#define    RTL8370_PORT1_STATUS_LINK_ON_MASTER_MASK    0x100
#define    RTL8370_PORT1_STATUS_NWAY_CAP_OFFSET    7
#define    RTL8370_PORT1_STATUS_NWAY_CAP_MASK    0x80
#define    RTL8370_PORT1_STATUS_TX_FLOWCTRL_CAP_OFFSET    6
#define    RTL8370_PORT1_STATUS_TX_FLOWCTRL_CAP_MASK    0x40
#define    RTL8370_PORT1_STATUS_RX_FLOWCTRL_CAP_OFFSET    5
#define    RTL8370_PORT1_STATUS_RX_FLOWCTRL_CAP_MASK    0x20
#define    RTL8370_PORT1_STATUS_LINK_STATE_OFFSET    4
#define    RTL8370_PORT1_STATUS_LINK_STATE_MASK    0x10
#define    RTL8370_PORT1_STATUS_FULL_DUPLUX_CAP_OFFSET    2
#define    RTL8370_PORT1_STATUS_FULL_DUPLUX_CAP_MASK    0x4
#define    RTL8370_PORT1_STATUS_LINK_SPEED_OFFSET    0
#define    RTL8370_PORT1_STATUS_LINK_SPEED_MASK    0x3

#define    RTL8370_REG_PORT2_STATUS    0x1354
#define    RTL8370_PORT2_STATUS_EN_1000_LPI_OFFSET    11
#define    RTL8370_PORT2_STATUS_EN_1000_LPI_MASK    0x800
#define    RTL8370_PORT2_STATUS_EN_100_LPI_OFFSET    10
#define    RTL8370_PORT2_STATUS_EN_100_LPI_MASK    0x400
#define    RTL8370_PORT2_STATUS_NWAY_FAULT_OFFSET    9
#define    RTL8370_PORT2_STATUS_NWAY_FAULT_MASK    0x200
#define    RTL8370_PORT2_STATUS_LINK_ON_MASTER_OFFSET    8
#define    RTL8370_PORT2_STATUS_LINK_ON_MASTER_MASK    0x100
#define    RTL8370_PORT2_STATUS_NWAY_CAP_OFFSET    7
#define    RTL8370_PORT2_STATUS_NWAY_CAP_MASK    0x80
#define    RTL8370_PORT2_STATUS_TX_FLOWCTRL_CAP_OFFSET    6
#define    RTL8370_PORT2_STATUS_TX_FLOWCTRL_CAP_MASK    0x40
#define    RTL8370_PORT2_STATUS_RX_FLOWCTRL_CAP_OFFSET    5
#define    RTL8370_PORT2_STATUS_RX_FLOWCTRL_CAP_MASK    0x20
#define    RTL8370_PORT2_STATUS_LINK_STATE_OFFSET    4
#define    RTL8370_PORT2_STATUS_LINK_STATE_MASK    0x10
#define    RTL8370_PORT2_STATUS_FULL_DUPLUX_CAP_OFFSET    2
#define    RTL8370_PORT2_STATUS_FULL_DUPLUX_CAP_MASK    0x4
#define    RTL8370_PORT2_STATUS_LINK_SPEED_OFFSET    0
#define    RTL8370_PORT2_STATUS_LINK_SPEED_MASK    0x3

#define    RTL8370_REG_PORT3_STATUS    0x1355
#define    RTL8370_PORT3_STATUS_EN_1000_LPI_OFFSET    11
#define    RTL8370_PORT3_STATUS_EN_1000_LPI_MASK    0x800
#define    RTL8370_PORT3_STATUS_EN_100_LPI_OFFSET    10
#define    RTL8370_PORT3_STATUS_EN_100_LPI_MASK    0x400
#define    RTL8370_PORT3_STATUS_NWAY_FAULT_OFFSET    9
#define    RTL8370_PORT3_STATUS_NWAY_FAULT_MASK    0x200
#define    RTL8370_PORT3_STATUS_LINK_ON_MASTER_OFFSET    8
#define    RTL8370_PORT3_STATUS_LINK_ON_MASTER_MASK    0x100
#define    RTL8370_PORT3_STATUS_NWAY_CAP_OFFSET    7
#define    RTL8370_PORT3_STATUS_NWAY_CAP_MASK    0x80
#define    RTL8370_PORT3_STATUS_TX_FLOWCTRL_CAP_OFFSET    6
#define    RTL8370_PORT3_STATUS_TX_FLOWCTRL_CAP_MASK    0x40
#define    RTL8370_PORT3_STATUS_RX_FLOWCTRL_CAP_OFFSET    5
#define    RTL8370_PORT3_STATUS_RX_FLOWCTRL_CAP_MASK    0x20
#define    RTL8370_PORT3_STATUS_LINK_STATE_OFFSET    4
#define    RTL8370_PORT3_STATUS_LINK_STATE_MASK    0x10
#define    RTL8370_PORT3_STATUS_FULL_DUPLUX_CAP_OFFSET    2
#define    RTL8370_PORT3_STATUS_FULL_DUPLUX_CAP_MASK    0x4
#define    RTL8370_PORT3_STATUS_LINK_SPEED_OFFSET    0
#define    RTL8370_PORT3_STATUS_LINK_SPEED_MASK    0x3

#define    RTL8370_REG_PORT4_STATUS    0x1356
#define    RTL8370_PORT4_STATUS_EN_1000_LPI_OFFSET    11
#define    RTL8370_PORT4_STATUS_EN_1000_LPI_MASK    0x800
#define    RTL8370_PORT4_STATUS_EN_100_LPI_OFFSET    10
#define    RTL8370_PORT4_STATUS_EN_100_LPI_MASK    0x400
#define    RTL8370_PORT4_STATUS_NWAY_FAULT_OFFSET    9
#define    RTL8370_PORT4_STATUS_NWAY_FAULT_MASK    0x200
#define    RTL8370_PORT4_STATUS_LINK_ON_MASTER_OFFSET    8
#define    RTL8370_PORT4_STATUS_LINK_ON_MASTER_MASK    0x100
#define    RTL8370_PORT4_STATUS_NWAY_CAP_OFFSET    7
#define    RTL8370_PORT4_STATUS_NWAY_CAP_MASK    0x80
#define    RTL8370_PORT4_STATUS_TX_FLOWCTRL_CAP_OFFSET    6
#define    RTL8370_PORT4_STATUS_TX_FLOWCTRL_CAP_MASK    0x40
#define    RTL8370_PORT4_STATUS_RX_FLOWCTRL_CAP_OFFSET    5
#define    RTL8370_PORT4_STATUS_RX_FLOWCTRL_CAP_MASK    0x20
#define    RTL8370_PORT4_STATUS_LINK_STATE_OFFSET    4
#define    RTL8370_PORT4_STATUS_LINK_STATE_MASK    0x10
#define    RTL8370_PORT4_STATUS_FULL_DUPLUX_CAP_OFFSET    2
#define    RTL8370_PORT4_STATUS_FULL_DUPLUX_CAP_MASK    0x4
#define    RTL8370_PORT4_STATUS_LINK_SPEED_OFFSET    0
#define    RTL8370_PORT4_STATUS_LINK_SPEED_MASK    0x3

#define    RTL8370_REG_PORT5_STATUS    0x1357
#define    RTL8370_PORT5_STATUS_EN_1000_LPI_OFFSET    11
#define    RTL8370_PORT5_STATUS_EN_1000_LPI_MASK    0x800
#define    RTL8370_PORT5_STATUS_EN_100_LPI_OFFSET    10
#define    RTL8370_PORT5_STATUS_EN_100_LPI_MASK    0x400
#define    RTL8370_PORT5_STATUS_NWAY_FAULT_OFFSET    9
#define    RTL8370_PORT5_STATUS_NWAY_FAULT_MASK    0x200
#define    RTL8370_PORT5_STATUS_LINK_ON_MASTER_OFFSET    8
#define    RTL8370_PORT5_STATUS_LINK_ON_MASTER_MASK    0x100
#define    RTL8370_PORT5_STATUS_NWAY_CAP_OFFSET    7
#define    RTL8370_PORT5_STATUS_NWAY_CAP_MASK    0x80
#define    RTL8370_PORT5_STATUS_TX_FLOWCTRL_CAP_OFFSET    6
#define    RTL8370_PORT5_STATUS_TX_FLOWCTRL_CAP_MASK    0x40
#define    RTL8370_PORT5_STATUS_RX_FLOWCTRL_CAP_OFFSET    5
#define    RTL8370_PORT5_STATUS_RX_FLOWCTRL_CAP_MASK    0x20
#define    RTL8370_PORT5_STATUS_LINK_STATE_OFFSET    4
#define    RTL8370_PORT5_STATUS_LINK_STATE_MASK    0x10
#define    RTL8370_PORT5_STATUS_FULL_DUPLUX_CAP_OFFSET    2
#define    RTL8370_PORT5_STATUS_FULL_DUPLUX_CAP_MASK    0x4
#define    RTL8370_PORT5_STATUS_LINK_SPEED_OFFSET    0
#define    RTL8370_PORT5_STATUS_LINK_SPEED_MASK    0x3

#define    RTL8370_REG_PORT6_STATUS    0x1358
#define    RTL8370_PORT6_STATUS_EN_1000_LPI_OFFSET    11
#define    RTL8370_PORT6_STATUS_EN_1000_LPI_MASK    0x800
#define    RTL8370_PORT6_STATUS_EN_100_LPI_OFFSET    10
#define    RTL8370_PORT6_STATUS_EN_100_LPI_MASK    0x400
#define    RTL8370_PORT6_STATUS_NWAY_FAULT_OFFSET    9
#define    RTL8370_PORT6_STATUS_NWAY_FAULT_MASK    0x200
#define    RTL8370_PORT6_STATUS_LINK_ON_MASTER_OFFSET    8
#define    RTL8370_PORT6_STATUS_LINK_ON_MASTER_MASK    0x100
#define    RTL8370_PORT6_STATUS_NWAY_CAP_OFFSET    7
#define    RTL8370_PORT6_STATUS_NWAY_CAP_MASK    0x80
#define    RTL8370_PORT6_STATUS_TX_FLOWCTRL_CAP_OFFSET    6
#define    RTL8370_PORT6_STATUS_TX_FLOWCTRL_CAP_MASK    0x40
#define    RTL8370_PORT6_STATUS_RX_FLOWCTRL_CAP_OFFSET    5
#define    RTL8370_PORT6_STATUS_RX_FLOWCTRL_CAP_MASK    0x20
#define    RTL8370_PORT6_STATUS_LINK_STATE_OFFSET    4
#define    RTL8370_PORT6_STATUS_LINK_STATE_MASK    0x10
#define    RTL8370_PORT6_STATUS_FULL_DUPLUX_CAP_OFFSET    2
#define    RTL8370_PORT6_STATUS_FULL_DUPLUX_CAP_MASK    0x4
#define    RTL8370_PORT6_STATUS_LINK_SPEED_OFFSET    0
#define    RTL8370_PORT6_STATUS_LINK_SPEED_MASK    0x3

#define    RTL8370_REG_PORT7_STATUS    0x1359
#define    RTL8370_PORT7_STATUS_EN_1000_LPI_OFFSET    11
#define    RTL8370_PORT7_STATUS_EN_1000_LPI_MASK    0x800
#define    RTL8370_PORT7_STATUS_EN_100_LPI_OFFSET    10
#define    RTL8370_PORT7_STATUS_EN_100_LPI_MASK    0x400
#define    RTL8370_PORT7_STATUS_NWAY_FAULT_OFFSET    9
#define    RTL8370_PORT7_STATUS_NWAY_FAULT_MASK    0x200
#define    RTL8370_PORT7_STATUS_LINK_ON_MASTER_OFFSET    8
#define    RTL8370_PORT7_STATUS_LINK_ON_MASTER_MASK    0x100
#define    RTL8370_PORT7_STATUS_NWAY_CAP_OFFSET    7
#define    RTL8370_PORT7_STATUS_NWAY_CAP_MASK    0x80
#define    RTL8370_PORT7_STATUS_TX_FLOWCTRL_CAP_OFFSET    6
#define    RTL8370_PORT7_STATUS_TX_FLOWCTRL_CAP_MASK    0x40
#define    RTL8370_PORT7_STATUS_RX_FLOWCTRL_CAP_OFFSET    5
#define    RTL8370_PORT7_STATUS_RX_FLOWCTRL_CAP_MASK    0x20
#define    RTL8370_PORT7_STATUS_LINK_STATE_OFFSET    4
#define    RTL8370_PORT7_STATUS_LINK_STATE_MASK    0x10
#define    RTL8370_PORT7_STATUS_FULL_DUPLUX_CAP_OFFSET    2
#define    RTL8370_PORT7_STATUS_FULL_DUPLUX_CAP_MASK    0x4
#define    RTL8370_PORT7_STATUS_LINK_SPEED_OFFSET    0
#define    RTL8370_PORT7_STATUS_LINK_SPEED_MASK    0x3

#define    RTL8370_REG_PORT8_STATUS    0x135a
#define    RTL8370_PORT8_STATUS_EN_1000_LPI_OFFSET    11
#define    RTL8370_PORT8_STATUS_EN_1000_LPI_MASK    0x800
#define    RTL8370_PORT8_STATUS_EN_100_LPI_OFFSET    10
#define    RTL8370_PORT8_STATUS_EN_100_LPI_MASK    0x400
#define    RTL8370_PORT8_STATUS_NWAY_FAULT_OFFSET    9
#define    RTL8370_PORT8_STATUS_NWAY_FAULT_MASK    0x200
#define    RTL8370_PORT8_STATUS_LINK_ON_MASTER_OFFSET    8
#define    RTL8370_PORT8_STATUS_LINK_ON_MASTER_MASK    0x100
#define    RTL8370_PORT8_STATUS_NWAY_CAP_OFFSET    7
#define    RTL8370_PORT8_STATUS_NWAY_CAP_MASK    0x80
#define    RTL8370_PORT8_STATUS_TX_FLOWCTRL_CAP_OFFSET    6
#define    RTL8370_PORT8_STATUS_TX_FLOWCTRL_CAP_MASK    0x40
#define    RTL8370_PORT8_STATUS_RX_FLOWCTRL_CAP_OFFSET    5
#define    RTL8370_PORT8_STATUS_RX_FLOWCTRL_CAP_MASK    0x20
#define    RTL8370_PORT8_STATUS_LINK_STATE_OFFSET    4
#define    RTL8370_PORT8_STATUS_LINK_STATE_MASK    0x10
#define    RTL8370_PORT8_STATUS_FULL_DUPLUX_CAP_OFFSET    2
#define    RTL8370_PORT8_STATUS_FULL_DUPLUX_CAP_MASK    0x4
#define    RTL8370_PORT8_STATUS_LINK_SPEED_OFFSET    0
#define    RTL8370_PORT8_STATUS_LINK_SPEED_MASK    0x3

#define    RTL8370_REG_PORT9_STATUS    0x135b
#define    RTL8370_PORT9_STATUS_EN_1000_LPI_OFFSET    11
#define    RTL8370_PORT9_STATUS_EN_1000_LPI_MASK    0x800
#define    RTL8370_PORT9_STATUS_EN_100_LPI_OFFSET    10
#define    RTL8370_PORT9_STATUS_EN_100_LPI_MASK    0x400
#define    RTL8370_PORT9_STATUS_NWAY_FAULT_OFFSET    9
#define    RTL8370_PORT9_STATUS_NWAY_FAULT_MASK    0x200
#define    RTL8370_PORT9_STATUS_LINK_ON_MASTER_OFFSET    8
#define    RTL8370_PORT9_STATUS_LINK_ON_MASTER_MASK    0x100
#define    RTL8370_PORT9_STATUS_NWAY_CAP_OFFSET    7
#define    RTL8370_PORT9_STATUS_NWAY_CAP_MASK    0x80
#define    RTL8370_PORT9_STATUS_TX_FLOWCTRL_CAP_OFFSET    6
#define    RTL8370_PORT9_STATUS_TX_FLOWCTRL_CAP_MASK    0x40
#define    RTL8370_PORT9_STATUS_RX_FLOWCTRL_CAP_OFFSET    5
#define    RTL8370_PORT9_STATUS_RX_FLOWCTRL_CAP_MASK    0x20
#define    RTL8370_PORT9_STATUS_LINK_STATE_OFFSET    4
#define    RTL8370_PORT9_STATUS_LINK_STATE_MASK    0x10
#define    RTL8370_PORT9_STATUS_FULL_DUPLUX_CAP_OFFSET    2
#define    RTL8370_PORT9_STATUS_FULL_DUPLUX_CAP_MASK    0x4
#define    RTL8370_PORT9_STATUS_LINK_SPEED_OFFSET    0
#define    RTL8370_PORT9_STATUS_LINK_SPEED_MASK    0x3

#define    RTL8370_REG_PORT10_STATUS    0x135c
#define    RTL8370_PORT10_STATUS_EN_1000_LPI_OFFSET    11
#define    RTL8370_PORT10_STATUS_EN_1000_LPI_MASK    0x800
#define    RTL8370_PORT10_STATUS_EN_100_LPI_OFFSET    10
#define    RTL8370_PORT10_STATUS_EN_100_LPI_MASK    0x400
#define    RTL8370_PORT10_STATUS_NWAY_FAULT_OFFSET    9
#define    RTL8370_PORT10_STATUS_NWAY_FAULT_MASK    0x200
#define    RTL8370_PORT10_STATUS_LINK_ON_MASTER_OFFSET    8
#define    RTL8370_PORT10_STATUS_LINK_ON_MASTER_MASK    0x100
#define    RTL8370_PORT10_STATUS_NWAY_CAP_OFFSET    7
#define    RTL8370_PORT10_STATUS_NWAY_CAP_MASK    0x80
#define    RTL8370_PORT10_STATUS_TX_FLOWCTRL_CAP_OFFSET    6
#define    RTL8370_PORT10_STATUS_TX_FLOWCTRL_CAP_MASK    0x40
#define    RTL8370_PORT10_STATUS_RX_FLOWCTRL_CAP_OFFSET    5
#define    RTL8370_PORT10_STATUS_RX_FLOWCTRL_CAP_MASK    0x20
#define    RTL8370_PORT10_STATUS_LINK_STATE_OFFSET    4
#define    RTL8370_PORT10_STATUS_LINK_STATE_MASK    0x10
#define    RTL8370_PORT10_STATUS_FULL_DUPLUX_CAP_OFFSET    2
#define    RTL8370_PORT10_STATUS_FULL_DUPLUX_CAP_MASK    0x4
#define    RTL8370_PORT10_STATUS_LINK_SPEED_OFFSET    0
#define    RTL8370_PORT10_STATUS_LINK_SPEED_MASK    0x3

#define    RTL8370_REG_PORT11_STATUS    0x135d
#define    RTL8370_PORT11_STATUS_EN_1000_LPI_OFFSET    11
#define    RTL8370_PORT11_STATUS_EN_1000_LPI_MASK    0x800
#define    RTL8370_PORT11_STATUS_EN_100_LPI_OFFSET    10
#define    RTL8370_PORT11_STATUS_EN_100_LPI_MASK    0x400
#define    RTL8370_PORT11_STATUS_NWAY_FAULT_OFFSET    9
#define    RTL8370_PORT11_STATUS_NWAY_FAULT_MASK    0x200
#define    RTL8370_PORT11_STATUS_LINK_ON_MASTER_OFFSET    8
#define    RTL8370_PORT11_STATUS_LINK_ON_MASTER_MASK    0x100
#define    RTL8370_PORT11_STATUS_NWAY_CAP_OFFSET    7
#define    RTL8370_PORT11_STATUS_NWAY_CAP_MASK    0x80
#define    RTL8370_PORT11_STATUS_TX_FLOWCTRL_CAP_OFFSET    6
#define    RTL8370_PORT11_STATUS_TX_FLOWCTRL_CAP_MASK    0x40
#define    RTL8370_PORT11_STATUS_RX_FLOWCTRL_CAP_OFFSET    5
#define    RTL8370_PORT11_STATUS_RX_FLOWCTRL_CAP_MASK    0x20
#define    RTL8370_PORT11_STATUS_LINK_STATE_OFFSET    4
#define    RTL8370_PORT11_STATUS_LINK_STATE_MASK    0x10
#define    RTL8370_PORT11_STATUS_FULL_DUPLUX_CAP_OFFSET    2
#define    RTL8370_PORT11_STATUS_FULL_DUPLUX_CAP_MASK    0x4
#define    RTL8370_PORT11_STATUS_LINK_SPEED_OFFSET    0
#define    RTL8370_PORT11_STATUS_LINK_SPEED_MASK    0x3

#define    RTL8370_REG_PORT12_STATUS    0x135e
#define    RTL8370_PORT12_STATUS_EN_1000_LPI_OFFSET    11
#define    RTL8370_PORT12_STATUS_EN_1000_LPI_MASK    0x800
#define    RTL8370_PORT12_STATUS_EN_100_LPI_OFFSET    10
#define    RTL8370_PORT12_STATUS_EN_100_LPI_MASK    0x400
#define    RTL8370_PORT12_STATUS_NWAY_FAULT_OFFSET    9
#define    RTL8370_PORT12_STATUS_NWAY_FAULT_MASK    0x200
#define    RTL8370_PORT12_STATUS_LINK_ON_MASTER_OFFSET    8
#define    RTL8370_PORT12_STATUS_LINK_ON_MASTER_MASK    0x100
#define    RTL8370_PORT12_STATUS_NWAY_CAP_OFFSET    7
#define    RTL8370_PORT12_STATUS_NWAY_CAP_MASK    0x80
#define    RTL8370_PORT12_STATUS_TX_FLOWCTRL_CAP_OFFSET    6
#define    RTL8370_PORT12_STATUS_TX_FLOWCTRL_CAP_MASK    0x40
#define    RTL8370_PORT12_STATUS_RX_FLOWCTRL_CAP_OFFSET    5
#define    RTL8370_PORT12_STATUS_RX_FLOWCTRL_CAP_MASK    0x20
#define    RTL8370_PORT12_STATUS_LINK_STATE_OFFSET    4
#define    RTL8370_PORT12_STATUS_LINK_STATE_MASK    0x10
#define    RTL8370_PORT12_STATUS_FULL_DUPLUX_CAP_OFFSET    2
#define    RTL8370_PORT12_STATUS_FULL_DUPLUX_CAP_MASK    0x4
#define    RTL8370_PORT12_STATUS_LINK_SPEED_OFFSET    0
#define    RTL8370_PORT12_STATUS_LINK_SPEED_MASK    0x3

#define    RTL8370_REG_PORT13_STATUS    0x135f
#define    RTL8370_PORT13_STATUS_EN_1000_LPI_OFFSET    11
#define    RTL8370_PORT13_STATUS_EN_1000_LPI_MASK    0x800
#define    RTL8370_PORT13_STATUS_EN_100_LPI_OFFSET    10
#define    RTL8370_PORT13_STATUS_EN_100_LPI_MASK    0x400
#define    RTL8370_PORT13_STATUS_NWAY_FAULT_OFFSET    9
#define    RTL8370_PORT13_STATUS_NWAY_FAULT_MASK    0x200
#define    RTL8370_PORT13_STATUS_LINK_ON_MASTER_OFFSET    8
#define    RTL8370_PORT13_STATUS_LINK_ON_MASTER_MASK    0x100
#define    RTL8370_PORT13_STATUS_NWAY_CAP_OFFSET    7
#define    RTL8370_PORT13_STATUS_NWAY_CAP_MASK    0x80
#define    RTL8370_PORT13_STATUS_TX_FLOWCTRL_CAP_OFFSET    6
#define    RTL8370_PORT13_STATUS_TX_FLOWCTRL_CAP_MASK    0x40
#define    RTL8370_PORT13_STATUS_RX_FLOWCTRL_CAP_OFFSET    5
#define    RTL8370_PORT13_STATUS_RX_FLOWCTRL_CAP_MASK    0x20
#define    RTL8370_PORT13_STATUS_LINK_STATE_OFFSET    4
#define    RTL8370_PORT13_STATUS_LINK_STATE_MASK    0x10
#define    RTL8370_PORT13_STATUS_FULL_DUPLUX_CAP_OFFSET    2
#define    RTL8370_PORT13_STATUS_FULL_DUPLUX_CAP_MASK    0x4
#define    RTL8370_PORT13_STATUS_LINK_SPEED_OFFSET    0
#define    RTL8370_PORT13_STATUS_LINK_SPEED_MASK    0x3

#define    RTL8370_REG_PORT14_STATUS    0x1360
#define    RTL8370_PORT14_STATUS_EN_1000_LPI_OFFSET    11
#define    RTL8370_PORT14_STATUS_EN_1000_LPI_MASK    0x800
#define    RTL8370_PORT14_STATUS_EN_100_LPI_OFFSET    10
#define    RTL8370_PORT14_STATUS_EN_100_LPI_MASK    0x400
#define    RTL8370_PORT14_STATUS_NWAY_FAULT_OFFSET    9
#define    RTL8370_PORT14_STATUS_NWAY_FAULT_MASK    0x200
#define    RTL8370_PORT14_STATUS_LINK_ON_MASTER_OFFSET    8
#define    RTL8370_PORT14_STATUS_LINK_ON_MASTER_MASK    0x100
#define    RTL8370_PORT14_STATUS_NWAY_CAP_OFFSET    7
#define    RTL8370_PORT14_STATUS_NWAY_CAP_MASK    0x80
#define    RTL8370_PORT14_STATUS_TX_FLOWCTRL_CAP_OFFSET    6
#define    RTL8370_PORT14_STATUS_TX_FLOWCTRL_CAP_MASK    0x40
#define    RTL8370_PORT14_STATUS_RX_FLOWCTRL_CAP_OFFSET    5
#define    RTL8370_PORT14_STATUS_RX_FLOWCTRL_CAP_MASK    0x20
#define    RTL8370_PORT14_STATUS_LINK_STATE_OFFSET    4
#define    RTL8370_PORT14_STATUS_LINK_STATE_MASK    0x10
#define    RTL8370_PORT14_STATUS_FULL_DUPLUX_CAP_OFFSET    2
#define    RTL8370_PORT14_STATUS_FULL_DUPLUX_CAP_MASK    0x4
#define    RTL8370_PORT14_STATUS_LINK_SPEED_OFFSET    0
#define    RTL8370_PORT14_STATUS_LINK_SPEED_MASK    0x3

#define    RTL8370_REG_PORT15_STATUS    0x1361
#define    RTL8370_PORT15_STATUS_EN_1000_LPI_OFFSET    11
#define    RTL8370_PORT15_STATUS_EN_1000_LPI_MASK    0x800
#define    RTL8370_PORT15_STATUS_EN_100_LPI_OFFSET    10
#define    RTL8370_PORT15_STATUS_EN_100_LPI_MASK    0x400
#define    RTL8370_PORT15_STATUS_NWAY_FAULT_OFFSET    9
#define    RTL8370_PORT15_STATUS_NWAY_FAULT_MASK    0x200
#define    RTL8370_PORT15_STATUS_LINK_ON_MASTER_OFFSET    8
#define    RTL8370_PORT15_STATUS_LINK_ON_MASTER_MASK    0x100
#define    RTL8370_PORT15_STATUS_NWAY_CAP_OFFSET    7
#define    RTL8370_PORT15_STATUS_NWAY_CAP_MASK    0x80
#define    RTL8370_PORT15_STATUS_TX_FLOWCTRL_CAP_OFFSET    6
#define    RTL8370_PORT15_STATUS_TX_FLOWCTRL_CAP_MASK    0x40
#define    RTL8370_PORT15_STATUS_RX_FLOWCTRL_CAP_OFFSET    5
#define    RTL8370_PORT15_STATUS_RX_FLOWCTRL_CAP_MASK    0x20
#define    RTL8370_PORT15_STATUS_LINK_STATE_OFFSET    4
#define    RTL8370_PORT15_STATUS_LINK_STATE_MASK    0x10
#define    RTL8370_PORT15_STATUS_FULL_DUPLUX_CAP_OFFSET    2
#define    RTL8370_PORT15_STATUS_FULL_DUPLUX_CAP_MASK    0x4
#define    RTL8370_PORT15_STATUS_LINK_SPEED_OFFSET    0
#define    RTL8370_PORT15_STATUS_LINK_SPEED_MASK    0x3

#define    RTL8370_REG_UPS_CTRL0    0x1362
#define    RTL8370_P3_REF_SD_BIT0_OFFSET    15
#define    RTL8370_P3_REF_SD_BIT0_MASK    0x8000
#define    RTL8370_P2_REF_SD_OFFSET    13
#define    RTL8370_P2_REF_SD_MASK    0x6000
#define    RTL8370_P1_REF_SD_OFFSET    11
#define    RTL8370_P1_REF_SD_MASK    0x1800
#define    RTL8370_P0_REF_SD_OFFSET    9
#define    RTL8370_P0_REF_SD_MASK    0x600
#define    RTL8370_REF_LDO_OFFSET    6
#define    RTL8370_REF_LDO_MASK    0x1C0
#define    RTL8370_SLP_TIME_SEL_OFFSET    5
#define    RTL8370_SLP_TIME_SEL_MASK    0x20
#define    RTL8370_RST1V_TIEM_SEL_OFFSET    3
#define    RTL8370_RST1V_TIEM_SEL_MASK    0x18
#define    RTL8370_MST_MODE_OFFSET    2
#define    RTL8370_MST_MODE_MASK    0x4
#define    RTL8370_FRC_UPS_OFFSET    1
#define    RTL8370_FRC_UPS_MASK    0x2
#define    RTL8370_EN_UPS_OFFSET    0
#define    RTL8370_EN_UPS_MASK    0x1

#define    RTL8370_REG_UPS_CTRL1    0x1363
#define    RTL8370_SEL_TX10M_HCC_OFFSET    15
#define    RTL8370_SEL_TX10M_HCC_MASK    0x8000
#define    RTL8370_TESTSPD_OFFSET    14
#define    RTL8370_TESTSPD_MASK    0x4000
#define    RTL8370_REF_CHUPS_OFFSET    10
#define    RTL8370_REF_CHUPS_MASK    0x3C00
#define    RTL8370_EN_CHUPS_OFFSET    9
#define    RTL8370_EN_CHUPS_MASK    0x200
#define    RTL8370_P7_REF_SD_OFFSET    7
#define    RTL8370_P7_REF_SD_MASK    0x180
#define    RTL8370_P6_REF_SD_OFFSET    5
#define    RTL8370_P6_REF_SD_MASK    0x60
#define    RTL8370_P5_REF_SD_OFFSET    3
#define    RTL8370_P5_REF_SD_MASK    0x18
#define    RTL8370_P4_REF_SD_OFFSET    1
#define    RTL8370_P4_REF_SD_MASK    0x6
#define    RTL8370_P3_REF_SD_BIT1_OFFSET    0
#define    RTL8370_P3_REF_SD_BIT1_MASK    0x1

#define    RTL8370_REG_UPS_CTRL2    0x1364
#define    RTL8370_P1_TX11M_SEL_OFFSET    12
#define    RTL8370_P1_TX11M_SEL_MASK    0xF000
#define    RTL8370_P0_TX11M_SEL_OFFSET    8
#define    RTL8370_P0_TX11M_SEL_MASK    0xF00
#define    RTL8370_P1_TX10M_SEL_OFFSET    4
#define    RTL8370_P1_TX10M_SEL_MASK    0xF0
#define    RTL8370_P0_TX10M_SEL_OFFSET    0
#define    RTL8370_P0_TX10M_SEL_MASK    0xF

#define    RTL8370_REG_UPS_CTRL3    0x1365
#define    RTL8370_P1_TX13M_SEL_OFFSET    12
#define    RTL8370_P1_TX13M_SEL_MASK    0xF000
#define    RTL8370_P0_TX13M_SEL_OFFSET    8
#define    RTL8370_P0_TX13M_SEL_MASK    0xF00
#define    RTL8370_P1_TX12M_SEL_OFFSET    4
#define    RTL8370_P1_TX12M_SEL_MASK    0xF0
#define    RTL8370_P0_TX12M_SEL_OFFSET    0
#define    RTL8370_P0_TX12M_SEL_MASK    0xF

#define    RTL8370_REG_UPS_CTRL4    0x1366
#define    RTL8370_UPS_DBG_3_OFFSET    14
#define    RTL8370_UPS_DBG_3_MASK    0xC000
#define    RTL8370_UPS_DBG_2_OFFSET    13
#define    RTL8370_UPS_DBG_2_MASK    0x2000
#define    RTL8370_UPS_DBG_1_OFFSET    8
#define    RTL8370_UPS_DBG_1_MASK    0x1F00
#define    RTL8370_UPS_DBG_0_OFFSET    7
#define    RTL8370_UPS_DBG_0_MASK    0x80
#define    RTL8370_PROB_EN_OFFSET    6
#define    RTL8370_PROB_EN_MASK    0x40
#define    RTL8370_UPS_CTRL4_DUMMY_1_OFFSET    5
#define    RTL8370_UPS_CTRL4_DUMMY_1_MASK    0x20
#define    RTL8370_FRC_ENRING_OFFSET    4
#define    RTL8370_FRC_ENRING_MASK    0x10
#define    RTL8370_SEL_UPSCLK_OFFSET    2
#define    RTL8370_SEL_UPSCLK_MASK    0xC
#define    RTL8370_PLL_DOWN_OFFSET    1
#define    RTL8370_PLL_DOWN_MASK    0x2
#define    RTL8370_XTAL_DOWN_OFFSET    0
#define    RTL8370_XTAL_DOWN_MASK    0x1

#define    RTL8370_REG_UPS_CTRL5    0x1367
#define    RTL8370_FRC_CPU_ACPT_OFFSET    3
#define    RTL8370_FRC_CPU_ACPT_MASK    0x8
#define    RTL8370_UPS_CPU_ACPT_OFFSET    2
#define    RTL8370_UPS_CPU_ACPT_MASK    0x4
#define    RTL8370_UPS_DBG_4_OFFSET    0
#define    RTL8370_UPS_DBG_4_MASK    0x3

#define    RTL8370_REG_TRIGGER_CTRL0    0x1368
#define    RTL8370_TRIGGER_CTRL0_DUMMY_0_OFFSET    15
#define    RTL8370_TRIGGER_CTRL0_DUMMY_0_MASK    0x8000
#define    RTL8370_TRIG_TYPE_OFFSET    13
#define    RTL8370_TRIG_TYPE_MASK    0x6000
#define    RTL8370_TRIG_EN_OFFSET    12
#define    RTL8370_TRIG_EN_MASK    0x1000
#define    RTL8370_EMA_DBGGORAM_OFFSET    9
#define    RTL8370_EMA_DBGGORAM_MASK    0xE00
#define    RTL8370_PGEN_DBGGORAM_OFFSET    8
#define    RTL8370_PGEN_DBGGORAM_MASK    0x100
#define    RTL8370_RETN_DBGGORAM_OFFSET    7
#define    RTL8370_RETN_DBGGORAM_MASK    0x80
#define    RTL8370_CLK_DBGO_OFFSET    0
#define    RTL8370_CLK_DBGO_MASK    0x7F

#define    RTL8370_REG_TRIGGER_WORD0    0x1369

#define    RTL8370_REG_TRIGGER_WORD1    0x136a

#define    RTL8370_REG_TRIGGER_WORD2    0x136b

#define    RTL8370_REG_TRIGGER_WORD3    0x136c

#define    RTL8370_REG_TRIGGER_WORD4    0x136d

#define    RTL8370_REG_TRIGGER_WORD5    0x136e

#define    RTL8370_REG_TRIGGER_CTRL1    0x136f
#define    RTL8370_FRC_DUMP_OFFSET    6
#define    RTL8370_FRC_DUMP_MASK    0x40
#define    RTL8370_STOP_TRIGGER_OFFSET    5
#define    RTL8370_STOP_TRIGGER_MASK    0x20
#define    RTL8370_START_TRIGGER_OFFSET    4
#define    RTL8370_START_TRIGGER_MASK    0x10
#define    RTL8370_CMP_BZ_OFFSET    1
#define    RTL8370_CMP_BZ_MASK    0x2
#define    RTL8370_PATTERN_HIT_OFFSET    0
#define    RTL8370_PATTERN_HIT_MASK    0x1

#define    RTL8370_REG_EFUSE_CMD    0x1370
#define    RTL8370_EFUSE_COMMAND_EN_OFFSET    1
#define    RTL8370_EFUSE_COMMAND_EN_MASK    0x2
#define    RTL8370_EFUSE_WR_OFFSET    0
#define    RTL8370_EFUSE_WR_MASK    0x1

#define    RTL8370_REG_EFUSE_ADR    0x1371

#define    RTL8370_REG_EFUSE_WDAT    0x1372

#define    RTL8370_REG_EFUSE_RDAT    0x1373

#define    RTL8370_REG_I2C_CTRL    0x1374
#define    RTL8370_NO_ACK_LAT_OFFSET    1
#define    RTL8370_NO_ACK_LAT_MASK    0x2
#define    RTL8370_NO_ACK_CLRPS_OFFSET    0
#define    RTL8370_NO_ACK_CLRPS_MASK    0x1

#define    RTL8370_REG_DW8051_PRO_REG0    0x13a0

#define    RTL8370_REG_DW8051_PRO_REG1    0x13a1

#define    RTL8370_REG_DW8051_PRO_REG2    0x13a2

#define    RTL8370_REG_DW8051_PRO_REG3    0x13a3

#define    RTL8370_REG_DW8051_PRO_REG4    0x13a4

#define    RTL8370_REG_DW8051_PRO_REG5    0x13a5

#define    RTL8370_REG_DW8051_PRO_REG6    0x13a6

#define    RTL8370_REG_DW8051_PRO_REG7    0x13a7

#define    RTL8370_REG_RTL_NO    0x13c0

#define    RTL8370_REG_RTL_VER    0x13c1
#define    RTL8370_RTL_VER_OFFSET    0
#define    RTL8370_RTL_VER_MASK    0xF

#define    RTL8370_REG_MAGIC_ID    0x13c2

/* (16'h1400) mtrpool_reg */

#define    RTL8370_REG_METER0_RATE_CTRL0    0x1400

#define    RTL8370_REG_METER0_RATE_CTRL1    0x1401
#define    RTL8370_METER0_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER0_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER1_RATE_CTRL0    0x1402

#define    RTL8370_REG_METER1_RATE_CTRL1    0x1403
#define    RTL8370_METER1_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER1_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER2_RATE_CTRL0    0x1404

#define    RTL8370_REG_METER2_RATE_CTRL1    0x1405
#define    RTL8370_METER2_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER2_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER3_RATE_CTRL0    0x1406

#define    RTL8370_REG_METER3_RATE_CTRL1    0x1407
#define    RTL8370_METER3_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER3_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER4_RATE_CTRL0    0x1408

#define    RTL8370_REG_METER4_RATE_CTRL1    0x1409
#define    RTL8370_METER4_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER4_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER5_RATE_CTRL0    0x140a

#define    RTL8370_REG_METER5_RATE_CTRL1    0x140b
#define    RTL8370_METER5_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER5_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER6_RATE_CTRL0    0x140c

#define    RTL8370_REG_METER6_RATE_CTRL1    0x140d
#define    RTL8370_METER6_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER6_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER7_RATE_CTRL0    0x140e

#define    RTL8370_REG_METER7_RATE_CTRL1    0x140f
#define    RTL8370_METER7_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER7_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER8_RATE_CTRL0    0x1410

#define    RTL8370_REG_METER8_RATE_CTRL1    0x1411
#define    RTL8370_METER8_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER8_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER9_RATE_CTRL0    0x1412

#define    RTL8370_REG_METER9_RATE_CTRL1    0x1413
#define    RTL8370_METER9_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER9_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER10_RATE_CTRL0    0x1414

#define    RTL8370_REG_METER10_RATE_CTRL1    0x1415
#define    RTL8370_METER10_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER10_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER11_RATE_CTRL0    0x1416

#define    RTL8370_REG_METER11_RATE_CTRL1    0x1417
#define    RTL8370_METER11_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER11_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER12_RATE_CTRL0    0x1418

#define    RTL8370_REG_METER12_RATE_CTRL1    0x1419
#define    RTL8370_METER12_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER12_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER13_RATE_CTRL0    0x141a

#define    RTL8370_REG_METER13_RATE_CTRL1    0x141b
#define    RTL8370_METER13_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER13_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER14_RATE_CTRL0    0x141c

#define    RTL8370_REG_METER14_RATE_CTRL1    0x141d
#define    RTL8370_METER14_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER14_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER15_RATE_CTRL0    0x141e

#define    RTL8370_REG_METER15_RATE_CTRL1    0x141f
#define    RTL8370_METER15_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER15_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER16_RATE_CTRL0    0x1420

#define    RTL8370_REG_METER16_RATE_CTRL1    0x1421
#define    RTL8370_METER16_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER16_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER17_RATE_CTRL0    0x1422

#define    RTL8370_REG_METER17_RATE_CTRL1    0x1423
#define    RTL8370_METER17_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER17_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER18_RATE_CTRL0    0x1424

#define    RTL8370_REG_METER18_RATE_CTRL1    0x1425
#define    RTL8370_METER18_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER18_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER19_RATE_CTRL0    0x1426

#define    RTL8370_REG_METER19_RATE_CTRL1    0x1427
#define    RTL8370_METER19_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER19_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER20_RATE_CTRL0    0x1428

#define    RTL8370_REG_METER20_RATE_CTRL1    0x1429
#define    RTL8370_METER20_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER20_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER21_RATE_CTRL0    0x142a

#define    RTL8370_REG_METER21_RATE_CTRL1    0x142b
#define    RTL8370_METER21_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER21_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER22_RATE_CTRL0    0x142c

#define    RTL8370_REG_METER22_RATE_CTRL1    0x142d
#define    RTL8370_METER22_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER22_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER23_RATE_CTRL0    0x142e

#define    RTL8370_REG_METER23_RATE_CTRL1    0x142f
#define    RTL8370_METER23_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER23_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER24_RATE_CTRL0    0x1430

#define    RTL8370_REG_METER24_RATE_CTRL1    0x1431
#define    RTL8370_METER24_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER24_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER25_RATE_CTRL0    0x1432

#define    RTL8370_REG_METER25_RATE_CTRL1    0x1433
#define    RTL8370_METER25_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER25_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER26_RATE_CTRL0    0x1434

#define    RTL8370_REG_METER26_RATE_CTRL1    0x1435
#define    RTL8370_METER26_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER26_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER27_RATE_CTRL0    0x1436

#define    RTL8370_REG_METER27_RATE_CTRL1    0x1437
#define    RTL8370_METER27_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER27_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER28_RATE_CTRL0    0x1438

#define    RTL8370_REG_METER28_RATE_CTRL1    0x1439
#define    RTL8370_METER28_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER28_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER29_RATE_CTRL0    0x143a

#define    RTL8370_REG_METER29_RATE_CTRL1    0x143b
#define    RTL8370_METER29_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER29_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER30_RATE_CTRL0    0x143c

#define    RTL8370_REG_METER30_RATE_CTRL1    0x143d
#define    RTL8370_METER30_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER30_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER31_RATE_CTRL0    0x143e

#define    RTL8370_REG_METER31_RATE_CTRL1    0x143f
#define    RTL8370_METER31_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER31_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER32_RATE_CTRL0    0x1440

#define    RTL8370_REG_METER32_RATE_CTRL1    0x1441
#define    RTL8370_METER32_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER32_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER33_RATE_CTRL0    0x1442

#define    RTL8370_REG_METER33_RATE_CTRL1    0x1443
#define    RTL8370_METER33_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER33_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER34_RATE_CTRL0    0x1444

#define    RTL8370_REG_METER34_RATE_CTRL1    0x1445
#define    RTL8370_METER34_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER34_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER35_RATE_CTRL0    0x1446

#define    RTL8370_REG_METER35_RATE_CTRL1    0x1447
#define    RTL8370_METER35_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER35_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER36_RATE_CTRL0    0x1448

#define    RTL8370_REG_METER36_RATE_CTRL1    0x1449
#define    RTL8370_METER36_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER36_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER37_RATE_CTRL0    0x144a

#define    RTL8370_REG_METER37_RATE_CTRL1    0x144b
#define    RTL8370_METER37_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER37_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER38_RATE_CTRL0    0x144c

#define    RTL8370_REG_METER38_RATE_CTRL1    0x144d
#define    RTL8370_METER38_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER38_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER39_RATE_CTRL0    0x144e

#define    RTL8370_REG_METER39_RATE_CTRL1    0x144f
#define    RTL8370_METER39_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER39_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER40_RATE_CTRL0    0x1450

#define    RTL8370_REG_METER40_RATE_CTRL1    0x1451
#define    RTL8370_METER40_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER40_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER41_RATE_CTRL0    0x1452

#define    RTL8370_REG_METER41_RATE_CTRL1    0x1453
#define    RTL8370_METER41_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER41_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER42_RATE_CTRL0    0x1454

#define    RTL8370_REG_METER42_RATE_CTRL1    0x1455
#define    RTL8370_METER42_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER42_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER43_RATE_CTRL0    0x1456

#define    RTL8370_REG_METER43_RATE_CTRL1    0x1457
#define    RTL8370_METER43_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER43_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER44_RATE_CTRL0    0x1458

#define    RTL8370_REG_METER44_RATE_CTRL1    0x1459
#define    RTL8370_METER44_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER44_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER45_RATE_CTRL0    0x145a

#define    RTL8370_REG_METER45_RATE_CTRL1    0x145b
#define    RTL8370_METER45_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER45_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER46_RATE_CTRL0    0x145c

#define    RTL8370_REG_METER46_RATE_CTRL1    0x145d
#define    RTL8370_METER46_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER46_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER47_RATE_CTRL0    0x145e

#define    RTL8370_REG_METER47_RATE_CTRL1    0x145f
#define    RTL8370_METER47_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER47_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER48_RATE_CTRL0    0x1460

#define    RTL8370_REG_METER48_RATE_CTRL1    0x1461
#define    RTL8370_METER48_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER48_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER49_RATE_CTRL0    0x1462

#define    RTL8370_REG_METER49_RATE_CTRL1    0x1463
#define    RTL8370_METER49_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER49_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER50_RATE_CTRL0    0x1464

#define    RTL8370_REG_METER50_RATE_CTRL1    0x1465
#define    RTL8370_METER50_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER50_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER51_RATE_CTRL0    0x1466

#define    RTL8370_REG_METER51_RATE_CTRL1    0x1467
#define    RTL8370_METER51_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER51_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER52_RATE_CTRL0    0x1468

#define    RTL8370_REG_METER52_RATE_CTRL1    0x1469
#define    RTL8370_METER52_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER52_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER53_RATE_CTRL0    0x146a

#define    RTL8370_REG_METER53_RATE_CTRL1    0x146b
#define    RTL8370_METER53_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER53_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER54_RATE_CTRL0    0x146c

#define    RTL8370_REG_METER54_RATE_CTRL1    0x146d
#define    RTL8370_METER54_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER54_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER55_RATE_CTRL0    0x146e

#define    RTL8370_REG_METER55_RATE_CTRL1    0x146f
#define    RTL8370_METER55_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER55_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER56_RATE_CTRL0    0x1470

#define    RTL8370_REG_METER56_RATE_CTRL1    0x1471
#define    RTL8370_METER56_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER56_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER57_RATE_CTRL0    0x1472

#define    RTL8370_REG_METER57_RATE_CTRL1    0x1473
#define    RTL8370_METER57_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER57_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER58_RATE_CTRL0    0x1474

#define    RTL8370_REG_METER58_RATE_CTRL1    0x1475
#define    RTL8370_METER58_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER58_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER59_RATE_CTRL0    0x1476

#define    RTL8370_REG_METER59_RATE_CTRL1    0x1477
#define    RTL8370_METER59_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER59_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER60_RATE_CTRL0    0x1478

#define    RTL8370_REG_METER60_RATE_CTRL1    0x1479
#define    RTL8370_METER60_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER60_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER61_RATE_CTRL0    0x147a

#define    RTL8370_REG_METER61_RATE_CTRL1    0x147b
#define    RTL8370_METER61_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER61_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER62_RATE_CTRL0    0x147c

#define    RTL8370_REG_METER62_RATE_CTRL1    0x147d
#define    RTL8370_METER62_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER62_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER63_RATE_CTRL0    0x147e

#define    RTL8370_REG_METER63_RATE_CTRL1    0x147f
#define    RTL8370_METER63_RATE_CTRL1_OFFSET    0
#define    RTL8370_METER63_RATE_CTRL1_MASK    0x1

#define    RTL8370_REG_METER0_BUCKET_SIZE    0x1600

#define    RTL8370_REG_METER1_BUCKET_SIZE    0x1601

#define    RTL8370_REG_METER2_BUCKET_SIZE    0x1602

#define    RTL8370_REG_METER3_BUCKET_SIZE    0x1603

#define    RTL8370_REG_METER4_BUCKET_SIZE    0x1604

#define    RTL8370_REG_METER5_BUCKET_SIZE    0x1605

#define    RTL8370_REG_METER6_BUCKET_SIZE    0x1606

#define    RTL8370_REG_METER7_BUCKET_SIZE    0x1607

#define    RTL8370_REG_METER8_BUCKET_SIZE    0x1608

#define    RTL8370_REG_METER9_BUCKET_SIZE    0x1609

#define    RTL8370_REG_METER10_BUCKET_SIZE    0x160a

#define    RTL8370_REG_METER11_BUCKET_SIZE    0x160b

#define    RTL8370_REG_METER12_BUCKET_SIZE    0x160c

#define    RTL8370_REG_METER13_BUCKET_SIZE    0x160d

#define    RTL8370_REG_METER14_BUCKET_SIZE    0x160e

#define    RTL8370_REG_METER15_BUCKET_SIZE    0x160f

#define    RTL8370_REG_METER16_BUCKET_SIZE    0x1610

#define    RTL8370_REG_METER17_BUCKET_SIZE    0x1611

#define    RTL8370_REG_METER18_BUCKET_SIZE    0x1612

#define    RTL8370_REG_METER19_BUCKET_SIZE    0x1613

#define    RTL8370_REG_METER20_BUCKET_SIZE    0x1614

#define    RTL8370_REG_METER21_BUCKET_SIZE    0x1615

#define    RTL8370_REG_METER22_BUCKET_SIZE    0x1616

#define    RTL8370_REG_METER23_BUCKET_SIZE    0x1617

#define    RTL8370_REG_METER24_BUCKET_SIZE    0x1618

#define    RTL8370_REG_METER25_BUCKET_SIZE    0x1619

#define    RTL8370_REG_METER26_BUCKET_SIZE    0x161a

#define    RTL8370_REG_METER27_BUCKET_SIZE    0x161b

#define    RTL8370_REG_METER28_BUCKET_SIZE    0x161c

#define    RTL8370_REG_METER29_BUCKET_SIZE    0x161d

#define    RTL8370_REG_METER30_BUCKET_SIZE    0x161e

#define    RTL8370_REG_METER31_BUCKET_SIZE    0x161f

#define    RTL8370_REG_METER32_BUCKET_SIZE    0x1620

#define    RTL8370_REG_METER33_BUCKET_SIZE    0x1621

#define    RTL8370_REG_METER34_BUCKET_SIZE    0x1622

#define    RTL8370_REG_METER35_BUCKET_SIZE    0x1623

#define    RTL8370_REG_METER36_BUCKET_SIZE    0x1624

#define    RTL8370_REG_METER37_BUCKET_SIZE    0x1625

#define    RTL8370_REG_METER38_BUCKET_SIZE    0x1626

#define    RTL8370_REG_METER39_BUCKET_SIZE    0x1627

#define    RTL8370_REG_METER40_BUCKET_SIZE    0x1628

#define    RTL8370_REG_METER41_BUCKET_SIZE    0x1629

#define    RTL8370_REG_METER42_BUCKET_SIZE    0x162a

#define    RTL8370_REG_METER43_BUCKET_SIZE    0x162b

#define    RTL8370_REG_METER44_BUCKET_SIZE    0x162c

#define    RTL8370_REG_METER45_BUCKET_SIZE    0x162d

#define    RTL8370_REG_METER46_BUCKET_SIZE    0x162e

#define    RTL8370_REG_METER47_BUCKET_SIZE    0x162f

#define    RTL8370_REG_METER48_BUCKET_SIZE    0x1630

#define    RTL8370_REG_METER49_BUCKET_SIZE    0x1631

#define    RTL8370_REG_METER50_BUCKET_SIZE    0x1632

#define    RTL8370_REG_METER51_BUCKET_SIZE    0x1633

#define    RTL8370_REG_METER52_BUCKET_SIZE    0x1634

#define    RTL8370_REG_METER53_BUCKET_SIZE    0x1635

#define    RTL8370_REG_METER54_BUCKET_SIZE    0x1636

#define    RTL8370_REG_METER55_BUCKET_SIZE    0x1637

#define    RTL8370_REG_METER56_BUCKET_SIZE    0x1638

#define    RTL8370_REG_METER57_BUCKET_SIZE    0x1639

#define    RTL8370_REG_METER58_BUCKET_SIZE    0x163a

#define    RTL8370_REG_METER59_BUCKET_SIZE    0x163b

#define    RTL8370_REG_METER60_BUCKET_SIZE    0x163c

#define    RTL8370_REG_METER61_BUCKET_SIZE    0x163d

#define    RTL8370_REG_METER62_BUCKET_SIZE    0x163e

#define    RTL8370_REG_METER63_BUCKET_SIZE    0x163f

#define    RTL8370_REG_METER_CTRL0    0x1700
#define    RTL8370_METER_OP_OFFSET    8
#define    RTL8370_METER_OP_MASK    0x100
#define    RTL8370_METER_TICK_OFFSET    0
#define    RTL8370_METER_TICK_MASK    0xFF

#define    RTL8370_REG_METER_CTRL1    0x1701
#define    RTL8370_METER_CTRL1_OFFSET    0
#define    RTL8370_METER_CTRL1_MASK    0xFF

#define    RTL8370_REG_METER_OVERRATE_INDICATOR0    0x1702
#define    RTL8370_METER15_EXCEED_OFFSET    15
#define    RTL8370_METER15_EXCEED_MASK    0x8000
#define    RTL8370_METER14_EXCEED_OFFSET    14
#define    RTL8370_METER14_EXCEED_MASK    0x4000
#define    RTL8370_METER13_EXCEED_OFFSET    13
#define    RTL8370_METER13_EXCEED_MASK    0x2000
#define    RTL8370_METER12_EXCEED_OFFSET    12
#define    RTL8370_METER12_EXCEED_MASK    0x1000
#define    RTL8370_METER11_EXCEED_OFFSET    11
#define    RTL8370_METER11_EXCEED_MASK    0x800
#define    RTL8370_METER10_EXCEED_OFFSET    10
#define    RTL8370_METER10_EXCEED_MASK    0x400
#define    RTL8370_METER9_EXCEED_OFFSET    9
#define    RTL8370_METER9_EXCEED_MASK    0x200
#define    RTL8370_METER8_EXCEED_OFFSET    8
#define    RTL8370_METER8_EXCEED_MASK    0x100
#define    RTL8370_METER7_EXCEED_OFFSET    7
#define    RTL8370_METER7_EXCEED_MASK    0x80
#define    RTL8370_METER6_EXCEED_OFFSET    6
#define    RTL8370_METER6_EXCEED_MASK    0x40
#define    RTL8370_METER5_EXCEED_OFFSET    5
#define    RTL8370_METER5_EXCEED_MASK    0x20
#define    RTL8370_METER4_EXCEED_OFFSET    4
#define    RTL8370_METER4_EXCEED_MASK    0x10
#define    RTL8370_METER3_EXCEED_OFFSET    3
#define    RTL8370_METER3_EXCEED_MASK    0x8
#define    RTL8370_METER2_EXCEED_OFFSET    2
#define    RTL8370_METER2_EXCEED_MASK    0x4
#define    RTL8370_METER1_EXCEED_OFFSET    1
#define    RTL8370_METER1_EXCEED_MASK    0x2
#define    RTL8370_METER0_EXCEED_OFFSET    0
#define    RTL8370_METER0_EXCEED_MASK    0x1

#define    RTL8370_REG_METER_OVERRATE_INDICATOR1    0x1703
#define    RTL8370_METER31_EXCEED_OFFSET    15
#define    RTL8370_METER31_EXCEED_MASK    0x8000
#define    RTL8370_METER30_EXCEED_OFFSET    14
#define    RTL8370_METER30_EXCEED_MASK    0x4000
#define    RTL8370_METER29_EXCEED_OFFSET    13
#define    RTL8370_METER29_EXCEED_MASK    0x2000
#define    RTL8370_METER28_EXCEED_OFFSET    12
#define    RTL8370_METER28_EXCEED_MASK    0x1000
#define    RTL8370_METER27_EXCEED_OFFSET    11
#define    RTL8370_METER27_EXCEED_MASK    0x800
#define    RTL8370_METER26_EXCEED_OFFSET    10
#define    RTL8370_METER26_EXCEED_MASK    0x400
#define    RTL8370_METER25_EXCEED_OFFSET    9
#define    RTL8370_METER25_EXCEED_MASK    0x200
#define    RTL8370_METER24_EXCEED_OFFSET    8
#define    RTL8370_METER24_EXCEED_MASK    0x100
#define    RTL8370_METER23_EXCEED_OFFSET    7
#define    RTL8370_METER23_EXCEED_MASK    0x80
#define    RTL8370_METER22_EXCEED_OFFSET    6
#define    RTL8370_METER22_EXCEED_MASK    0x40
#define    RTL8370_METER21_EXCEED_OFFSET    5
#define    RTL8370_METER21_EXCEED_MASK    0x20
#define    RTL8370_METER20_EXCEED_OFFSET    4
#define    RTL8370_METER20_EXCEED_MASK    0x10
#define    RTL8370_METER19_EXCEED_OFFSET    3
#define    RTL8370_METER19_EXCEED_MASK    0x8
#define    RTL8370_METER18_EXCEED_OFFSET    2
#define    RTL8370_METER18_EXCEED_MASK    0x4
#define    RTL8370_METER17_EXCEED_OFFSET    1
#define    RTL8370_METER17_EXCEED_MASK    0x2
#define    RTL8370_METER16_EXCEED_OFFSET    0
#define    RTL8370_METER16_EXCEED_MASK    0x1

#define    RTL8370_REG_METER_OVERRATE_INDICATOR2    0x1704
#define    RTL8370_METER47_EXCEED_OFFSET    15
#define    RTL8370_METER47_EXCEED_MASK    0x8000
#define    RTL8370_METER46_EXCEED_OFFSET    14
#define    RTL8370_METER46_EXCEED_MASK    0x4000
#define    RTL8370_METER45_EXCEED_OFFSET    13
#define    RTL8370_METER45_EXCEED_MASK    0x2000
#define    RTL8370_METER44_EXCEED_OFFSET    12
#define    RTL8370_METER44_EXCEED_MASK    0x1000
#define    RTL8370_METER43_EXCEED_OFFSET    11
#define    RTL8370_METER43_EXCEED_MASK    0x800
#define    RTL8370_METER42_EXCEED_OFFSET    10
#define    RTL8370_METER42_EXCEED_MASK    0x400
#define    RTL8370_METER41_EXCEED_OFFSET    9
#define    RTL8370_METER41_EXCEED_MASK    0x200
#define    RTL8370_METER40_EXCEED_OFFSET    8
#define    RTL8370_METER40_EXCEED_MASK    0x100
#define    RTL8370_METER39_EXCEED_OFFSET    7
#define    RTL8370_METER39_EXCEED_MASK    0x80
#define    RTL8370_METER38_EXCEED_OFFSET    6
#define    RTL8370_METER38_EXCEED_MASK    0x40
#define    RTL8370_METER37_EXCEED_OFFSET    5
#define    RTL8370_METER37_EXCEED_MASK    0x20
#define    RTL8370_METER36_EXCEED_OFFSET    4
#define    RTL8370_METER36_EXCEED_MASK    0x10
#define    RTL8370_METER35_EXCEED_OFFSET    3
#define    RTL8370_METER35_EXCEED_MASK    0x8
#define    RTL8370_METER34_EXCEED_OFFSET    2
#define    RTL8370_METER34_EXCEED_MASK    0x4
#define    RTL8370_METER33_EXCEED_OFFSET    1
#define    RTL8370_METER33_EXCEED_MASK    0x2
#define    RTL8370_METER32_EXCEED_OFFSET    0
#define    RTL8370_METER32_EXCEED_MASK    0x1

#define    RTL8370_REG_METER_OVERRATE_INDICATOR3    0x1705
#define    RTL8370_METER63_EXCEED_OFFSET    15
#define    RTL8370_METER63_EXCEED_MASK    0x8000
#define    RTL8370_METER62_EXCEED_OFFSET    14
#define    RTL8370_METER62_EXCEED_MASK    0x4000
#define    RTL8370_METER61_EXCEED_OFFSET    13
#define    RTL8370_METER61_EXCEED_MASK    0x2000
#define    RTL8370_METER60_EXCEED_OFFSET    12
#define    RTL8370_METER60_EXCEED_MASK    0x1000
#define    RTL8370_METER59_EXCEED_OFFSET    11
#define    RTL8370_METER59_EXCEED_MASK    0x800
#define    RTL8370_METER58_EXCEED_OFFSET    10
#define    RTL8370_METER58_EXCEED_MASK    0x400
#define    RTL8370_METER57_EXCEED_OFFSET    9
#define    RTL8370_METER57_EXCEED_MASK    0x200
#define    RTL8370_METER56_EXCEED_OFFSET    8
#define    RTL8370_METER56_EXCEED_MASK    0x100
#define    RTL8370_METER55_EXCEED_OFFSET    7
#define    RTL8370_METER55_EXCEED_MASK    0x80
#define    RTL8370_METER54_EXCEED_OFFSET    6
#define    RTL8370_METER54_EXCEED_MASK    0x40
#define    RTL8370_METER53_EXCEED_OFFSET    5
#define    RTL8370_METER53_EXCEED_MASK    0x20
#define    RTL8370_METER52_EXCEED_OFFSET    4
#define    RTL8370_METER52_EXCEED_MASK    0x10
#define    RTL8370_METER51_EXCEED_OFFSET    3
#define    RTL8370_METER51_EXCEED_MASK    0x8
#define    RTL8370_METER50_EXCEED_OFFSET    2
#define    RTL8370_METER50_EXCEED_MASK    0x4
#define    RTL8370_METER49_EXCEED_OFFSET    1
#define    RTL8370_METER49_EXCEED_MASK    0x2
#define    RTL8370_METER48_EXCEED_OFFSET    0
#define    RTL8370_METER48_EXCEED_MASK    0x1

#define    RTL8370_REG_METER_IFG_CTRL0    0x1712
#define    RTL8370_METER15_IFG_OFFSET    15
#define    RTL8370_METER15_IFG_MASK    0x8000
#define    RTL8370_METER14_IFG_OFFSET    14
#define    RTL8370_METER14_IFG_MASK    0x4000
#define    RTL8370_METER13_IFG_OFFSET    13
#define    RTL8370_METER13_IFG_MASK    0x2000
#define    RTL8370_METER12_IFG_OFFSET    12
#define    RTL8370_METER12_IFG_MASK    0x1000
#define    RTL8370_METER11_IFG_OFFSET    11
#define    RTL8370_METER11_IFG_MASK    0x800
#define    RTL8370_METER10_IFG_OFFSET    10
#define    RTL8370_METER10_IFG_MASK    0x400
#define    RTL8370_METER9_IFG_OFFSET    9
#define    RTL8370_METER9_IFG_MASK    0x200
#define    RTL8370_METER8_IFG_OFFSET    8
#define    RTL8370_METER8_IFG_MASK    0x100
#define    RTL8370_METER7_IFG_OFFSET    7
#define    RTL8370_METER7_IFG_MASK    0x80
#define    RTL8370_METER6_IFG_OFFSET    6
#define    RTL8370_METER6_IFG_MASK    0x40
#define    RTL8370_METER5_IFG_OFFSET    5
#define    RTL8370_METER5_IFG_MASK    0x20
#define    RTL8370_METER4_IFG_OFFSET    4
#define    RTL8370_METER4_IFG_MASK    0x10
#define    RTL8370_METER3_IFG_OFFSET    3
#define    RTL8370_METER3_IFG_MASK    0x8
#define    RTL8370_METER2_IFG_OFFSET    2
#define    RTL8370_METER2_IFG_MASK    0x4
#define    RTL8370_METER1_IFG_OFFSET    1
#define    RTL8370_METER1_IFG_MASK    0x2
#define    RTL8370_METER0_IFG_OFFSET    0
#define    RTL8370_METER0_IFG_MASK    0x1

#define    RTL8370_REG_METER_IFG_CTRL1    0x1713
#define    RTL8370_METER31_IFG_OFFSET    15
#define    RTL8370_METER31_IFG_MASK    0x8000
#define    RTL8370_METER30_IFG_OFFSET    14
#define    RTL8370_METER30_IFG_MASK    0x4000
#define    RTL8370_METER29_IFG_OFFSET    13
#define    RTL8370_METER29_IFG_MASK    0x2000
#define    RTL8370_METER28_IFG_OFFSET    12
#define    RTL8370_METER28_IFG_MASK    0x1000
#define    RTL8370_METER27_IFG_OFFSET    11
#define    RTL8370_METER27_IFG_MASK    0x800
#define    RTL8370_METER26_IFG_OFFSET    10
#define    RTL8370_METER26_IFG_MASK    0x400
#define    RTL8370_METER25_IFG_OFFSET    9
#define    RTL8370_METER25_IFG_MASK    0x200
#define    RTL8370_METER24_IFG_OFFSET    8
#define    RTL8370_METER24_IFG_MASK    0x100
#define    RTL8370_METER23_IFG_OFFSET    7
#define    RTL8370_METER23_IFG_MASK    0x80
#define    RTL8370_METER22_IFG_OFFSET    6
#define    RTL8370_METER22_IFG_MASK    0x40
#define    RTL8370_METER21_IFG_OFFSET    5
#define    RTL8370_METER21_IFG_MASK    0x20
#define    RTL8370_METER20_IFG_OFFSET    4
#define    RTL8370_METER20_IFG_MASK    0x10
#define    RTL8370_METER19_IFG_OFFSET    3
#define    RTL8370_METER19_IFG_MASK    0x8
#define    RTL8370_METER18_IFG_OFFSET    2
#define    RTL8370_METER18_IFG_MASK    0x4
#define    RTL8370_METER17_IFG_OFFSET    1
#define    RTL8370_METER17_IFG_MASK    0x2
#define    RTL8370_METER16_IFG_OFFSET    0
#define    RTL8370_METER16_IFG_MASK    0x1

#define    RTL8370_REG_METER_IFG_CTRL2    0x1714
#define    RTL8370_METER47_IFG_OFFSET    15
#define    RTL8370_METER47_IFG_MASK    0x8000
#define    RTL8370_METER46_IFG_OFFSET    14
#define    RTL8370_METER46_IFG_MASK    0x4000
#define    RTL8370_METER45_IFG_OFFSET    13
#define    RTL8370_METER45_IFG_MASK    0x2000
#define    RTL8370_METER44_IFG_OFFSET    12
#define    RTL8370_METER44_IFG_MASK    0x1000
#define    RTL8370_METER43_IFG_OFFSET    11
#define    RTL8370_METER43_IFG_MASK    0x800
#define    RTL8370_METER42_IFG_OFFSET    10
#define    RTL8370_METER42_IFG_MASK    0x400
#define    RTL8370_METER41_IFG_OFFSET    9
#define    RTL8370_METER41_IFG_MASK    0x200
#define    RTL8370_METER40_IFG_OFFSET    8
#define    RTL8370_METER40_IFG_MASK    0x100
#define    RTL8370_METER39_IFG_OFFSET    7
#define    RTL8370_METER39_IFG_MASK    0x80
#define    RTL8370_METER38_IFG_OFFSET    6
#define    RTL8370_METER38_IFG_MASK    0x40
#define    RTL8370_METER37_IFG_OFFSET    5
#define    RTL8370_METER37_IFG_MASK    0x20
#define    RTL8370_METER36_IFG_OFFSET    4
#define    RTL8370_METER36_IFG_MASK    0x10
#define    RTL8370_METER35_IFG_OFFSET    3
#define    RTL8370_METER35_IFG_MASK    0x8
#define    RTL8370_METER34_IFG_OFFSET    2
#define    RTL8370_METER34_IFG_MASK    0x4
#define    RTL8370_METER33_IFG_OFFSET    1
#define    RTL8370_METER33_IFG_MASK    0x2
#define    RTL8370_METER32_IFG_OFFSET    0
#define    RTL8370_METER32_IFG_MASK    0x1

#define    RTL8370_REG_METER_IFG_CTRL3    0x1715
#define    RTL8370_METER63_IFG_OFFSET    15
#define    RTL8370_METER63_IFG_MASK    0x8000
#define    RTL8370_METER62_IFG_OFFSET    14
#define    RTL8370_METER62_IFG_MASK    0x4000
#define    RTL8370_METER61_IFG_OFFSET    13
#define    RTL8370_METER61_IFG_MASK    0x2000
#define    RTL8370_METER60_IFG_OFFSET    12
#define    RTL8370_METER60_IFG_MASK    0x1000
#define    RTL8370_METER59_IFG_OFFSET    11
#define    RTL8370_METER59_IFG_MASK    0x800
#define    RTL8370_METER58_IFG_OFFSET    10
#define    RTL8370_METER58_IFG_MASK    0x400
#define    RTL8370_METER57_IFG_OFFSET    9
#define    RTL8370_METER57_IFG_MASK    0x200
#define    RTL8370_METER56_IFG_OFFSET    8
#define    RTL8370_METER56_IFG_MASK    0x100
#define    RTL8370_METER55_IFG_OFFSET    7
#define    RTL8370_METER55_IFG_MASK    0x80
#define    RTL8370_METER54_IFG_OFFSET    6
#define    RTL8370_METER54_IFG_MASK    0x40
#define    RTL8370_METER53_IFG_OFFSET    5
#define    RTL8370_METER53_IFG_MASK    0x20
#define    RTL8370_METER52_IFG_OFFSET    4
#define    RTL8370_METER52_IFG_MASK    0x10
#define    RTL8370_METER51_IFG_OFFSET    3
#define    RTL8370_METER51_IFG_MASK    0x8
#define    RTL8370_METER50_IFG_OFFSET    2
#define    RTL8370_METER50_IFG_MASK    0x4
#define    RTL8370_METER49_IFG_OFFSET    1
#define    RTL8370_METER49_IFG_MASK    0x2
#define    RTL8370_METER48_IFG_OFFSET    0
#define    RTL8370_METER48_IFG_MASK    0x1

/* (16'h1800)8051_RLDP_EEE_reg */

#define    RTL8370_REG_EEELLDP_CTRL0    0x1820
#define    RTL8370_EEELLDP_SUBTYPE_OFFSET    6
#define    RTL8370_EEELLDP_SUBTYPE_MASK    0x3FC0
#define    RTL8370_EEELLDP_ACK_READY_OFFSET    5
#define    RTL8370_EEELLDP_ACK_READY_MASK    0x20
#define    RTL8370_EEELLDP_CAP_READY_OFFSET    4
#define    RTL8370_EEELLDP_CAP_READY_MASK    0x10
#define    RTL8370_EEELLDP_INT_8051_OFFSET    3
#define    RTL8370_EEELLDP_INT_8051_MASK    0x8
#define    RTL8370_EEELLDP_TRAP_DW8051_OFFSET    2
#define    RTL8370_EEELLDP_TRAP_DW8051_MASK    0x4
#define    RTL8370_EEELLDP_TRAP_CPU_OFFSET    1
#define    RTL8370_EEELLDP_TRAP_CPU_MASK    0x2
#define    RTL8370_EEELLDP_ENABLE_OFFSET    0
#define    RTL8370_EEELLDP_ENABLE_MASK    0x1

#define    RTL8370_REG_EEELLDP_CTRL1    0x1821
#define    RTL8370_EEELLDP_ACK_PORT_OFFSET    4
#define    RTL8370_EEELLDP_ACK_PORT_MASK    0xF0
#define    RTL8370_EEELLDP_CAP_PORT_OFFSET    0
#define    RTL8370_EEELLDP_CAP_PORT_MASK    0xF

#define    RTL8370_REG_EEELLDP_PMSK    0x1822

#define    RTL8370_REG_EEELLDP_FRAMEU0D    0x1823

#define    RTL8370_REG_EEELLDP_FRAMEU0C    0x1824

#define    RTL8370_REG_EEELLDP_FRAMEU0B    0x1825

#define    RTL8370_REG_EEELLDP_FRAMEU0A    0x1826

#define    RTL8370_REG_EEELLDP_FRAMEU09    0x1827

#define    RTL8370_REG_EEELLDP_FRAMEU08    0x1828

#define    RTL8370_REG_EEELLDP_FRAMEU07    0x1829

#define    RTL8370_REG_EEELLDP_FRAMEU06    0x182a

#define    RTL8370_REG_EEELLDP_FRAMEU05    0x182b

#define    RTL8370_REG_EEELLDP_FRAMEU04    0x182c

#define    RTL8370_REG_EEELLDP_FRAMEU03    0x182d

#define    RTL8370_REG_EEELLDP_FRAMEU02    0x182e

#define    RTL8370_REG_EEELLDP_FRAMEU01    0x182f

#define    RTL8370_REG_EEELLDP_FRAMEU00    0x1830
#define    RTL8370_EEELLDP_FRAMEU00_OFFSET    0
#define    RTL8370_EEELLDP_FRAMEU00_MASK    0xFF

#define    RTL8370_REG_EEELLDP_CAP_FRAMEL08    0x1831

#define    RTL8370_REG_EEELLDP_CAP_FRAMEL07    0x1832

#define    RTL8370_REG_EEELLDP_CAP_FRAMEL06    0x1833

#define    RTL8370_REG_EEELLDP_CAP_FRAMEL05    0x1834

#define    RTL8370_REG_EEELLDP_CAP_FRAMEL04    0x1835

#define    RTL8370_REG_EEELLDP_CAP_FRAMEL03    0x1836

#define    RTL8370_REG_EEELLDP_CAP_FRAMEL02    0x1837

#define    RTL8370_REG_EEELLDP_CAP_FRAMEL01    0x1838

#define    RTL8370_REG_EEELLDP_CAP_FRAMEL00    0x1839

#define    RTL8370_REG_EEELLDP_ACK_FRAMEL08    0x183a

#define    RTL8370_REG_EEELLDP_ACK_FRAMEL07    0x183b

#define    RTL8370_REG_EEELLDP_ACK_FRAMEL06    0x183c

#define    RTL8370_REG_EEELLDP_ACK_FRAMEL05    0x183d

#define    RTL8370_REG_EEELLDP_ACK_FRAMEL04    0x183e

#define    RTL8370_REG_EEELLDP_ACK_FRAMEL03    0x183f

#define    RTL8370_REG_EEELLDP_ACK_FRAMEL02    0x1840

#define    RTL8370_REG_EEELLDP_ACK_FRAMEL01    0x1841

#define    RTL8370_REG_EEELLDP_ACK_FRAMEL00    0x1842

#define    RTL8370_REG_EEELLDP_RX_VALUE_P00_08    0x1843

#define    RTL8370_REG_EEELLDP_RX_VALUE_P00_07    0x1844

#define    RTL8370_REG_EEELLDP_RX_VALUE_P00_06    0x1845

#define    RTL8370_REG_EEELLDP_RX_VALUE_P00_05    0x1846

#define    RTL8370_REG_EEELLDP_RX_VALUE_P00_04    0x1847

#define    RTL8370_REG_EEELLDP_RX_VALUE_P00_03    0x1848

#define    RTL8370_REG_EEELLDP_RX_VALUE_P00_02    0x1849

#define    RTL8370_REG_EEELLDP_RX_VALUE_P00_01    0x184a

#define    RTL8370_REG_EEELLDP_RX_VALUE_P00_00    0x184b

#define    RTL8370_REG_EEELLDP_RX_VALUE_P01_08    0x184c

#define    RTL8370_REG_EEELLDP_RX_VALUE_P01_07    0x184d

#define    RTL8370_REG_EEELLDP_RX_VALUE_P01_06    0x184e

#define    RTL8370_REG_EEELLDP_RX_VALUE_P01_05    0x184f

#define    RTL8370_REG_EEELLDP_RX_VALUE_P01_04    0x1850

#define    RTL8370_REG_EEELLDP_RX_VALUE_P01_03    0x1851

#define    RTL8370_REG_EEELLDP_RX_VALUE_P01_02    0x1852

#define    RTL8370_REG_EEELLDP_RX_VALUE_P01_01    0x1853

#define    RTL8370_REG_EEELLDP_RX_VALUE_P01_00    0x1854

#define    RTL8370_REG_EEELLDP_RX_VALUE_P02_08    0x1855

#define    RTL8370_REG_EEELLDP_RX_VALUE_P02_07    0x1856

#define    RTL8370_REG_EEELLDP_RX_VALUE_P02_06    0x1857

#define    RTL8370_REG_EEELLDP_RX_VALUE_P02_05    0x1858

#define    RTL8370_REG_EEELLDP_RX_VALUE_P02_04    0x1859

#define    RTL8370_REG_EEELLDP_RX_VALUE_P02_03    0x185a

#define    RTL8370_REG_EEELLDP_RX_VALUE_P02_02    0x185b

#define    RTL8370_REG_EEELLDP_RX_VALUE_P02_01    0x185c

#define    RTL8370_REG_EEELLDP_RX_VALUE_P02_00    0x185d

#define    RTL8370_REG_EEELLDP_RX_VALUE_P03_08    0x185e

#define    RTL8370_REG_EEELLDP_RX_VALUE_P03_07    0x185f

#define    RTL8370_REG_EEELLDP_RX_VALUE_P03_06    0x1860

#define    RTL8370_REG_EEELLDP_RX_VALUE_P03_05    0x1861

#define    RTL8370_REG_EEELLDP_RX_VALUE_P03_04    0x1862

#define    RTL8370_REG_EEELLDP_RX_VALUE_P03_03    0x1863

#define    RTL8370_REG_EEELLDP_RX_VALUE_P03_02    0x1864

#define    RTL8370_REG_EEELLDP_RX_VALUE_P03_01    0x1865

#define    RTL8370_REG_EEELLDP_RX_VALUE_P03_00    0x1866

#define    RTL8370_REG_EEELLDP_RX_VALUE_P04_08    0x1867

#define    RTL8370_REG_EEELLDP_RX_VALUE_P04_07    0x1868

#define    RTL8370_REG_EEELLDP_RX_VALUE_P04_06    0x1869

#define    RTL8370_REG_EEELLDP_RX_VALUE_P04_05    0x186a

#define    RTL8370_REG_EEELLDP_RX_VALUE_P04_04    0x186b

#define    RTL8370_REG_EEELLDP_RX_VALUE_P04_03    0x186c

#define    RTL8370_REG_EEELLDP_RX_VALUE_P04_02    0x186d

#define    RTL8370_REG_EEELLDP_RX_VALUE_P04_01    0x186e

#define    RTL8370_REG_EEELLDP_RX_VALUE_P04_00    0x186f

#define    RTL8370_REG_EEELLDP_RX_VALUE_P05_08    0x1870

#define    RTL8370_REG_EEELLDP_RX_VALUE_P05_07    0x1871

#define    RTL8370_REG_EEELLDP_RX_VALUE_P05_06    0x1872

#define    RTL8370_REG_EEELLDP_RX_VALUE_P05_05    0x1873

#define    RTL8370_REG_EEELLDP_RX_VALUE_P05_04    0x1874

#define    RTL8370_REG_EEELLDP_RX_VALUE_P05_03    0x1875

#define    RTL8370_REG_EEELLDP_RX_VALUE_P05_02    0x1876

#define    RTL8370_REG_EEELLDP_RX_VALUE_P05_01    0x1877

#define    RTL8370_REG_EEELLDP_RX_VALUE_P05_00    0x1878

#define    RTL8370_REG_EEELLDP_RX_VALUE_P06_08    0x1879

#define    RTL8370_REG_EEELLDP_RX_VALUE_P06_07    0x187a

#define    RTL8370_REG_EEELLDP_RX_VALUE_P06_06    0x187b

#define    RTL8370_REG_EEELLDP_RX_VALUE_P06_05    0x187c

#define    RTL8370_REG_EEELLDP_RX_VALUE_P06_04    0x187d

#define    RTL8370_REG_EEELLDP_RX_VALUE_P06_03    0x187e

#define    RTL8370_REG_EEELLDP_RX_VALUE_P06_02    0x187f

#define    RTL8370_REG_EEELLDP_RX_VALUE_P06_01    0x1880

#define    RTL8370_REG_EEELLDP_RX_VALUE_P06_00    0x1881

#define    RTL8370_REG_EEELLDP_RX_VALUE_P07_08    0x1882

#define    RTL8370_REG_EEELLDP_RX_VALUE_P07_07    0x1883

#define    RTL8370_REG_EEELLDP_RX_VALUE_P07_06    0x1884

#define    RTL8370_REG_EEELLDP_RX_VALUE_P07_05    0x1885

#define    RTL8370_REG_EEELLDP_RX_VALUE_P07_04    0x1886

#define    RTL8370_REG_EEELLDP_RX_VALUE_P07_03    0x1887

#define    RTL8370_REG_EEELLDP_RX_VALUE_P07_02    0x1888

#define    RTL8370_REG_EEELLDP_RX_VALUE_P07_01    0x1889

#define    RTL8370_REG_EEELLDP_RX_VALUE_P07_00    0x188a

#define    RTL8370_REG_EEELLDP_RX_VALUE_P08_08    0x188b

#define    RTL8370_REG_EEELLDP_RX_VALUE_P08_07    0x188c

#define    RTL8370_REG_EEELLDP_RX_VALUE_P08_06    0x188d

#define    RTL8370_REG_EEELLDP_RX_VALUE_P08_05    0x188e

#define    RTL8370_REG_EEELLDP_RX_VALUE_P08_04    0x188f

#define    RTL8370_REG_EEELLDP_RX_VALUE_P08_03    0x1890

#define    RTL8370_REG_EEELLDP_RX_VALUE_P08_02    0x1891

#define    RTL8370_REG_EEELLDP_RX_VALUE_P08_01    0x1892

#define    RTL8370_REG_EEELLDP_RX_VALUE_P08_00    0x1893

#define    RTL8370_REG_EEELLDP_RX_VALUE_P09_08    0x1894

#define    RTL8370_REG_EEELLDP_RX_VALUE_P09_07    0x1895

#define    RTL8370_REG_EEELLDP_RX_VALUE_P09_06    0x1896

#define    RTL8370_REG_EEELLDP_RX_VALUE_P09_05    0x1897

#define    RTL8370_REG_EEELLDP_RX_VALUE_P09_04    0x1898

#define    RTL8370_REG_EEELLDP_RX_VALUE_P09_03    0x1899

#define    RTL8370_REG_EEELLDP_RX_VALUE_P09_02    0x189a

#define    RTL8370_REG_EEELLDP_RX_VALUE_P09_01    0x189b

#define    RTL8370_REG_EEELLDP_RX_VALUE_P09_00    0x189c

#define    RTL8370_REG_EEELLDP_RX_VALUE_P10_08    0x189d

#define    RTL8370_REG_EEELLDP_RX_VALUE_P10_07    0x189e

#define    RTL8370_REG_EEELLDP_RX_VALUE_P10_06    0x189f

#define    RTL8370_REG_EEELLDP_RX_VALUE_P10_05    0x18a0

#define    RTL8370_REG_EEELLDP_RX_VALUE_P10_04    0x18a1

#define    RTL8370_REG_EEELLDP_RX_VALUE_P10_03    0x18a2

#define    RTL8370_REG_EEELLDP_RX_VALUE_P10_02    0x18a3

#define    RTL8370_REG_EEELLDP_RX_VALUE_P10_01    0x18a4

#define    RTL8370_REG_EEELLDP_RX_VALUE_P10_00    0x18a5

#define    RTL8370_REG_EEELLDP_RX_VALUE_P11_08    0x18a6

#define    RTL8370_REG_EEELLDP_RX_VALUE_P11_07    0x18a7

#define    RTL8370_REG_EEELLDP_RX_VALUE_P11_06    0x18a8

#define    RTL8370_REG_EEELLDP_RX_VALUE_P11_05    0x18a9

#define    RTL8370_REG_EEELLDP_RX_VALUE_P11_04    0x18aa

#define    RTL8370_REG_EEELLDP_RX_VALUE_P11_03    0x18ab

#define    RTL8370_REG_EEELLDP_RX_VALUE_P11_02    0x18ac

#define    RTL8370_REG_EEELLDP_RX_VALUE_P11_01    0x18ad

#define    RTL8370_REG_EEELLDP_RX_VALUE_P11_00    0x18ae

#define    RTL8370_REG_EEELLDP_RX_VALUE_P12_08    0x18af

#define    RTL8370_REG_EEELLDP_RX_VALUE_P12_07    0x18b0

#define    RTL8370_REG_EEELLDP_RX_VALUE_P12_06    0x18b1

#define    RTL8370_REG_EEELLDP_RX_VALUE_P12_05    0x18b2

#define    RTL8370_REG_EEELLDP_RX_VALUE_P12_04    0x18b3

#define    RTL8370_REG_EEELLDP_RX_VALUE_P12_03    0x18b4

#define    RTL8370_REG_EEELLDP_RX_VALUE_P12_02    0x18b5

#define    RTL8370_REG_EEELLDP_RX_VALUE_P12_01    0x18b6

#define    RTL8370_REG_EEELLDP_RX_VALUE_P12_00    0x18b7

#define    RTL8370_REG_EEELLDP_RX_VALUE_P13_08    0x18b8

#define    RTL8370_REG_EEELLDP_RX_VALUE_P13_07    0x18b9

#define    RTL8370_REG_EEELLDP_RX_VALUE_P13_06    0x18ba

#define    RTL8370_REG_EEELLDP_RX_VALUE_P13_05    0x18bb

#define    RTL8370_REG_EEELLDP_RX_VALUE_P13_04    0x18bc

#define    RTL8370_REG_EEELLDP_RX_VALUE_P13_03    0x18bd

#define    RTL8370_REG_EEELLDP_RX_VALUE_P13_02    0x18be

#define    RTL8370_REG_EEELLDP_RX_VALUE_P13_01    0x18bf

#define    RTL8370_REG_EEELLDP_RX_VALUE_P13_00    0x18c0

#define    RTL8370_REG_EEELLDP_RX_VALUE_P14_08    0x18c1

#define    RTL8370_REG_EEELLDP_RX_VALUE_P14_07    0x18c2

#define    RTL8370_REG_EEELLDP_RX_VALUE_P14_06    0x18c3

#define    RTL8370_REG_EEELLDP_RX_VALUE_P14_05    0x18c4

#define    RTL8370_REG_EEELLDP_RX_VALUE_P14_04    0x18c5

#define    RTL8370_REG_EEELLDP_RX_VALUE_P14_03    0x18c6

#define    RTL8370_REG_EEELLDP_RX_VALUE_P14_02    0x18c7

#define    RTL8370_REG_EEELLDP_RX_VALUE_P14_01    0x18c8

#define    RTL8370_REG_EEELLDP_RX_VALUE_P14_00    0x18c9

#define    RTL8370_REG_EEELLDP_RX_VALUE_P15_08    0x18ca

#define    RTL8370_REG_EEELLDP_RX_VALUE_P15_07    0x18cb

#define    RTL8370_REG_EEELLDP_RX_VALUE_P15_06    0x18cc

#define    RTL8370_REG_EEELLDP_RX_VALUE_P15_05    0x18cd

#define    RTL8370_REG_EEELLDP_RX_VALUE_P15_04    0x18ce

#define    RTL8370_REG_EEELLDP_RX_VALUE_P15_03    0x18cf

#define    RTL8370_REG_EEELLDP_RX_VALUE_P15_02    0x18d0

#define    RTL8370_REG_EEELLDP_RX_VALUE_P15_01    0x18d1

#define    RTL8370_REG_EEELLDP_RX_VALUE_P15_00    0x18d2

#define    RTL8370_REG_RRCP_CTRL0    0x18d3
#define    RTL8370_RRCP_TRAP_8051_OFFSET    8
#define    RTL8370_RRCP_TRAP_8051_MASK    0x100
#define    RTL8370_RRCP_V2_EN_OFFSET    4
#define    RTL8370_RRCP_V2_EN_MASK    0x10
#define    RTL8370_RRCP_V1_EN_OFFSET    0
#define    RTL8370_RRCP_V1_EN_MASK    0x1

#define    RTL8370_REG_RRCP_CTRL3    0x18d4

#define    RTL8370_REG_RRCP_CTRL1    0x18d5

#define    RTL8370_REG_RRCP_CTRL2    0x18d6

#define    RTL8370_REG_RLDP_CTRL0    0x18e0
#define    RTL8370_RLDP_INDICATOR_SOURCE_OFFSET    4
#define    RTL8370_RLDP_INDICATOR_SOURCE_MASK    0x10
#define    RTL8370_RLDP_GEN_RANDOM_OFFSET    3
#define    RTL8370_RLDP_GEN_RANDOM_MASK    0x8
#define    RTL8370_RLDP_COMP_ID_OFFSET    2
#define    RTL8370_RLDP_COMP_ID_MASK    0x4
#define    RTL8370_RLDP_8051_ENABLE_OFFSET    1
#define    RTL8370_RLDP_8051_ENABLE_MASK    0x2
#define    RTL8370_RLDP_ENABLE_OFFSET    0
#define    RTL8370_RLDP_ENABLE_MASK    0x1

#define    RTL8370_REG_RLDP_CTRL1    0x18e1
#define    RTL8370_RLDP_RETRY_COUNT_LOOPSTATE_OFFSET    8
#define    RTL8370_RLDP_RETRY_COUNT_LOOPSTATE_MASK    0xFF00
#define    RTL8370_RLDP_RETRY_COUNT_CHKSTATE_OFFSET    0
#define    RTL8370_RLDP_RETRY_COUNT_CHKSTATE_MASK    0xFF

#define    RTL8370_REG_RLDP_CTRL2    0x18e2

#define    RTL8370_REG_RLDP_CTRL3    0x18e3

#define    RTL8370_REG_RLDP_CTRL4    0x18e4

#define    RTL8370_REG_RLDP_RAND_NUM0    0x18e5

#define    RTL8370_REG_RLDP_RAND_NUM1    0x18e6

#define    RTL8370_REG_RLDP_RAND_NUM2    0x18e7

#define    RTL8370_REG_RLDP_SEED_NUM0    0x18e8

#define    RTL8370_REG_RLDP_SEED_NUM1    0x18e9

#define    RTL8370_REG_RLDP_SEED_NUM2    0x18ea

#define    RTL8370_REG_RLDP_LOOP_PMSK    0x18eb

#define    RTL8370_REG_RLDP_LOOP_PORT_REG0    0x18ec
#define    RTL8370_RLDP_LOOP_PORT_01_OFFSET    8
#define    RTL8370_RLDP_LOOP_PORT_01_MASK    0xFF00
#define    RTL8370_RLDP_LOOP_PORT_00_OFFSET    0
#define    RTL8370_RLDP_LOOP_PORT_00_MASK    0xFF

#define    RTL8370_REG_RLDP_LOOP_PORT_REG1    0x18ed
#define    RTL8370_RLDP_LOOP_PORT_03_OFFSET    8
#define    RTL8370_RLDP_LOOP_PORT_03_MASK    0xFF00
#define    RTL8370_RLDP_LOOP_PORT_02_OFFSET    0
#define    RTL8370_RLDP_LOOP_PORT_02_MASK    0xFF

#define    RTL8370_REG_RLDP_LOOP_PORT_REG2    0x18ee
#define    RTL8370_RLDP_LOOP_PORT_05_OFFSET    8
#define    RTL8370_RLDP_LOOP_PORT_05_MASK    0xFF00
#define    RTL8370_RLDP_LOOP_PORT_04_OFFSET    0
#define    RTL8370_RLDP_LOOP_PORT_04_MASK    0xFF

#define    RTL8370_REG_RLDP_LOOP_PORT_REG3    0x18ef
#define    RTL8370_RLDP_LOOP_PORT_07_OFFSET    8
#define    RTL8370_RLDP_LOOP_PORT_07_MASK    0xFF00
#define    RTL8370_RLDP_LOOP_PORT_06_OFFSET    0
#define    RTL8370_RLDP_LOOP_PORT_06_MASK    0xFF

#define    RTL8370_REG_RLDP_LOOP_PORT_REG4    0x18f0
#define    RTL8370_RLDP_LOOP_PORT_09_OFFSET    8
#define    RTL8370_RLDP_LOOP_PORT_09_MASK    0xFF00
#define    RTL8370_RLDP_LOOP_PORT_08_OFFSET    0
#define    RTL8370_RLDP_LOOP_PORT_08_MASK    0xFF

#define    RTL8370_REG_RLDP_LOOP_PORT_REG5    0x18f1
#define    RTL8370_RLDP_LOOP_PORT_11_OFFSET    8
#define    RTL8370_RLDP_LOOP_PORT_11_MASK    0xFF00
#define    RTL8370_RLDP_LOOP_PORT_10_OFFSET    0
#define    RTL8370_RLDP_LOOP_PORT_10_MASK    0xFF

#define    RTL8370_REG_RLDP_LOOP_PORT_REG6    0x18f2
#define    RTL8370_RLDP_LOOP_PORT_13_OFFSET    8
#define    RTL8370_RLDP_LOOP_PORT_13_MASK    0xFF00
#define    RTL8370_RLDP_LOOP_PORT_12_OFFSET    0
#define    RTL8370_RLDP_LOOP_PORT_12_MASK    0xFF

#define    RTL8370_REG_RLDP_LOOP_PORT_REG7    0x18f3
#define    RTL8370_RLDP_LOOP_PORT_15_OFFSET    8
#define    RTL8370_RLDP_LOOP_PORT_15_MASK    0xFF00
#define    RTL8370_RLDP_LOOP_PORT_14_OFFSET    0
#define    RTL8370_RLDP_LOOP_PORT_14_MASK    0xFF

/* (16'h1a00)nic_reg */

#define    RTL8370_REG_NIC_RXRDRL    0x1a04
#define    RTL8370_NIC_RXRDRL_OFFSET    0
#define    RTL8370_NIC_RXRDRL_MASK    0xFF

#define    RTL8370_REG_NIC_RXRDRH    0x1a05
#define    RTL8370_NIC_RXRDRH_OFFSET    0
#define    RTL8370_NIC_RXRDRH_MASK    0xFF

#define    RTL8370_REG_NIC_TXASRL    0x1a08
#define    RTL8370_NIC_TXASRL_OFFSET    0
#define    RTL8370_NIC_TXASRL_MASK    0xFF

#define    RTL8370_REG_NIC_TXASRH    0x1a09
#define    RTL8370_NIC_TXASRH_OFFSET    0
#define    RTL8370_NIC_TXASRH_MASK    0xFF

#define    RTL8370_REG_NIC_RXCMDR    0x1a0c
#define    RTL8370_NIC_RXCMDR_OFFSET    0
#define    RTL8370_NIC_RXCMDR_MASK    0x1

#define    RTL8370_REG_NIC_TXCMDR    0x1a0d
#define    RTL8370_NIC_TXCMDR_OFFSET    0
#define    RTL8370_NIC_TXCMDR_MASK    0x1

#define    RTL8370_REG_NIC_IMS    0x1a0e
#define    RTL8370_NIC_RXIS_OFFSET    7
#define    RTL8370_NIC_RXIS_MASK    0x80
#define    RTL8370_NIC_TXIS_OFFSET    6
#define    RTL8370_NIC_TXIS_MASK    0x40
#define    RTL8370_NIC_TXES_OFFSET    5
#define    RTL8370_NIC_TXES_MASK    0x20
#define    RTL8370_NIC_RXBUS_OFFSET    3
#define    RTL8370_NIC_RXBUS_MASK    0x8
#define    RTL8370_NIC_TXBOS_OFFSET    2
#define    RTL8370_NIC_TXBOS_MASK    0x4
#define    RTL8370_NIC_RXMIS_OFFSET    1
#define    RTL8370_NIC_RXMIS_MASK    0x2
#define    RTL8370_NIC_TXNLS_OFFSET    0
#define    RTL8370_NIC_TXNLS_MASK    0x1

#define    RTL8370_REG_NIC_IMR    0x1a0f
#define    RTL8370_NIC_RXIE_OFFSET    7
#define    RTL8370_NIC_RXIE_MASK    0x80
#define    RTL8370_NIC_TXIE_OFFSET    6
#define    RTL8370_NIC_TXIE_MASK    0x40
#define    RTL8370_NIC_TXEE_OFFSET    5
#define    RTL8370_NIC_TXEE_MASK    0x20
#define    RTL8370_NIC_RXBUE_OFFSET    3
#define    RTL8370_NIC_RXBUE_MASK    0x8
#define    RTL8370_NIC_TXBOE_OFFSET    2
#define    RTL8370_NIC_TXBOE_MASK    0x4
#define    RTL8370_NIC_RXMIE_OFFSET    1
#define    RTL8370_NIC_RXMIE_MASK    0x2
#define    RTL8370_NIC_TXNLE_OFFSET    0
#define    RTL8370_NIC_TXNLE_MASK    0x1

#define    RTL8370_REG_NIC_RXCR0    0x1a14
#define    RTL8370_NIC_HFPPE_OFFSET    7
#define    RTL8370_NIC_HFPPE_MASK    0x80
#define    RTL8370_NIC_HFMPE_OFFSET    6
#define    RTL8370_NIC_HFMPE_MASK    0x40
#define    RTL8370_NIC_RXBPE_OFFSET    5
#define    RTL8370_NIC_RXBPE_MASK    0x20
#define    RTL8370_NIC_RXMPE_OFFSET    4
#define    RTL8370_NIC_RXMPE_MASK    0x10
#define    RTL8370_NIC_RXPPS_OFFSET    2
#define    RTL8370_NIC_RXPPS_MASK    0xC
#define    RTL8370_NIC_RXAPE_OFFSET    1
#define    RTL8370_NIC_RXAPE_MASK    0x2
#define    RTL8370_NIC_ARPPE_OFFSET    0
#define    RTL8370_NIC_ARPPE_MASK    0x1

#define    RTL8370_REG_NIC_RXCR1    0x1a15
#define    RTL8370_NIC_RL4CEPE_OFFSET    4
#define    RTL8370_NIC_RL4CEPE_MASK    0x10
#define    RTL8370_NIC_RL3CEPE_OFFSET    3
#define    RTL8370_NIC_RL3CEPE_MASK    0x8
#define    RTL8370_NIC_RCRCEPE_OFFSET    2
#define    RTL8370_NIC_RCRCEPE_MASK    0x4
#define    RTL8370_NIC_RMCRC_OFFSET    1
#define    RTL8370_NIC_RMCRC_MASK    0x2
#define    RTL8370_NIC_RXENABLE_OFFSET    0
#define    RTL8370_NIC_RXENABLE_MASK    0x1

#define    RTL8370_REG_NIC_TXCR    0x1a16
#define    RTL8370_NIC_LBE_OFFSET    2
#define    RTL8370_NIC_LBE_MASK    0x4
#define    RTL8370_NIC_TXMFM_OFFSET    1
#define    RTL8370_NIC_TXMFM_MASK    0x2
#define    RTL8370_NIC_TXENABLE_OFFSET    0
#define    RTL8370_NIC_TXENABLE_MASK    0x1

#define    RTL8370_REG_NIC_GCR    0x1a17
#define    RTL8370_NIC_RXMTU_OFFSET    4
#define    RTL8370_NIC_RXMTU_MASK    0x30
#define    RTL8370_NIC_SRST_OFFSET    0
#define    RTL8370_NIC_SRST_MASK    0x1

#define    RTL8370_REG_NIC_MHR0    0x1a24
#define    RTL8370_NIC_MHR0_OFFSET    0
#define    RTL8370_NIC_MHR0_MASK    0xFF

#define    RTL8370_REG_NIC_MHR1    0x1a25
#define    RTL8370_NIC_MHR1_OFFSET    0
#define    RTL8370_NIC_MHR1_MASK    0xFF

#define    RTL8370_REG_NIC_MHR2    0x1a26
#define    RTL8370_NIC_MHR2_OFFSET    0
#define    RTL8370_NIC_MHR2_MASK    0xFF

#define    RTL8370_REG_NIC_MHR3    0x1a27
#define    RTL8370_NIC_MHR3_OFFSET    0
#define    RTL8370_NIC_MHR3_MASK    0xFF

#define    RTL8370_REG_NIC_MHR4    0x1a28
#define    RTL8370_NIC_MHR4_OFFSET    0
#define    RTL8370_NIC_MHR4_MASK    0xFF

#define    RTL8370_REG_NIC_MHR5    0x1a29
#define    RTL8370_NIC_MHR5_OFFSET    0
#define    RTL8370_NIC_MHR5_MASK    0xFF

#define    RTL8370_REG_NIC_MHR6    0x1a2a
#define    RTL8370_NIC_MHR6_OFFSET    0
#define    RTL8370_NIC_MHR6_MASK    0xFF

#define    RTL8370_REG_NIC_MHR7    0x1a2b
#define    RTL8370_NIC_MHR7_OFFSET    0
#define    RTL8370_NIC_MHR7_MASK    0xFF

#define    RTL8370_REG_NIC_PAHR0    0x1a2c
#define    RTL8370_NIC_PAHR0_OFFSET    0
#define    RTL8370_NIC_PAHR0_MASK    0xFF

#define    RTL8370_REG_NIC_PAHR1    0x1a2d
#define    RTL8370_NIC_PAHR1_OFFSET    0
#define    RTL8370_NIC_PAHR1_MASK    0xFF

#define    RTL8370_REG_NIC_PAHR2    0x1a2e
#define    RTL8370_NIC_PAHR2_OFFSET    0
#define    RTL8370_NIC_PAHR2_MASK    0xFF

#define    RTL8370_REG_NIC_PAHR3    0x1a2f
#define    RTL8370_NIC_PAHR3_OFFSET    0
#define    RTL8370_NIC_PAHR3_MASK    0xFF

#define    RTL8370_REG_NIC_PAHR4    0x1a30
#define    RTL8370_NIC_PAHR4_OFFSET    0
#define    RTL8370_NIC_PAHR4_MASK    0xFF

#define    RTL8370_REG_NIC_PAHR5    0x1a31
#define    RTL8370_NIC_PAHR5_OFFSET    0
#define    RTL8370_NIC_PAHR5_MASK    0xFF

#define    RTL8370_REG_NIC_PAHR6    0x1a32
#define    RTL8370_NIC_PAHR6_OFFSET    0
#define    RTL8370_NIC_PAHR6_MASK    0xFF

#define    RTL8370_REG_NIC_PAHR7    0x1a33
#define    RTL8370_NIC_PAHR7_OFFSET    0
#define    RTL8370_NIC_PAHR7_MASK    0xFF

#define    RTL8370_REG_NIC_TXSTOPRL    0x1a44
#define    RTL8370_NIC_TXSTOPRL_OFFSET    0
#define    RTL8370_NIC_TXSTOPRL_MASK    0xFF

#define    RTL8370_REG_NIC_TXSTOPRH    0x1a45
#define    RTL8370_NIC_TXSTOPRH_OFFSET    0
#define    RTL8370_NIC_TXSTOPRH_MASK    0x7

#define    RTL8370_REG_NIC_RXSTOPRL    0x1a46
#define    RTL8370_NIC_RXSTOPRL_OFFSET    0
#define    RTL8370_NIC_RXSTOPRL_MASK    0xFF

#define    RTL8370_REG_NIC_RXSTOPRH    0x1a47
#define    RTL8370_NIC_RXSTOPH_OFFSET    0
#define    RTL8370_NIC_RXSTOPH_MASK    0x7
#define    RTL8370_NIC_RXFST_OFFSET    0
#define    RTL8370_NIC_RXFST_MASK    0xFF

#define    RTL8370_REG_NIC_RXMBTRL    0x1a4c
#define    RTL8370_NIC_RXMBTRL_OFFSET    0
#define    RTL8370_NIC_RXMBTRL_MASK    0xFF

#define    RTL8370_REG_NIC_RXMBTRH    0x1a4d
#define    RTL8370_NIC_RXMBTRH_OFFSET    0
#define    RTL8370_NIC_RXMBTRH_MASK    0x7F

#define    RTL8370_REG_NIC_RXMPTR    0x1a4e
#define    RTL8370_NIC_RXMPTR_OFFSET    0
#define    RTL8370_NIC_RXMPTR_MASK    0xFF

#define    RTL8370_REG_NIC_T0TR    0x1a4f
#define    RTL8370_NIC_T0TR_OFFSET    0
#define    RTL8370_NIC_T0TR_MASK    0xFF

#define    RTL8370_REG_NIC_CRXCPRL    0x1a50
#define    RTL8370_NIC_CRXCPRL_OFFSET    0
#define    RTL8370_NIC_CRXCPRL_MASK    0xFF

#define    RTL8370_REG_NIC_CRXCPRH    0x1a51
#define    RTL8370_NIC_CRXCPRH_OFFSET    0
#define    RTL8370_NIC_CRXCPRH_MASK    0xFF

#define    RTL8370_REG_NIC_CTXCPRL    0x1a52
#define    RTL8370_NIC_CTXCPRL_OFFSET    0
#define    RTL8370_NIC_CTXCPRL_MASK    0xFF

#define    RTL8370_REG_NIC_CTXPCRH    0x1a53
#define    RTL8370_NIC_CTXPCRH_OFFSET    0
#define    RTL8370_NIC_CTXPCRH_MASK    0xFF

#define    RTL8370_REG_NIC_SRXCURPKTRL    0x1a54
#define    RTL8370_NIC_SRXCURPKTRL_OFFSET    0
#define    RTL8370_NIC_SRXCURPKTRL_MASK    0xFF

#define    RTL8370_REG_NIC_SRXCURPKTRH    0x1a55
#define    RTL8370_NIC_SRXCURPKTRH_OFFSET    0
#define    RTL8370_NIC_SRXCURPKTRH_MASK    0xFF

#define    RTL8370_REG_NIC_STXCURPKTRL    0x1a56
#define    RTL8370_NIC_STXCURPKTRL_OFFSET    0
#define    RTL8370_NIC_STXCURPKTRL_MASK    0xFF

#define    RTL8370_REG_NIC_STXCURPKTRH    0x1a57
#define    RTL8370_NIC_STXCURPKTRH_OFFSET    0
#define    RTL8370_NIC_STXCURPKTRH_MASK    0xFF

#define    RTL8370_REG_NIC_STXPKTLENRL    0x1a58
#define    RTL8370_NIC_STXPKTLENRL_OFFSET    0
#define    RTL8370_NIC_STXPKTLENRL_MASK    0xFF

#define    RTL8370_REG_NIC_STXPKTLENRH    0x1a59
#define    RTL8370_NIC_STXPKTLENRH_OFFSET    0
#define    RTL8370_NIC_STXPKTLENRH_MASK    0xFF

#define    RTL8370_REG_NIC_STXCURUNITRL    0x1a5a
#define    RTL8370_NIC_STXCURUNITRL_OFFSET    0
#define    RTL8370_NIC_STXCURUNITRL_MASK    0xFF

#define    RTL8370_REG_NIC_STXCURUNITRH    0x1a5b
#define    RTL8370_NIC_STXCURUNITRH_OFFSET    0
#define    RTL8370_NIC_STXCURUNITRH_MASK    0xFF

/* (16'h1b00)LED */

#define    RTL8370_REG_LED_SYS_CONFIG    0x1b00
#define    RTL8370_LED_SYS_CONFIG_DUMMY_0_OFFSET    14
#define    RTL8370_LED_SYS_CONFIG_DUMMY_0_MASK    0xC000
#define    RTL8370_LED_EEE_LPI_MODE_OFFSET    13
#define    RTL8370_LED_EEE_LPI_MODE_MASK    0x2000
#define    RTL8370_LED_EEE_LPI_EN_OFFSET    12
#define    RTL8370_LED_EEE_LPI_EN_MASK    0x1000
#define    RTL8370_LED_EEE_LPI_10_OFFSET    11
#define    RTL8370_LED_EEE_LPI_10_MASK    0x800
#define    RTL8370_LED_EEE_CAP_10_OFFSET    10
#define    RTL8370_LED_EEE_CAP_10_MASK    0x400
#define    RTL8370_LED_LPI_SEL_OFFSET    8
#define    RTL8370_LED_LPI_SEL_MASK    0x300
#define    RTL8370_SERI_LED_ACT_LOW_OFFSET    7
#define    RTL8370_SERI_LED_ACT_LOW_MASK    0x80
#define    RTL8370_LED_POWERON_2_OFFSET    6
#define    RTL8370_LED_POWERON_2_MASK    0x40
#define    RTL8370_LED_POWERON_1_OFFSET    5
#define    RTL8370_LED_POWERON_1_MASK    0x20
#define    RTL8370_LED_POWERON_0_OFFSET    4
#define    RTL8370_LED_POWERON_0_MASK    0x10
#define    RTL8370_LED_IO_DISABLE_OFFSET    3
#define    RTL8370_LED_IO_DISABLE_MASK    0x8
#define    RTL8370_SEL_SERIAL_LED_OFFSET    2
#define    RTL8370_SEL_SERIAL_LED_MASK    0x4
#define    RTL8370_LED_SELECT_OFFSET    0
#define    RTL8370_LED_SELECT_MASK    0x3

#define    RTL8370_REG_LED_MODE    0x1b02
#define    RTL8370_RTCT_TEST_TIME_OFFSET    15
#define    RTL8370_RTCT_TEST_TIME_MASK    0x8000
#define    RTL8370_LED_BUZZ_DUTY_OFFSET    14
#define    RTL8370_LED_BUZZ_DUTY_MASK    0x4000
#define    RTL8370_BUZZER_RATE_OFFSET    12
#define    RTL8370_BUZZER_RATE_MASK    0x3000
#define    RTL8370_LOOP_DETECT_MODE_OFFSET    11
#define    RTL8370_LOOP_DETECT_MODE_MASK    0x800
#define    RTL8370_SEL_PWRON_TIME_OFFSET    9
#define    RTL8370_SEL_PWRON_TIME_MASK    0x600
#define    RTL8370_EN_DLINK_LED_OFFSET    8
#define    RTL8370_EN_DLINK_LED_MASK    0x100
#define    RTL8370_LOOP_DETECT_RATE_OFFSET    6
#define    RTL8370_LOOP_DETECT_RATE_MASK    0xC0
#define    RTL8370_FORCE_RATE_OFFSET    4
#define    RTL8370_FORCE_RATE_MASK    0x30
#define    RTL8370_SEL_LEDRATE_OFFSET    1
#define    RTL8370_SEL_LEDRATE_MASK    0xE
#define    RTL8370_SPEED_UP_OFFSET    0
#define    RTL8370_SPEED_UP_MASK    0x1

#define    RTL8370_REG_LED_CONFIGURATION    0x1b03
#define    RTL8370_LED_CONFIGURATION_DUMMY_0_OFFSET    15
#define    RTL8370_LED_CONFIGURATION_DUMMY_0_MASK    0x8000
#define    RTL8370_LED_CONFIG_SEL_OFFSET    14
#define    RTL8370_LED_CONFIG_SEL_MASK    0x4000
#define    RTL8370_DATA_LED_OFFSET    12
#define    RTL8370_DATA_LED_MASK    0x3000
#define    RTL8370_LED2_CFG_OFFSET    8
#define    RTL8370_LED2_CFG_MASK    0xF00
#define    RTL8370_LED1_CFG_OFFSET    4
#define    RTL8370_LED1_CFG_MASK    0xF0
#define    RTL8370_LED0_CFG_OFFSET    0
#define    RTL8370_LED0_CFG_MASK    0xF

#define    RTL8370_REG_RTCT_RESULTS_CFG    0x1b04
#define    RTL8370_RTCT_2PAIR_FTT_OFFSET    15
#define    RTL8370_RTCT_2PAIR_FTT_MASK    0x8000
#define    RTL8370_RTCT_2PAIR_MODE_OFFSET    14
#define    RTL8370_RTCT_2PAIR_MODE_MASK    0x4000
#define    RTL8370_BLINK_EN_OFFSET    13
#define    RTL8370_BLINK_EN_MASK    0x2000
#define    RTL8370_TIMEOUT_OFFSET    12
#define    RTL8370_TIMEOUT_MASK    0x1000
#define    RTL8370_EN_CD_SAME_SHORT_OFFSET    11
#define    RTL8370_EN_CD_SAME_SHORT_MASK    0x800
#define    RTL8370_EN_CD_SAME_OPEN_OFFSET    10
#define    RTL8370_EN_CD_SAME_OPEN_MASK    0x400
#define    RTL8370_EN_CD_SAME_LINEDRIVER_OFFSET    9
#define    RTL8370_EN_CD_SAME_LINEDRIVER_MASK    0x200
#define    RTL8370_EN_CD_SAME_MISMATCH_OFFSET    8
#define    RTL8370_EN_CD_SAME_MISMATCH_MASK    0x100
#define    RTL8370_EN_CD_SHORT_OFFSET    7
#define    RTL8370_EN_CD_SHORT_MASK    0x80
#define    RTL8370_EN_AB_SHORT_OFFSET    6
#define    RTL8370_EN_AB_SHORT_MASK    0x40
#define    RTL8370_EN_CD_OPEN_OFFSET    5
#define    RTL8370_EN_CD_OPEN_MASK    0x20
#define    RTL8370_EN_AB_OPEN_OFFSET    4
#define    RTL8370_EN_AB_OPEN_MASK    0x10
#define    RTL8370_EN_CD_MISMATCH_OFFSET    3
#define    RTL8370_EN_CD_MISMATCH_MASK    0x8
#define    RTL8370_EN_AB_MISMATCH_OFFSET    2
#define    RTL8370_EN_AB_MISMATCH_MASK    0x4
#define    RTL8370_EN_CD_LINEDRIVER_OFFSET    1
#define    RTL8370_EN_CD_LINEDRIVER_MASK    0x2
#define    RTL8370_EN_AB_LINEDRIVER_OFFSET    0
#define    RTL8370_EN_AB_LINEDRIVER_MASK    0x1

#define    RTL8370_REG_RTCT_LED    0x1b05
#define    RTL8370_RTCT_LED_DUMMY_0_OFFSET    12
#define    RTL8370_RTCT_LED_DUMMY_0_MASK    0xF000
#define    RTL8370_RTCT_LED2_OFFSET    8
#define    RTL8370_RTCT_LED2_MASK    0xF00
#define    RTL8370_RTCT_LED1_OFFSET    4
#define    RTL8370_RTCT_LED1_MASK    0xF0
#define    RTL8370_RTCT_LED0_OFFSET    0
#define    RTL8370_RTCT_LED0_MASK    0xF

#define    RTL8370_REG_CPU_FORCE_LED_CFG    0x1b07
#define    RTL8370_CPU_FORCE_LED_CFG_DUMMY_0_OFFSET    8
#define    RTL8370_CPU_FORCE_LED_CFG_DUMMY_0_MASK    0xFF00
#define    RTL8370_LED_FORCE_MODE_OFFSET    2
#define    RTL8370_LED_FORCE_MODE_MASK    0xFC
#define    RTL8370_FORCE_MODE_OFFSET    0
#define    RTL8370_FORCE_MODE_MASK    0x3

#define    RTL8370_REG_CPU_FORCE_LED0_CFG0    0x1b08
#define    RTL8370_PORT7_LED0_MODE_OFFSET    14
#define    RTL8370_PORT7_LED0_MODE_MASK    0xC000
#define    RTL8370_PORT6_LED0_MODE_OFFSET    12
#define    RTL8370_PORT6_LED0_MODE_MASK    0x3000
#define    RTL8370_PORT5_LED0_MODE_OFFSET    10
#define    RTL8370_PORT5_LED0_MODE_MASK    0xC00
#define    RTL8370_PORT4_LED0_MODE_OFFSET    8
#define    RTL8370_PORT4_LED0_MODE_MASK    0x300
#define    RTL8370_PORT3_LED0_MODE_OFFSET    6
#define    RTL8370_PORT3_LED0_MODE_MASK    0xC0
#define    RTL8370_PORT2_LED0_MODE_OFFSET    4
#define    RTL8370_PORT2_LED0_MODE_MASK    0x30
#define    RTL8370_PORT1_LED0_MODE_OFFSET    2
#define    RTL8370_PORT1_LED0_MODE_MASK    0xC
#define    RTL8370_PORT0_LED0_MODE_OFFSET    0
#define    RTL8370_PORT0_LED0_MODE_MASK    0x3

#define    RTL8370_REG_CPU_FORCE_LED0_CFG1    0x1b09
#define    RTL8370_PORT15_LED0_MODE_OFFSET    14
#define    RTL8370_PORT15_LED0_MODE_MASK    0xC000
#define    RTL8370_PORT14_LED0_MODE_OFFSET    12
#define    RTL8370_PORT14_LED0_MODE_MASK    0x3000
#define    RTL8370_PORT13_LED0_MODE_OFFSET    10
#define    RTL8370_PORT13_LED0_MODE_MASK    0xC00
#define    RTL8370_PORT12_LED0_MODE_OFFSET    8
#define    RTL8370_PORT12_LED0_MODE_MASK    0x300
#define    RTL8370_PORT11_LED0_MODE_OFFSET    6
#define    RTL8370_PORT11_LED0_MODE_MASK    0xC0
#define    RTL8370_PORT10_LED0_MODE_OFFSET    4
#define    RTL8370_PORT10_LED0_MODE_MASK    0x30
#define    RTL8370_PORT9_LED0_MODE_OFFSET    2
#define    RTL8370_PORT9_LED0_MODE_MASK    0xC
#define    RTL8370_PORT8_LED0_MODE_OFFSET    0
#define    RTL8370_PORT8_LED0_MODE_MASK    0x3

#define    RTL8370_REG_CPU_FORCE_LED1_CFG0    0x1b0a
#define    RTL8370_PORT7_LED1_MODE_OFFSET    14
#define    RTL8370_PORT7_LED1_MODE_MASK    0xC000
#define    RTL8370_PORT6_LED1_MODE_OFFSET    12
#define    RTL8370_PORT6_LED1_MODE_MASK    0x3000
#define    RTL8370_PORT5_LED1_MODE_OFFSET    10
#define    RTL8370_PORT5_LED1_MODE_MASK    0xC00
#define    RTL8370_PORT4_LED1_MODE_OFFSET    8
#define    RTL8370_PORT4_LED1_MODE_MASK    0x300
#define    RTL8370_PORT3_LED1_MODE_OFFSET    6
#define    RTL8370_PORT3_LED1_MODE_MASK    0xC0
#define    RTL8370_PORT2_LED1_MODE_OFFSET    4
#define    RTL8370_PORT2_LED1_MODE_MASK    0x30
#define    RTL8370_PORT1_LED1_MODE_OFFSET    2
#define    RTL8370_PORT1_LED1_MODE_MASK    0xC
#define    RTL8370_PORT0_LED1_MODE_OFFSET    0
#define    RTL8370_PORT0_LED1_MODE_MASK    0x3

#define    RTL8370_REG_CPU_FORCE_LED1_CFG1    0x1b0b
#define    RTL8370_PORT15_LED1_MODE_OFFSET    14
#define    RTL8370_PORT15_LED1_MODE_MASK    0xC000
#define    RTL8370_PORT14_LED1_MODE_OFFSET    12
#define    RTL8370_PORT14_LED1_MODE_MASK    0x3000
#define    RTL8370_PORT13_LED1_MODE_OFFSET    10
#define    RTL8370_PORT13_LED1_MODE_MASK    0xC00
#define    RTL8370_PORT12_LED1_MODE_OFFSET    8
#define    RTL8370_PORT12_LED1_MODE_MASK    0x300
#define    RTL8370_PORT11_LED1_MODE_OFFSET    6
#define    RTL8370_PORT11_LED1_MODE_MASK    0xC0
#define    RTL8370_PORT10_LED1_MODE_OFFSET    4
#define    RTL8370_PORT10_LED1_MODE_MASK    0x30
#define    RTL8370_PORT9_LED1_MODE_OFFSET    2
#define    RTL8370_PORT9_LED1_MODE_MASK    0xC
#define    RTL8370_PORT8_LED1_MODE_OFFSET    0
#define    RTL8370_PORT8_LED1_MODE_MASK    0x3

#define    RTL8370_REG_CPU_FORCE_LED2_CFG0    0x1b0c
#define    RTL8370_PORT7_LED2_MODE_OFFSET    14
#define    RTL8370_PORT7_LED2_MODE_MASK    0xC000
#define    RTL8370_PORT6_LED2_MODE_OFFSET    12
#define    RTL8370_PORT6_LED2_MODE_MASK    0x3000
#define    RTL8370_PORT5_LED2_MODE_OFFSET    10
#define    RTL8370_PORT5_LED2_MODE_MASK    0xC00
#define    RTL8370_PORT4_LED2_MODE_OFFSET    8
#define    RTL8370_PORT4_LED2_MODE_MASK    0x300
#define    RTL8370_PORT3_LED2_MODE_OFFSET    6
#define    RTL8370_PORT3_LED2_MODE_MASK    0xC0
#define    RTL8370_PORT2_LED2_MODE_OFFSET    4
#define    RTL8370_PORT2_LED2_MODE_MASK    0x30
#define    RTL8370_PORT1_LED2_MODE_OFFSET    2
#define    RTL8370_PORT1_LED2_MODE_MASK    0xC
#define    RTL8370_PORT0_LED2_MODE_OFFSET    0
#define    RTL8370_PORT0_LED2_MODE_MASK    0x3

#define    RTL8370_REG_CPU_FORCE_LED2_CFG1    0x1b0d
#define    RTL8370_PORT15_LED2_MODE_OFFSET    14
#define    RTL8370_PORT15_LED2_MODE_MASK    0xC000
#define    RTL8370_PORT14_LED2_MODE_OFFSET    12
#define    RTL8370_PORT14_LED2_MODE_MASK    0x3000
#define    RTL8370_PORT13_LED2_MODE_OFFSET    10
#define    RTL8370_PORT13_LED2_MODE_MASK    0xC00
#define    RTL8370_PORT12_LED2_MODE_OFFSET    8
#define    RTL8370_PORT12_LED2_MODE_MASK    0x300
#define    RTL8370_PORT11_LED2_MODE_OFFSET    6
#define    RTL8370_PORT11_LED2_MODE_MASK    0xC0
#define    RTL8370_PORT10_LED2_MODE_OFFSET    4
#define    RTL8370_PORT10_LED2_MODE_MASK    0x30
#define    RTL8370_PORT9_LED2_MODE_OFFSET    2
#define    RTL8370_PORT9_LED2_MODE_MASK    0xC
#define    RTL8370_PORT8_LED2_MODE_OFFSET    0
#define    RTL8370_PORT8_LED2_MODE_MASK    0x3

#define    RTL8370_REG_LED_ACTIVE_LOW_CFG0    0x1b0e
#define    RTL8370_LED_ACTIVE_LOW_CFG0_DUMMY_0_OFFSET    15
#define    RTL8370_LED_ACTIVE_LOW_CFG0_DUMMY_0_MASK    0x8000
#define    RTL8370_PORT3_LED_ACTIVE_LOW_OFFSET    12
#define    RTL8370_PORT3_LED_ACTIVE_LOW_MASK    0x7000
#define    RTL8370_LED_ACTIVE_LOW_CFG0_DUMMY_1_OFFSET    11
#define    RTL8370_LED_ACTIVE_LOW_CFG0_DUMMY_1_MASK    0x800
#define    RTL8370_PORT2_LED_ACTIVE_LOW_OFFSET    8
#define    RTL8370_PORT2_LED_ACTIVE_LOW_MASK    0x700
#define    RTL8370_LED_ACTIVE_LOW_CFG0_DUMMY_2_OFFSET    7
#define    RTL8370_LED_ACTIVE_LOW_CFG0_DUMMY_2_MASK    0x80
#define    RTL8370_PORT1_LED_ACTIVE_LOW_OFFSET    4
#define    RTL8370_PORT1_LED_ACTIVE_LOW_MASK    0x70
#define    RTL8370_LED_ACTIVE_LOW_CFG0_DUMMY_3_OFFSET    3
#define    RTL8370_LED_ACTIVE_LOW_CFG0_DUMMY_3_MASK    0x8
#define    RTL8370_PORT0_LED_ACTIVE_LOW_OFFSET    0
#define    RTL8370_PORT0_LED_ACTIVE_LOW_MASK    0x7

#define    RTL8370_REG_LED_ACTIVE_LOW_CFG1    0x1b0f
#define    RTL8370_LED_ACTIVE_LOW_CFG1_DUMMY_0_OFFSET    15
#define    RTL8370_LED_ACTIVE_LOW_CFG1_DUMMY_0_MASK    0x8000
#define    RTL8370_PORT7_LED_ACTIVE_LOW_OFFSET    12
#define    RTL8370_PORT7_LED_ACTIVE_LOW_MASK    0x7000
#define    RTL8370_LED_ACTIVE_LOW_CFG1_DUMMY_1_OFFSET    11
#define    RTL8370_LED_ACTIVE_LOW_CFG1_DUMMY_1_MASK    0x800
#define    RTL8370_PORT6_LED_ACTIVE_LOW_OFFSET    8
#define    RTL8370_PORT6_LED_ACTIVE_LOW_MASK    0x700
#define    RTL8370_LED_ACTIVE_LOW_CFG1_DUMMY_2_OFFSET    7
#define    RTL8370_LED_ACTIVE_LOW_CFG1_DUMMY_2_MASK    0x80
#define    RTL8370_PORT5_LED_ACTIVE_LOW_OFFSET    4
#define    RTL8370_PORT5_LED_ACTIVE_LOW_MASK    0x70
#define    RTL8370_LED_ACTIVE_LOW_CFG1_DUMMY_3_OFFSET    3
#define    RTL8370_LED_ACTIVE_LOW_CFG1_DUMMY_3_MASK    0x8
#define    RTL8370_PORT4_LED_ACTIVE_LOW_OFFSET    0
#define    RTL8370_PORT4_LED_ACTIVE_LOW_MASK    0x7

#define    RTL8370_REG_EXT_LED    0x1b10
#define    RTL8370_EXT_LED_NUMBER_OFFSET    9
#define    RTL8370_EXT_LED_NUMBER_MASK    0xFE00
#define    RTL8370_EXT_LED_SCAN_OFFSET    8
#define    RTL8370_EXT_LED_SCAN_MASK    0x100
#define    RTL8370_EXT_LED_HALT_OFFSET    7
#define    RTL8370_EXT_LED_HALT_MASK    0x80
#define    RTL8370_EXT_LED_INITIAL_EN_OFFSET    6
#define    RTL8370_EXT_LED_INITIAL_EN_MASK    0x40
#define    RTL8370_EXT_LED_EN_OFFSET    5
#define    RTL8370_EXT_LED_EN_MASK    0x20
#define    RTL8370_EXT_LED_AD_OFFSET    0
#define    RTL8370_EXT_LED_AD_MASK    0x1F

#define    RTL8370_REG_EXT_BUZZER    0x1b11
#define    RTL8370_EXT_BUZZER_DUMMY_0_OFFSET    13
#define    RTL8370_EXT_BUZZER_DUMMY_0_MASK    0xE000
#define    RTL8370_BYPASS_EXTLED_INIT_OFFSET    12
#define    RTL8370_BYPASS_EXTLED_INIT_MASK    0x1000
#define    RTL8370_DO_INITIAL_EXTLED_OFFSET    11
#define    RTL8370_DO_INITIAL_EXTLED_MASK    0x800
#define    RTL8370_LED_COLOR_OFFSET    10
#define    RTL8370_LED_COLOR_MASK    0x400
#define    RTL8370_DEBOUNCING_OFFSET    4
#define    RTL8370_DEBOUNCING_MASK    0x3F0
#define    RTL8370_EXT_BUZZER_EN_OFFSET    3
#define    RTL8370_EXT_BUZZER_EN_MASK    0x8
#define    RTL8370_EXT_BUZZER_FREQUENCE_OFFSET    0
#define    RTL8370_EXT_BUZZER_FREQUENCE_MASK    0x7

#define    RTL8370_REG_EXT_GPIO_ENABLE_CTRL0    0x1b12

#define    RTL8370_REG_EXT_GPIO_ENABLE_CTRL1    0x1b13

#define    RTL8370_REG_EXT_GPIO_ENABLE_CTRL2    0x1b14
#define    RTL8370_EXT_GPIO_ENABLE_CTRL2_DUMMY_0_OFFSET    5
#define    RTL8370_EXT_GPIO_ENABLE_CTRL2_DUMMY_0_MASK    0xFFE0
#define    RTL8370_EXT_GPIO_ENABLE_CTRL2_OFFSET    0
#define    RTL8370_EXT_GPIO_ENABLE_CTRL2_MASK    0x1F

#define    RTL8370_REG_EXT_GPI_CTRL0    0x1b15

#define    RTL8370_REG_EXT_GPI_CTRL1    0x1b16

#define    RTL8370_REG_EXT_GPI_CTRL2    0x1b17
#define    RTL8370_EXT_GPI_CTRL2_DUMMY_0_OFFSET    5
#define    RTL8370_EXT_GPI_CTRL2_DUMMY_0_MASK    0xFFE0
#define    RTL8370_EXT_GPI_CTRL2_OFFSET    0
#define    RTL8370_EXT_GPI_CTRL2_MASK    0x1F

#define    RTL8370_REG_EXT_GPIO_INVERT_CTRL0    0x1b18

#define    RTL8370_REG_EXT_GPIO_INVERT_CTRL1    0x1b19

#define    RTL8370_REG_EXT_GPIO_INVERT_CTRL2    0x1b1a
#define    RTL8370_EXT_GPIO_INVERT_CTRL2_DUMMY_0_OFFSET    5
#define    RTL8370_EXT_GPIO_INVERT_CTRL2_DUMMY_0_MASK    0xFFE0
#define    RTL8370_EXT_GPIO_INVERT_CTRL2_OFFSET    0
#define    RTL8370_EXT_GPIO_INVERT_CTRL2_MASK    0x1F

#define    RTL8370_REG_EXT_LED_GPI_STATUS0    0x1b1b

#define    RTL8370_REG_EXT_LED_GPI_STATUS1    0x1b1c

#define    RTL8370_REG_EXT_LED_CTRL    0x1b1d
#define    RTL8370_EXT_LED_GPI_BUSY_OFFSET    15
#define    RTL8370_EXT_LED_GPI_BUSY_MASK    0x8000
#define    RTL8370_EXT_LED_INITIAL_STATUS_OFFSET    14
#define    RTL8370_EXT_LED_INITIAL_STATUS_MASK    0x4000
#define    RTL8370_EXT_LED_CTRL_DUMMY_0_OFFSET    5
#define    RTL8370_EXT_LED_CTRL_DUMMY_0_MASK    0x3FE0
#define    RTL8370_EXT_LED_GPI_STATUS2_OFFSET    0
#define    RTL8370_EXT_LED_GPI_STATUS2_MASK    0x1F

#define    RTL8370_REG_EXT_LED_GPO_CTRL0    0x1b1e

#define    RTL8370_REG_EXT_LED_GPO_CTRL1    0x1b1f

#define    RTL8370_REG_EXT_LED_GPO_CTRL2    0x1b20
#define    RTL8370_EXT_LED_GPO_CTRL2_DUMMY_0_OFFSET    5
#define    RTL8370_EXT_LED_GPO_CTRL2_DUMMY_0_MASK    0xFFE0
#define    RTL8370_EXT_LED_GPO_CTRL2_OFFSET    0
#define    RTL8370_EXT_LED_GPO_CTRL2_MASK    0x1F

#define    RTL8370_REG_SEL_RTCT_PARA    0x1b21
#define    RTL8370_DO_RTCT_COMMAND_OFFSET    15
#define    RTL8370_DO_RTCT_COMMAND_MASK    0x8000
#define    RTL8370_SEL_RTCT_PARA_DUMMY_0_OFFSET    14
#define    RTL8370_SEL_RTCT_PARA_DUMMY_0_MASK    0x4000
#define    RTL8370_SEL_RTCT_PHASE_OFFSET    12
#define    RTL8370_SEL_RTCT_PHASE_MASK    0x3000
#define    RTL8370_SEL_RTCT_RLSTLED_TIME_OFFSET    10
#define    RTL8370_SEL_RTCT_RLSTLED_TIME_MASK    0xC00
#define    RTL8370_SEL_RTCT_TEST_LED_TIME_OFFSET    8
#define    RTL8370_SEL_RTCT_TEST_LED_TIME_MASK    0x300
#define    RTL8370_EN_SCAN_RTCT_OFFSET    7
#define    RTL8370_EN_SCAN_RTCT_MASK    0x80
#define    RTL8370_EN_RTCT_TIMOUT_OFFSET    6
#define    RTL8370_EN_RTCT_TIMOUT_MASK    0x40
#define    RTL8370_EN_ALL_RTCT_OFFSET    5
#define    RTL8370_EN_ALL_RTCT_MASK    0x20
#define    RTL8370_SEL_RTCT_PLE_WID_OFFSET    0
#define    RTL8370_SEL_RTCT_PLE_WID_MASK    0x1F

#define    RTL8370_REG_RTCT_ENABLE    0x1b22

#define    RTL8370_REG_RTCT_TIMEOUT    0x1b23

#define    RTL8370_REG_PARA_LED_IO_EN1    0x1b24
#define    RTL8370_LED1_PARA_P07_00_OFFSET    8
#define    RTL8370_LED1_PARA_P07_00_MASK    0xFF00
#define    RTL8370_LED0_PARA_P07_00_OFFSET    0
#define    RTL8370_LED0_PARA_P07_00_MASK    0xFF

#define    RTL8370_REG_PARA_LED_IO_EN2    0x1b25
#define    RTL8370_PARA_LED_IO_EN2_DUMMY_0_OFFSET    8
#define    RTL8370_PARA_LED_IO_EN2_DUMMY_0_MASK    0xFF00
#define    RTL8370_LED2_PARA_P07_00_OFFSET    0
#define    RTL8370_LED2_PARA_P07_00_MASK    0xFF

#define    RTL8370_REG_SCAN0_LED_IO_EN    0x1b26
#define    RTL8370_LED_SCAN0_BI_PORT_EN_OFFSET    8
#define    RTL8370_LED_SCAN0_BI_PORT_EN_MASK    0xFF00
#define    RTL8370_LED_SCAN0_BI_STA_EN_OFFSET    5
#define    RTL8370_LED_SCAN0_BI_STA_EN_MASK    0xE0
#define    RTL8370_SCAN0_LED_IO_EN_DUMMY_0_OFFSET    3
#define    RTL8370_SCAN0_LED_IO_EN_DUMMY_0_MASK    0x18
#define    RTL8370_LED_LOOP_DET_BUZZER_EN_OFFSET    2
#define    RTL8370_LED_LOOP_DET_BUZZER_EN_MASK    0x4
#define    RTL8370_LED_SERI_DATA_EN_OFFSET    1
#define    RTL8370_LED_SERI_DATA_EN_MASK    0x2
#define    RTL8370_LED_SERI_CLK_EN_OFFSET    0
#define    RTL8370_LED_SERI_CLK_EN_MASK    0x1

#define    RTL8370_REG_SCAN1_LED_IO_EN    0x1b27
#define    RTL8370_LED_SCAN1_BI_PORT_EN_OFFSET    8
#define    RTL8370_LED_SCAN1_BI_PORT_EN_MASK    0xFF00
#define    RTL8370_LED_SCAN1_BI_STA_EN_OFFSET    7
#define    RTL8370_LED_SCAN1_BI_STA_EN_MASK    0x80
#define    RTL8370_SCAN1_LED_IO_EN_DUMMY_0_OFFSET    6
#define    RTL8370_SCAN1_LED_IO_EN_DUMMY_0_MASK    0x40
#define    RTL8370_LED_SCAN1_SI_PORT_EN_OFFSET    2
#define    RTL8370_LED_SCAN1_SI_PORT_EN_MASK    0x3C
#define    RTL8370_LED_SCAN1_SI_STA_EN_OFFSET    0
#define    RTL8370_LED_SCAN1_SI_STA_EN_MASK    0x3

#define    RTL8370_REG_LPI_LED_OPT1    0x1b28
#define    RTL8370_LPI_TAG4_OFFSET    12
#define    RTL8370_LPI_TAG4_MASK    0xF000
#define    RTL8370_LPI_TAG3_OFFSET    8
#define    RTL8370_LPI_TAG3_MASK    0xF00
#define    RTL8370_LPI_TAG2_OFFSET    4
#define    RTL8370_LPI_TAG2_MASK    0xF0
#define    RTL8370_LPI_TAG1_OFFSET    0
#define    RTL8370_LPI_TAG1_MASK    0xF

#define    RTL8370_REG_LPI_LED_OPT2    0x1b29
#define    RTL8370_LPI_LED_OPT2_DUMMY_0_OFFSET    15
#define    RTL8370_LPI_LED_OPT2_DUMMY_0_MASK    0x8000
#define    RTL8370_LPI_LED2_WEAK_OFFSET    14
#define    RTL8370_LPI_LED2_WEAK_MASK    0x4000
#define    RTL8370_LPI_LED1_WEAK_OFFSET    13
#define    RTL8370_LPI_LED1_WEAK_MASK    0x2000
#define    RTL8370_LPI_LED0_WEAK_OFFSET    12
#define    RTL8370_LPI_LED0_WEAK_MASK    0x1000
#define    RTL8370_LPI_LED2_OFFSET    11
#define    RTL8370_LPI_LED2_MASK    0x800
#define    RTL8370_LPI_LED1_OFFSET    10
#define    RTL8370_LPI_LED1_MASK    0x400
#define    RTL8370_LPI_LED0_OFFSET    9
#define    RTL8370_LPI_LED0_MASK    0x200
#define    RTL8370_LPI_TAG8_OFFSET    8
#define    RTL8370_LPI_TAG8_MASK    0x100
#define    RTL8370_LPI_TAG7_OFFSET    6
#define    RTL8370_LPI_TAG7_MASK    0xC0
#define    RTL8370_LPI_TAG6_OFFSET    4
#define    RTL8370_LPI_TAG6_MASK    0x30
#define    RTL8370_LPI_TAG5_OFFSET    0
#define    RTL8370_LPI_TAG5_MASK    0xF

/* (16'h1f00) patch_reg */

#define    RTL8370_REG_INDRECT_ACCESS_CRTL    0x1f00
#define    RTL8370_RW_OFFSET    1
#define    RTL8370_RW_MASK    0x2
#define    RTL8370_CMD_OFFSET    0
#define    RTL8370_CMD_MASK    0x1

#define    RTL8370_REG_INDRECT_ACCESS_STATUS    0x1f01
#define    RTL8370_PHY_BUSY_OFFSET    2
#define    RTL8370_PHY_BUSY_MASK    0x4
#define    RTL8370_SDS_BUSY_OFFSET    1
#define    RTL8370_SDS_BUSY_MASK    0x2
#define    RTL8370_MDX_BUSY_OFFSET    0
#define    RTL8370_MDX_BUSY_MASK    0x1

#define    RTL8370_REG_INDRECT_ACCESS_ADDRESS    0x1f02

#define    RTL8370_REG_INDRECT_ACCESS_WRITE_DATA    0x1f03

#define    RTL8370_REG_INDRECT_ACCESS_READ_DATA    0x1f04

#define    RTL8370_REG_INDRECT_ACCESS_DELAY    0x1f80

#define    RTL8370_REG_INDRECT_ACCESS_BURST    0x1f81

/* (16'h6000)Serdes */

#define    RTL8370_REG_SDS0_REG0    0x6240
#define    RTL8370_SDS0_REG0_sds_frc_rx_OFFSET    12
#define    RTL8370_SDS0_REG0_sds_frc_rx_MASK    0xF000
#define    RTL8370_SDS0_REG0_sds_frc_tx_OFFSET    8
#define    RTL8370_SDS0_REG0_sds_frc_tx_MASK    0xF00
#define    RTL8370_SDS0_REG0_dis_apx_OFFSET    7
#define    RTL8370_SDS0_REG0_dis_apx_MASK    0x80
#define    RTL8370_SDS0_REG0_soft_rst_OFFSET    6
#define    RTL8370_SDS0_REG0_soft_rst_MASK    0x40
#define    RTL8370_SDS0_REG0_inv_hsi_OFFSET    5
#define    RTL8370_SDS0_REG0_inv_hsi_MASK    0x20
#define    RTL8370_SDS0_REG0_inv_hso_OFFSET    4
#define    RTL8370_SDS0_REG0_inv_hso_MASK    0x10
#define    RTL8370_SDS0_REG0_mark_carr_ext_OFFSET    3
#define    RTL8370_SDS0_REG0_mark_carr_ext_MASK    0x8
#define    RTL8370_SDS0_REG0_codec_lpk_OFFSET    2
#define    RTL8370_SDS0_REG0_codec_lpk_MASK    0x4
#define    RTL8370_SDS0_REG0_afe_lpk_OFFSET    1
#define    RTL8370_SDS0_REG0_afe_lpk_MASK    0x2
#define    RTL8370_SDS0_REG0_remote_lpk_OFFSET    0
#define    RTL8370_SDS0_REG0_remote_lpk_MASK    0x1

#define    RTL8370_REG_SDS0_REG1    0x6241
#define    RTL8370_SDS0_REG1_ability_OFFSET    12
#define    RTL8370_SDS0_REG1_ability_MASK    0xF000
#define    RTL8370_SDS0_REG1_sds_restart_an_OFFSET    8
#define    RTL8370_SDS0_REG1_sds_restart_an_MASK    0xF00
#define    RTL8370_SDS0_REG1_sds_tx_down_OFFSET    7
#define    RTL8370_SDS0_REG1_sds_tx_down_MASK    0x80
#define    RTL8370_SDS0_REG1_send_np_on_OFFSET    6
#define    RTL8370_SDS0_REG1_send_np_on_MASK    0x40
#define    RTL8370_SDS0_REG1_sds_frc_an_OFFSET    4
#define    RTL8370_SDS0_REG1_sds_frc_an_MASK    0x30
#define    RTL8370_SDS0_REG1_frc_cggood_OFFSET    2
#define    RTL8370_SDS0_REG1_frc_cggood_MASK    0xC
#define    RTL8370_SDS0_REG1_cdet_OFFSET    0
#define    RTL8370_SDS0_REG1_cdet_MASK    0x3

#define    RTL8370_REG_SDS0_REG2    0x6242
#define    RTL8370_SDS0_REG2_frc_preamble_OFFSET    14
#define    RTL8370_SDS0_REG2_frc_preamble_MASK    0xC000
#define    RTL8370_SDS0_REG2_frc_ipg_OFFSET    12
#define    RTL8370_SDS0_REG2_frc_ipg_MASK    0x3000
#define    RTL8370_SDS0_REG2_sds_en_rx_OFFSET    11
#define    RTL8370_SDS0_REG2_sds_en_rx_MASK    0x800
#define    RTL8370_SDS0_REG2_sds_en_tx_OFFSET    10
#define    RTL8370_SDS0_REG2_sds_en_tx_MASK    0x400
#define    RTL8370_SDS0_REG2_sd_det_algor_OFFSET    9
#define    RTL8370_SDS0_REG2_sd_det_algor_MASK    0x200
#define    RTL8370_SDS0_REG2_auto_det_algor_OFFSET    8
#define    RTL8370_SDS0_REG2_auto_det_algor_MASK    0x100
#define    RTL8370_SDS0_REG2_rdm_algor_OFFSET    7
#define    RTL8370_SDS0_REG2_rdm_algor_MASK    0x80
#define    RTL8370_SDS0_REG2_byp_8b10b_OFFSET    6
#define    RTL8370_SDS0_REG2_byp_8b10b_MASK    0x40
#define    RTL8370_SDS0_REG2_dis_tmr_cma_OFFSET    5
#define    RTL8370_SDS0_REG2_dis_tmr_cma_MASK    0x20
#define    RTL8370_SDS0_REG2_cma_rq_OFFSET    0
#define    RTL8370_SDS0_REG2_cma_rq_MASK    0x1F

#define    RTL8370_REG_SDS0_REG3    0x6243
#define    RTL8370_SDS0_REG3_sds_lk_time_OFFSET    8
#define    RTL8370_SDS0_REG3_sds_lk_time_MASK    0xFF00
#define    RTL8370_SDS0_REG3_apxt_time_OFFSET    0
#define    RTL8370_SDS0_REG3_apxt_time_MASK    0xFF

#define    RTL8370_REG_SDS0_REG4    0x6244
#define    RTL8370_SDS0_REG4_wr_soft_rstb_OFFSET    15
#define    RTL8370_SDS0_REG4_wr_soft_rstb_MASK    0x8000
#define    RTL8370_SDS0_REG4_dbg_sts_sel_OFFSET    12
#define    RTL8370_SDS0_REG4_dbg_sts_sel_MASK    0x7000
#define    RTL8370_SDS0_REG4_reg_calib_ok_cnt_OFFSET    8
#define    RTL8370_SDS0_REG4_reg_calib_ok_cnt_MASK    0xF00
#define    RTL8370_SDS0_REG4_reg_pcsreq_pos_OFFSET    7
#define    RTL8370_SDS0_REG4_reg_pcsreq_pos_MASK    0x80
#define    RTL8370_SDS0_REG4_reg_mark_scr_OFFSET    6
#define    RTL8370_SDS0_REG4_reg_mark_scr_MASK    0x40
#define    RTL8370_SDS0_REG4_disan_link_sgm_OFFSET    5
#define    RTL8370_SDS0_REG4_disan_link_sgm_MASK    0x20
#define    RTL8370_SDS0_REG4_disan_link_fib_OFFSET    4
#define    RTL8370_SDS0_REG4_disan_link_fib_MASK    0x10
#define    RTL8370_SDS0_REG4_sgmii_ck_sel_OFFSET    3
#define    RTL8370_SDS0_REG4_sgmii_ck_sel_MASK    0x8
#define    RTL8370_SDS0_REG4_clr_soft_rstb_OFFSET    2
#define    RTL8370_SDS0_REG4_clr_soft_rstb_MASK    0x4
#define    RTL8370_SDS0_REG4_sel_deg_OFFSET    1
#define    RTL8370_SDS0_REG4_sel_deg_MASK    0x2
#define    RTL8370_SDS0_REG4_dis_renway_OFFSET    0
#define    RTL8370_SDS0_REG4_dis_renway_MASK    0x1

#define    RTL8370_REG_SDS0_REG5    0x6245
#define    RTL8370_SDS0_REG5_reg_pwrsv_ctrl_sel_OFFSET    15
#define    RTL8370_SDS0_REG5_reg_pwrsv_ctrl_sel_MASK    0x8000
#define    RTL8370_SDS0_REG5_reg_eee_sds_an_OFFSET    14
#define    RTL8370_SDS0_REG5_reg_eee_sds_an_MASK    0x4000
#define    RTL8370_SDS0_REG5_reg_c3_timer_OFFSET    11
#define    RTL8370_SDS0_REG5_reg_c3_timer_MASK    0x3800
#define    RTL8370_SDS0_REG5_reg_c2_timer_OFFSET    8
#define    RTL8370_SDS0_REG5_reg_c2_timer_MASK    0x700
#define    RTL8370_SDS0_REG5_reg_c1_timer_OFFSET    5
#define    RTL8370_SDS0_REG5_reg_c1_timer_MASK    0xE0
#define    RTL8370_SDS0_REG5_reg_c0_timer_OFFSET    2
#define    RTL8370_SDS0_REG5_reg_c0_timer_MASK    0x1C
#define    RTL8370_SDS0_REG5_reg_c2_pwrsav_en_OFFSET    1
#define    RTL8370_SDS0_REG5_reg_c2_pwrsav_en_MASK    0x2
#define    RTL8370_SDS0_REG5_reg_c1_pwrsav_en_OFFSET    0
#define    RTL8370_SDS0_REG5_reg_c1_pwrsav_en_MASK    0x1

#define    RTL8370_REG_SDS0_REG6    0x6246
#define    RTL8370_SDS0_REG6_eee_program_c3_OFFSET    15
#define    RTL8370_SDS0_REG6_eee_program_c3_MASK    0x8000
#define    RTL8370_SDS0_REG6_eee_program_c2_OFFSET    14
#define    RTL8370_SDS0_REG6_eee_program_c2_MASK    0x4000
#define    RTL8370_SDS0_REG6_eee_program_c1_OFFSET    13
#define    RTL8370_SDS0_REG6_eee_program_c1_MASK    0x2000
#define    RTL8370_SDS0_REG6_eee_program_c0_OFFSET    12
#define    RTL8370_SDS0_REG6_eee_program_c0_MASK    0x1000
#define    RTL8370_SDS0_REG6_eee_program_5_OFFSET    10
#define    RTL8370_SDS0_REG6_eee_program_5_MASK    0xC00
#define    RTL8370_SDS0_REG6_eee_program_4_OFFSET    8
#define    RTL8370_SDS0_REG6_eee_program_4_MASK    0x300
#define    RTL8370_SDS0_REG6_eee_program_3_OFFSET    6
#define    RTL8370_SDS0_REG6_eee_program_3_MASK    0xC0
#define    RTL8370_SDS0_REG6_eee_program_2_OFFSET    4
#define    RTL8370_SDS0_REG6_eee_program_2_MASK    0x30
#define    RTL8370_SDS0_REG6_eee_program_1_OFFSET    2
#define    RTL8370_SDS0_REG6_eee_program_1_MASK    0xC
#define    RTL8370_SDS0_REG6_eee_program_0_OFFSET    0
#define    RTL8370_SDS0_REG6_eee_program_0_MASK    0x3

#define    RTL8370_REG_SDS0_REG7    0x6247
#define    RTL8370_SDS0_REG7_byp_start_OFFSET    12
#define    RTL8370_SDS0_REG7_byp_start_MASK    0xF000
#define    RTL8370_SDS0_REG7_byp_end_OFFSET    8
#define    RTL8370_SDS0_REG7_byp_end_MASK    0xF00
#define    RTL8370_SDS0_REG7_tx_bypscr_OFFSET    4
#define    RTL8370_SDS0_REG7_tx_bypscr_MASK    0xF0
#define    RTL8370_SDS0_REG7_rx_bypscr_OFFSET    0
#define    RTL8370_SDS0_REG7_rx_bypscr_MASK    0xF

#define    RTL8370_REG_SDS0_REG8    0x6248

#define    RTL8370_REG_SDS0_REG9    0x6249

#define    RTL8370_REG_SDS0_REG10    0x624a

#define    RTL8370_REG_SDS0_REG11    0x624b

#define    RTL8370_REG_SDS0_REG12    0x624c

#define    RTL8370_REG_SDS0_REG13    0x624d

#define    RTL8370_REG_SDS0_REG14    0x624e
#define    RTL8370_cfg_afe_spd5g_OFFSET    13
#define    RTL8370_cfg_afe_spd5g_MASK    0xE000
#define    RTL8370_SDS0_REG14_ana_rg0x_OFFSET    8
#define    RTL8370_SDS0_REG14_ana_rg0x_MASK    0x1F00
#define    RTL8370_cfg_afe_rst_biterr_OFFSET    7
#define    RTL8370_cfg_afe_rst_biterr_MASK    0x80
#define    RTL8370_REG_BG_OFFSET    5
#define    RTL8370_REG_BG_MASK    0x60
#define    RTL8370_SDS0_REG14_CLKREQB_OFFSET    3
#define    RTL8370_SDS0_REG14_CLKREQB_MASK    0x8
#define    RTL8370_SDS0_REG14_PDOWN_OFFSET    2
#define    RTL8370_SDS0_REG14_PDOWN_MASK    0x4
#define    RTL8370_SDS0_REG14_RX_EN_OFFSET    1
#define    RTL8370_SDS0_REG14_RX_EN_MASK    0x2
#define    RTL8370_SDS0_REG14_CMU_EN_OFFSET    0
#define    RTL8370_SDS0_REG14_CMU_EN_MASK    0x1

#define    RTL8370_REG_SDS0_REG15    0x624f

#define    RTL8370_REG_SDS0_REG16    0x6250

#define    RTL8370_REG_SDS0_REG17    0x6251

#define    RTL8370_REG_SDS0_REG18    0x6252

#define    RTL8370_REG_SDS0_REG19    0x6253

#define    RTL8370_REG_SDS0_REG20    0x6254

#define    RTL8370_REG_SDS0_REG21    0x6255

#define    RTL8370_REG_SDS0_REG22    0x6256

#define    RTL8370_REG_SDS0_REG23    0x6257

#define    RTL8370_REG_SDS0_REG24    0x6258
#define    RTL8370_SDS0_REG24_sds_sdet_deg_OFFSET    14
#define    RTL8370_SDS0_REG24_sds_sdet_deg_MASK    0xC000
#define    RTL8370_SDS0_REG24_ana_rg10x_OFFSET    0
#define    RTL8370_SDS0_REG24_ana_rg10x_MASK    0x3FFF

#define    RTL8370_REG_SDS0_REG25    0x6259
#define    RTL8370_SDS0_REG25_pwrsv_ctl_sel_ext_OFFSET    15
#define    RTL8370_SDS0_REG25_pwrsv_ctl_sel_ext_MASK    0x8000
#define    RTL8370_SDS0_REG25_ana_rg11x_OFFSET    0
#define    RTL8370_SDS0_REG25_ana_rg11x_MASK    0x7FFF

#define    RTL8370_REG_SDS0_REG26    0x625a
#define    RTL8370_SDS0_REG26_use_25m_clk_OFFSET    15
#define    RTL8370_SDS0_REG26_use_25m_clk_MASK    0x8000
#define    RTL8370_SDS0_REG26_ana_rg12x_OFFSET    0
#define    RTL8370_SDS0_REG26_ana_rg12x_MASK    0x7FFF

#define    RTL8370_REG_SDS0_REG27    0x625b
#define    RTL8370_reg_inb_timeout_OFFSET    12
#define    RTL8370_reg_inb_timeout_MASK    0xF000
#define    RTL8370_SDS0_REG27_ana_rg13x_OFFSET    0
#define    RTL8370_SDS0_REG27_ana_rg13x_MASK    0xFFF

#define    RTL8370_REG_SDS0_REG28    0x625c

#define    RTL8370_REG_SDS0_REG29    0x625d

#define    RTL8370_REG_SDS0_REG30    0x625e
#define    RTL8370_SDS0_REG30_signstat_OFFSET    8
#define    RTL8370_SDS0_REG30_signstat_MASK    0x100
#define    RTL8370_SDS0_REG30_linkstat_OFFSET    4
#define    RTL8370_SDS0_REG30_linkstat_MASK    0xF0
#define    RTL8370_SDS0_REG30_syncstat_OFFSET    0
#define    RTL8370_SDS0_REG30_syncstat_MASK    0xF

#define    RTL8370_REG_SDS1_REG0    0x6440
#define    RTL8370_SDS1_REG0_sds_frc_rx_OFFSET    12
#define    RTL8370_SDS1_REG0_sds_frc_rx_MASK    0xF000
#define    RTL8370_SDS1_REG0_sds_frc_tx_OFFSET    8
#define    RTL8370_SDS1_REG0_sds_frc_tx_MASK    0xF00
#define    RTL8370_SDS1_REG0_dis_apx_OFFSET    7
#define    RTL8370_SDS1_REG0_dis_apx_MASK    0x80
#define    RTL8370_SDS1_REG0_soft_rst_OFFSET    6
#define    RTL8370_SDS1_REG0_soft_rst_MASK    0x40
#define    RTL8370_SDS1_REG0_inv_hsi_OFFSET    5
#define    RTL8370_SDS1_REG0_inv_hsi_MASK    0x20
#define    RTL8370_SDS1_REG0_inv_hso_OFFSET    4
#define    RTL8370_SDS1_REG0_inv_hso_MASK    0x10
#define    RTL8370_SDS1_REG0_mark_carr_ext_OFFSET    3
#define    RTL8370_SDS1_REG0_mark_carr_ext_MASK    0x8
#define    RTL8370_SDS1_REG0_codec_lpk_OFFSET    2
#define    RTL8370_SDS1_REG0_codec_lpk_MASK    0x4
#define    RTL8370_SDS1_REG0_afe_lpk_OFFSET    1
#define    RTL8370_SDS1_REG0_afe_lpk_MASK    0x2
#define    RTL8370_SDS1_REG0_remote_lpk_OFFSET    0
#define    RTL8370_SDS1_REG0_remote_lpk_MASK    0x1

#define    RTL8370_REG_SDS1_REG1    0x6441
#define    RTL8370_SDS1_REG1_ability_OFFSET    12
#define    RTL8370_SDS1_REG1_ability_MASK    0xF000
#define    RTL8370_SDS1_REG1_sds_restart_an_OFFSET    8
#define    RTL8370_SDS1_REG1_sds_restart_an_MASK    0xF00
#define    RTL8370_SDS1_REG1_sds_tx_down_OFFSET    7
#define    RTL8370_SDS1_REG1_sds_tx_down_MASK    0x80
#define    RTL8370_SDS1_REG1_send_np_on_OFFSET    6
#define    RTL8370_SDS1_REG1_send_np_on_MASK    0x40
#define    RTL8370_SDS1_REG1_sds_frc_an_OFFSET    4
#define    RTL8370_SDS1_REG1_sds_frc_an_MASK    0x30
#define    RTL8370_SDS1_REG1_frc_cggood_OFFSET    2
#define    RTL8370_SDS1_REG1_frc_cggood_MASK    0xC
#define    RTL8370_SDS1_REG1_cdet_OFFSET    0
#define    RTL8370_SDS1_REG1_cdet_MASK    0x3

#define    RTL8370_REG_SDS1_REG2    0x6442
#define    RTL8370_SDS1_REG2_frc_preamble_OFFSET    14
#define    RTL8370_SDS1_REG2_frc_preamble_MASK    0xC000
#define    RTL8370_SDS1_REG2_frc_ipg_OFFSET    12
#define    RTL8370_SDS1_REG2_frc_ipg_MASK    0x3000
#define    RTL8370_SDS1_REG2_sds_en_rx_OFFSET    11
#define    RTL8370_SDS1_REG2_sds_en_rx_MASK    0x800
#define    RTL8370_SDS1_REG2_sds_en_tx_OFFSET    10
#define    RTL8370_SDS1_REG2_sds_en_tx_MASK    0x400
#define    RTL8370_SDS1_REG2_sd_det_algor_OFFSET    9
#define    RTL8370_SDS1_REG2_sd_det_algor_MASK    0x200
#define    RTL8370_SDS1_REG2_auto_det_algor_OFFSET    8
#define    RTL8370_SDS1_REG2_auto_det_algor_MASK    0x100
#define    RTL8370_SDS1_REG2_rdm_algor_OFFSET    7
#define    RTL8370_SDS1_REG2_rdm_algor_MASK    0x80
#define    RTL8370_SDS1_REG2_byp_8b10b_OFFSET    6
#define    RTL8370_SDS1_REG2_byp_8b10b_MASK    0x40
#define    RTL8370_SDS1_REG2_dis_tmr_cma_OFFSET    5
#define    RTL8370_SDS1_REG2_dis_tmr_cma_MASK    0x20
#define    RTL8370_SDS1_REG2_cma_rq_OFFSET    0
#define    RTL8370_SDS1_REG2_cma_rq_MASK    0x1F

#define    RTL8370_REG_SDS1_REG3    0x6443
#define    RTL8370_SDS1_REG3_sds_lk_time_OFFSET    8
#define    RTL8370_SDS1_REG3_sds_lk_time_MASK    0xFF00
#define    RTL8370_SDS1_REG3_apxt_time_OFFSET    0
#define    RTL8370_SDS1_REG3_apxt_time_MASK    0xFF

#define    RTL8370_REG_SDS1_REG4    0x6444
#define    RTL8370_SDS1_REG4_wr_soft_rstb_OFFSET    15
#define    RTL8370_SDS1_REG4_wr_soft_rstb_MASK    0x8000
#define    RTL8370_SDS1_REG4_dbg_sts_sel_OFFSET    12
#define    RTL8370_SDS1_REG4_dbg_sts_sel_MASK    0x7000
#define    RTL8370_SDS1_REG4_reg_calib_ok_cnt_OFFSET    8
#define    RTL8370_SDS1_REG4_reg_calib_ok_cnt_MASK    0xF00
#define    RTL8370_SDS1_REG4_reg_pcsreq_pos_OFFSET    7
#define    RTL8370_SDS1_REG4_reg_pcsreq_pos_MASK    0x80
#define    RTL8370_SDS1_REG4_reg_mark_scr_OFFSET    6
#define    RTL8370_SDS1_REG4_reg_mark_scr_MASK    0x40
#define    RTL8370_SDS1_REG4_disan_link_sgm_OFFSET    5
#define    RTL8370_SDS1_REG4_disan_link_sgm_MASK    0x20
#define    RTL8370_SDS1_REG4_disan_link_fib_OFFSET    4
#define    RTL8370_SDS1_REG4_disan_link_fib_MASK    0x10
#define    RTL8370_SDS1_REG4_sgmii_ck_sel_OFFSET    3
#define    RTL8370_SDS1_REG4_sgmii_ck_sel_MASK    0x8
#define    RTL8370_SDS1_REG4_clr_soft_rstb_OFFSET    2
#define    RTL8370_SDS1_REG4_clr_soft_rstb_MASK    0x4
#define    RTL8370_SDS1_REG4_sel_deg_OFFSET    1
#define    RTL8370_SDS1_REG4_sel_deg_MASK    0x2
#define    RTL8370_SDS1_REG4_dis_renway_OFFSET    0
#define    RTL8370_SDS1_REG4_dis_renway_MASK    0x1

#define    RTL8370_REG_SDS1_REG5    0x6445
#define    RTL8370_SDS1_REG5_reg_pwrsv_ctrl_sel_OFFSET    15
#define    RTL8370_SDS1_REG5_reg_pwrsv_ctrl_sel_MASK    0x8000
#define    RTL8370_SDS1_REG5_reg_eee_sds_an_OFFSET    14
#define    RTL8370_SDS1_REG5_reg_eee_sds_an_MASK    0x4000
#define    RTL8370_SDS1_REG5_reg_c3_timer_OFFSET    11
#define    RTL8370_SDS1_REG5_reg_c3_timer_MASK    0x3800
#define    RTL8370_SDS1_REG5_reg_c2_timer_OFFSET    8
#define    RTL8370_SDS1_REG5_reg_c2_timer_MASK    0x700
#define    RTL8370_SDS1_REG5_reg_c1_timer_OFFSET    5
#define    RTL8370_SDS1_REG5_reg_c1_timer_MASK    0xE0
#define    RTL8370_SDS1_REG5_reg_c0_timer_OFFSET    2
#define    RTL8370_SDS1_REG5_reg_c0_timer_MASK    0x1C
#define    RTL8370_SDS1_REG5_reg_c2_pwrsav_en_OFFSET    1
#define    RTL8370_SDS1_REG5_reg_c2_pwrsav_en_MASK    0x2
#define    RTL8370_SDS1_REG5_reg_c1_pwrsav_en_OFFSET    0
#define    RTL8370_SDS1_REG5_reg_c1_pwrsav_en_MASK    0x1

#define    RTL8370_REG_SDS1_REG6    0x6446
#define    RTL8370_SDS1_REG6_eee_program_c3_OFFSET    15
#define    RTL8370_SDS1_REG6_eee_program_c3_MASK    0x8000
#define    RTL8370_SDS1_REG6_eee_program_c2_OFFSET    14
#define    RTL8370_SDS1_REG6_eee_program_c2_MASK    0x4000
#define    RTL8370_SDS1_REG6_eee_program_c1_OFFSET    13
#define    RTL8370_SDS1_REG6_eee_program_c1_MASK    0x2000
#define    RTL8370_SDS1_REG6_eee_program_c0_OFFSET    12
#define    RTL8370_SDS1_REG6_eee_program_c0_MASK    0x1000
#define    RTL8370_SDS1_REG6_eee_program_5_OFFSET    10
#define    RTL8370_SDS1_REG6_eee_program_5_MASK    0xC00
#define    RTL8370_SDS1_REG6_eee_program_4_OFFSET    8
#define    RTL8370_SDS1_REG6_eee_program_4_MASK    0x300
#define    RTL8370_SDS1_REG6_eee_program_3_OFFSET    6
#define    RTL8370_SDS1_REG6_eee_program_3_MASK    0xC0
#define    RTL8370_SDS1_REG6_eee_program_2_OFFSET    4
#define    RTL8370_SDS1_REG6_eee_program_2_MASK    0x30
#define    RTL8370_SDS1_REG6_eee_program_1_OFFSET    2
#define    RTL8370_SDS1_REG6_eee_program_1_MASK    0xC
#define    RTL8370_SDS1_REG6_eee_program_0_OFFSET    0
#define    RTL8370_SDS1_REG6_eee_program_0_MASK    0x3

#define    RTL8370_REG_SDS1_REG7    0x6447
#define    RTL8370_SDS1_REG7_byp_start_OFFSET    12
#define    RTL8370_SDS1_REG7_byp_start_MASK    0xF000
#define    RTL8370_SDS1_REG7_byp_end_OFFSET    8
#define    RTL8370_SDS1_REG7_byp_end_MASK    0xF00
#define    RTL8370_SDS1_REG7_tx_bypscr_OFFSET    4
#define    RTL8370_SDS1_REG7_tx_bypscr_MASK    0xF0
#define    RTL8370_SDS1_REG7_rx_bypscr_OFFSET    0
#define    RTL8370_SDS1_REG7_rx_bypscr_MASK    0xF

#define    RTL8370_REG_SDS1_REG8    0x6448

#define    RTL8370_REG_SDS1_REG9    0x6449

#define    RTL8370_REG_SDS1_REG10    0x644a

#define    RTL8370_REG_SDS1_REG11    0x644b

#define    RTL8370_REG_SDS1_REG12    0x644c

#define    RTL8370_REG_SDS1_REG13    0x644d

#define    RTL8370_REG_SDS1_REG14    0x644e
#define    RTL8370_SDS1_REG14_ana_rg0x_OFFSET    8
#define    RTL8370_SDS1_REG14_ana_rg0x_MASK    0x1F00
#define    RTL8370_SDS1_REG14_CLKREQB_OFFSET    3
#define    RTL8370_SDS1_REG14_CLKREQB_MASK    0x8
#define    RTL8370_SDS1_REG14_PDOWN_OFFSET    2
#define    RTL8370_SDS1_REG14_PDOWN_MASK    0x4
#define    RTL8370_SDS1_REG14_RX_EN_OFFSET    1
#define    RTL8370_SDS1_REG14_RX_EN_MASK    0x2
#define    RTL8370_SDS1_REG14_CMU_EN_OFFSET    0
#define    RTL8370_SDS1_REG14_CMU_EN_MASK    0x1

#define    RTL8370_REG_SDS1_REG15    0x644f

#define    RTL8370_REG_SDS1_REG16    0x6450

#define    RTL8370_REG_SDS1_REG17    0x6451

#define    RTL8370_REG_SDS1_REG18    0x6452

#define    RTL8370_REG_SDS1_REG19    0x6453

#define    RTL8370_REG_SDS1_REG20    0x6454

#define    RTL8370_REG_SDS1_REG21    0x6455

#define    RTL8370_REG_SDS1_REG22    0x6456

#define    RTL8370_REG_SDS1_REG23    0x6447

#define    RTL8370_REG_SDS1_REG24    0x6458
#define    RTL8370_SDS1_REG24_sds_sdet_deg_OFFSET    14
#define    RTL8370_SDS1_REG24_sds_sdet_deg_MASK    0xC000
#define    RTL8370_SDS1_REG24_ana_rg10x_OFFSET    0
#define    RTL8370_SDS1_REG24_ana_rg10x_MASK    0x3FFF

#define    RTL8370_REG_SDS1_REG25    0x6459
#define    RTL8370_SDS1_REG25_pwrsv_ctl_sel_ext_OFFSET    15
#define    RTL8370_SDS1_REG25_pwrsv_ctl_sel_ext_MASK    0x8000
#define    RTL8370_SDS1_REG25_ana_rg11x_OFFSET    0
#define    RTL8370_SDS1_REG25_ana_rg11x_MASK    0x7FFF

#define    RTL8370_REG_SDS1_REG26    0x645a
#define    RTL8370_SDS1_REG26_use_25m_clk_OFFSET    15
#define    RTL8370_SDS1_REG26_use_25m_clk_MASK    0x8000
#define    RTL8370_SDS1_REG26_ana_rg12x_OFFSET    0
#define    RTL8370_SDS1_REG26_ana_rg12x_MASK    0x7FFF

#define    RTL8370_REG_SDS1_REG27    0x645b
#define    RTL8370_SDS1_REG27_OFFSET    0
#define    RTL8370_SDS1_REG27_MASK    0xFFF

#define    RTL8370_REG_SDS1_REG28    0x645c

#define    RTL8370_REG_SDS1_REG29    0x645d

#define    RTL8370_REG_SDS1_REG30    0x645e
#define    RTL8370_SDS1_REG30_signstat_OFFSET    8
#define    RTL8370_SDS1_REG30_signstat_MASK    0x100
#define    RTL8370_SDS1_REG30_linkstat_OFFSET    4
#define    RTL8370_SDS1_REG30_linkstat_MASK    0xF0
#define    RTL8370_SDS1_REG30_syncstat_OFFSET    0
#define    RTL8370_SDS1_REG30_syncstat_MASK    0xF


#endif /*#ifndef _RTL8370_REG_H_*/


#define RTL8370_LEDGROUPMAX					2	
#define RTL8370_LEDGROUPMASK               0x7
#define RTL8370_LED_FORCE_MODE_BASE        RTL8370_REG_CPU_FORCE_LED0_CFG0
#define RTL8370_LED_FORCE_CTRL             RTL8370_REG_CPU_FORCE_LED_CFG
#define RTL8370_LEDPORTMAX				   8

enum RTL8370_LEDOP{

    LEDOP_SCAN0=0,         
    LEDOP_SCAN1,        
    LEDOP_PARALLEL,        
    LEDOP_SERIAL, 
    LEDOP_MAX,
};

enum RTL8370_LEDSERACT{

    LEDSERACT_HIGH=0,         
    LEDSERACT_LOW,        
    LEDSERACT_MAX,
};

enum RTL8370_LEDSER{

    LEDSER_16G=0,         
    LEDSER_8G,        
    LEDSER_MAX,
};

enum RTL8370_LEDCONF{

    LEDCONF_LEDOFF=0,         
    LEDCONF_DUPCOL,        
    LEDCONF_LINK_ACT,        
    LEDCONF_SPD1000,        
    LEDCONF_SPD100,        
    LEDCONF_SPD10,            
    LEDCONF_SPD1000ACT,    
    LEDCONF_SPD100ACT,    
    LEDCONF_SPD10ACT,        
    LEDCONF_SPD10010ACT,  
    LEDCONF_LOOPDETECT,            
    LEDCONF_EEE,            
    LEDCONF_LINKRX,        
    LEDCONF_LINKTX,        
    LEDCONF_MASTER,        
    LEDCONF_ACT,    
};

enum RTL8370_LEDBLINKRATE{

	LEDBLINKRATE_32MS=0, 		
	LEDBLINKRATE_64MS,		
	LEDBLINKRATE_128MS,
	LEDBLINKRATE_256MS,
	LEDBLINKRATE_512MS,
	LEDBLINKRATE_1024MS,
	LEDBLINKRATE_48MS,
	LEDBLINKRATE_96MS,
	LEDBLINKRATE_MAX,

};

enum RTL8370_LEDFORCEMODE{

    LEDFORCEMODE_NORMAL=0,
    LEDFORCEMODE_BLINK,
    LEDFORCEMODE_OFF,
    LEDFORCEMODE_ON,
    LEDFORCEMODE_MAX,
};

enum RTL8370_LEDFORCERATE{

    LEDFORCERATE_512MS=0,
    LEDFORCERATE_1024MS,
    LEDFORCERATE_2048MS,
    LEDFORCERATE_NORMAL,
    LEDFORCERATE_MAX,

};

#define CONST_T               const

#define RTL8370_REGBITLENGTH               16
#define RTL8370_REGDATAMAX                 0xFFFF


#define MDIO_NOP_DELAY delay(1);
#define MDIO_PULSE_P  _rtl865x_setGpioDataBit(smi_SCK, 0); MDIO_NOP_DELAY; _rtl865x_setGpioDataBit(smi_SCK, 1); MDIO_NOP_DELAY 

#define LS2H_GPIO_CFG_REG (*(volatile int *)0xffffffffbfd000c0LL)
#define LS2H_GPIO_OE_REG  (*(volatile int *)0xffffffffbfd000c4LL)
#define LS2H_GPIO_IN_REG  (*(volatile int *)0xffffffffbfd000c8LL)
#define LS2H_GPIO_OUT_REG (*(volatile int *)0xffffffffbfd000ccLL)

#define GPIO_ID(port, pin) pin
enum {
GPIO_PERI_GPIO = 1,
GPIO_DIR_OUT = 1,
GPIO_DIR_IN = 0,
GPIO_INT_DISABLE = 0,
GPIO_INT_ENABLE = 1,
};

typedef int gpioID;
typedef int int32;
typedef unsigned int uint32;

gpioID smi_SCK;        /* GPIO used for SMI Clock Generation */
gpioID smi_SDA;        /* GPIO used for SMI Data signal */
gpioID smi_RST;     /* GPIO used for reset swtich */



int _rtl865x_initGpioPin(int pin, int gpioen, int outen,int irqen)
{
/*low output*/
if(outen) LS2H_GPIO_OE_REG &= ~(1<<pin);
else LS2H_GPIO_OE_REG |= (1<<pin);
 
/*low gpio*/
if((LS2H_GPIO_CFG_REG>>pin) != !gpioen)
{
if(gpioen)
 LS2H_GPIO_CFG_REG &= ~(1<<pin);
else
  LS2H_GPIO_CFG_REG |= (1<<pin);  
}
return 0;
}

int _rtl865x_setGpioDataBit(int pin, int val)
{

if(val)
 LS2H_GPIO_OUT_REG  |= 1<<pin;
else
 LS2H_GPIO_OUT_REG  &= ~(1<<pin);
return 0;
}

int _rtl865x_getGpioDataBit(int pin, int *pval)
{
*pval = (LS2H_GPIO_IN_REG>>pin)&1;
return 0;
}

void MDIO_idle()
{
	unsigned char i;

	for(i=0;i<35;i++)
	{
		_rtl865x_setGpioDataBit(smi_SDA, 1);
		MDIO_PULSE_P;
	}
}

void MDIO_read_head()
{
	_rtl865x_setGpioDataBit(smi_SDA, 0);  //start code 01
	MDIO_PULSE_P;
	_rtl865x_setGpioDataBit(smi_SDA, 1);
	MDIO_PULSE_P;
	_rtl865x_setGpioDataBit(smi_SDA, 1);  //operation code 10 for read, 01 for write
	MDIO_PULSE_P;
	_rtl865x_setGpioDataBit(smi_SDA, 0);
	MDIO_PULSE_P;
}

void MDIO_write_head()
{
    _rtl865x_setGpioDataBit(smi_SDA, 0);  //start code 01
    MDIO_PULSE_P;
    _rtl865x_setGpioDataBit(smi_SDA, 1);
    MDIO_PULSE_P;
    _rtl865x_setGpioDataBit(smi_SDA, 0);  //operation code 10 for read, 01 for write
    MDIO_PULSE_P;
    _rtl865x_setGpioDataBit(smi_SDA, 1);
    MDIO_PULSE_P;        
}

void MDIO_send_address(unsigned char uPort,unsigned char uOffset)
{
	unsigned char i;

	for (i=0; i<5; i++) 
		{
		_rtl865x_setGpioDataBit(smi_SDA, (uPort&0x10)?1:0);
		MDIO_PULSE_P;
		uPort = uPort << 1;
		}

	for (i=0; i<5; i++) 
		{
		_rtl865x_setGpioDataBit(smi_SDA, (uOffset&0x10)?1:0);
		MDIO_PULSE_P;
		uOffset = uOffset << 1;
		}
}

void MDIO_send_data(unsigned char d)
{
	unsigned char i;

	for (i=0; i<8; i++) 
		{
		_rtl865x_setGpioDataBit(smi_SDA, (d&0x80)?1:0);
		MDIO_PULSE_P;
		d = d << 1;
		}
}

unsigned char MDIO_read_byte()
{
	unsigned char i,c;
	int b;
       c=0;
	for (i=0; i<8; i++) 
		{
		MDIO_PULSE_P;
		_rtl865x_getGpioDataBit(smi_SDA, &b);
		c=(c<<1)|b;
		}
	return c;
}


void   MDC_MDIO_WRITE(int dummy, unsigned char uPort,unsigned char uOffset, unsigned short data)
{
	unsigned char uD_h;
	unsigned char uD_l;
	uD_h = (data>>8) & 0xff;
	uD_l = data&0xff;
	MDIO_idle(); 
	MDIO_write_head();
	MDIO_send_address(uPort,uOffset);
	
	_rtl865x_setGpioDataBit(smi_SDA, 1);  //write turn arround
	MDIO_PULSE_P;
	_rtl865x_setGpioDataBit(smi_SDA, 0);
	MDIO_PULSE_P; 	
	
	MDIO_send_data(uD_h);
	MDIO_send_data(uD_l);
	MDIO_idle();    	
}

void MDC_MDIO_READ(int dummy, unsigned char uPort,unsigned char uOffset, unsigned int *uD_h)
{unsigned char uD_hh, uD_hl;

	MDIO_idle();    
	MDIO_read_head();
	MDIO_send_address(uPort,uOffset);

	_rtl865x_setGpioDataBit(smi_SDA, 1);  //read turn arround
	MDIO_PULSE_P;
    _rtl865x_initGpioPin(smi_SDA, GPIO_PERI_GPIO, GPIO_DIR_IN, GPIO_INT_DISABLE);
	MDIO_PULSE_P; 	

	uD_hh= MDIO_read_byte();
	uD_hl= MDIO_read_byte();
    _rtl865x_initGpioPin(smi_SDA, GPIO_PERI_GPIO, GPIO_DIR_OUT, GPIO_INT_DISABLE);
	MDIO_idle();    

	//enable_debug_output=1;
	// putdata(uD_hh); putdata(uD_hl);
           //   debug_printf("read mdio uD_hh:0x%1x\n",(unsigned char) uD_hh);	
	    //  debug_printf("read mdio uD_hl:0x%x\n",uD_hl);	
           //   debug_printf("read mdio uD_hh:%d\n",uD_hh);	
	    //  debug_printf("read mdio uD_hl:%d\n",uD_hl);	
	*uD_h=(unsigned int)uD_hl+(unsigned int)(uD_hh<<8);	
	//debug_printf("read mdio uD_h:0x%04x\n",*uD_h);	
}

int32 smi_init(uint32 port, uint32 pinSCK, uint32 pinSDA)
{
    gpioID gpioId;
    int32 res;

    /* change GPIO pin to Input only */
    /* Initialize GPIO port C, pin 0 as SMI SDA0 */
    gpioId = GPIO_ID(port, pinSDA);
    res = _rtl865x_initGpioPin(gpioId, GPIO_PERI_GPIO, GPIO_DIR_OUT, GPIO_INT_DISABLE);
    if (res != RT_ERR_OK)
        return res;
    smi_SDA = gpioId;


    /* Initialize GPIO port C, pin 1 as SMI SCK0 */
    gpioId = GPIO_ID(port, pinSCK);
    res = _rtl865x_initGpioPin(gpioId, GPIO_PERI_GPIO, GPIO_DIR_OUT, GPIO_INT_DISABLE);
    if (res != RT_ERR_OK)
        return res;
    smi_SCK = gpioId;


    _rtl865x_setGpioDataBit(smi_SDA, 1);    
    _rtl865x_setGpioDataBit(smi_SCK, 1);    
    return RT_ERR_OK;
}

#define rtl8370_getAsicReg RTL8367_getReg

unsigned int  RTL8367_getReg(unsigned int  reg_addrs,unsigned *reg_data)
{
	unsigned int   r_data;
	

    /* Write address control code to register 31 */
    //MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_DUMMY_ID, MDC_MDIO_CTRL0_REG, MDC_MDIO_ADDR_OP);
    MDC_MDIO_WRITE(0,0,31, 0x0E);//delay_ms(20);
    /* Write address to register 23 */
    //MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_DUMMY_ID, MDC_MDIO_ADDRESS_REG, mAddrs);
    MDC_MDIO_WRITE(0,0,23, reg_addrs);//delay_ms(20);
    /* Write data to register 24 */
    //MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_DUMMY_ID, MDC_MDIO_DATA_WRITE_REG, rData);
    MDC_MDIO_WRITE(0,0,21,0x01);//delay_ms(20);
    /* Write data control code to register 21 */
   // MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_DUMMY_ID, MDC_MDIO_CTRL1_REG, MDC_MDIO_WRITE_OP);
    MDC_MDIO_READ(32,0,25,&r_data);
    *reg_data=r_data;
 //   debug_printf("rtl8370_getReg:0x%04x\n",*reg_data);	
//	regdata= addrs[0]+(unsigned int)(addrs[1]<<8);
//    return regdata;
return 0;
}

unsigned int RTL8367_setReg(unsigned int  mAddrs, unsigned int  rData)
{

    /* Write address control code to register 31 */
   // MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_DUMMY_ID, MDC_MDIO_CTRL0_REG, MDC_MDIO_ADDR_OP);
    MDC_MDIO_WRITE(0,0, 31,0x0E);//delay_ms(20);

    /* Write address to register 23 */
    MDC_MDIO_WRITE(0, 0, 23, mAddrs);

    /* Write read control code to register 21 */
    MDC_MDIO_WRITE(0, 0, 24, rData);

    /* Read data from register 25 */
  //  MDC_MDIO_READ(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_DUMMY_ID, MDC_MDIO_DATA_READ_REG, rData);
    MDC_MDIO_WRITE(0, 0,21,0x03);//delay_ms(20);
    return 0;
}

unsigned int rtl8370_setAsicRegBit(unsigned int reg, unsigned int regbit, unsigned int value)
{

    unsigned int regData;
    unsigned int retVal;
    
    retVal = RTL8367_getReg(reg, &regData);

    if (value) 
        regData = regData | (1<<regbit);
    else
        regData = regData & (~(1<<regbit));
    
    retVal = RTL8367_setReg(reg, regData);
    if (retVal != RT_ERR_OK) 
         return RT_ERR_SMI;
    return RT_ERR_OK;
}

unsigned int rtl8370_getAsicRegBit(unsigned int reg, unsigned int regbit, unsigned int *value)
{
    unsigned int regData;
    unsigned int retVal;

    retVal = RTL8367_getReg(reg, &regData);
    if (retVal != RT_ERR_OK) 
		return RT_ERR_SMI;
    *value = (regData & (0x1 << regbit)) >> regbit;    

    return RT_ERR_OK;
}



unsigned int rtl8370_setAsicRegBits(unsigned int reg, unsigned int bits, unsigned int value)
{
    
    unsigned int regData;    
    unsigned int retVal;    
    unsigned int bitsShift;    
    unsigned int valueShifted;        

   
    bitsShift = 0;
	//debug_printf("valueshift=:%.4x\n", valueShifted);
    while(!(bits & (1 << bitsShift)))
    {
        bitsShift++;
        if(bitsShift >= RTL8370_REGBITLENGTH)
            return RT_ERR_INPUT;
    }
    valueShifted = value << bitsShift;
//debug_printf("valueshift=:%.4x\n", valueShifted);
    if(valueShifted > RTL8370_REGDATAMAX)
        return RT_ERR_INPUT;

    retVal = RTL8367_getReg(reg, &regData);
    if (retVal != RT_ERR_OK) 
		return RT_ERR_SMI;
 
    regData = regData & (~bits);
    regData = regData | (valueShifted & bits);

    retVal = RTL8367_setReg(reg, regData);
    if (retVal != RT_ERR_OK) 
		return RT_ERR_SMI;
 
    return RT_ERR_OK;
}

unsigned int rtl8370_getAsicRegBits(unsigned int reg, unsigned int bits, unsigned int *value)
{  
    unsigned int regData;    
    unsigned int retVal;    
    unsigned int bitsShift;    

   // if(bits>= (1<<RTL8370_REGBITLENGTH) )
   //     return RT_ERR_INPUT;    

    bitsShift = 0;
    while(!(bits & (1 << bitsShift)))
    {
        bitsShift++;
        if(bitsShift >= RTL8370_REGBITLENGTH)
            return RT_ERR_INPUT;
    }
    
    retVal = RTL8367_getReg(reg, &regData);
    if (retVal != RT_ERR_OK) 
		return RT_ERR_SMI;

    *value = (regData & bits) >> bitsShift;
  
    return RT_ERR_OK;
}




unsigned int rtl8370_setAsicReg(unsigned int reg, unsigned int value)
{
    if(reg > 0xffff || value > 0xffff )
	    return RT_ERR_INPUT;

    RTL8367_setReg(reg, value);

    return RT_ERR_OK;
}


#define	RTL8370_MAC7		7
#define    RTL8370_EXTNO       2

enum EXTMODE
{
    EXT_DISABLE = 0,
    EXT_RGMII,
    EXT_MII_MAC,
    EXT_MII_PHY, 
    EXT_TMII_MAC,
    EXT_TMII_PHY, 
    EXT_GMII,
    EXT_RGMII_33V
};

enum SPEEDMODE
{
	SPD_10M = 0,
	SPD_100M,
	SPD_1000M
};

/* enum for mac link mode */
enum LINKMODE
{
	MAC_NORMAL = 0,
	MAC_FORCE,
};

/* enum for port current link duplex mode */
enum DUPLEXMODE
{
	HALF_DUPLEX = 0,
	FULL_DUPLEX
};

typedef enum rtk_port_linkStatus_e
{
    PORT_LINKDOWN = 0,
    PORT_LINKUP,
    PORT_LINKSTATUS_END
} rtk_port_linkStatus_t;

typedef enum rtk_enable_e
{
    DISABLED = 0,
    ENABLED,
    RTK_ENABLE_END
} rtk_enable_t;

typedef int                   rtk_api_ret_t;
typedef int                   ret_t;
typedef long long                  rtk_u_long_t;
typedef short uint16;

typedef unsigned int  rtk_data_t; 

typedef struct  rtk_port_mac_ability_s
{
    uint32 forcemode;
    uint32 speed;
    uint32 duplex;
    uint32 link;    
    uint32 nway;    
    uint32 txpause;
    uint32 rxpause;      
    uint32 lpi100;
    uint32 lpi1000;   
}rtk_port_mac_ability_t;

typedef enum rtk_mode_ext_e
{
    MODE_EXT_DISABLE = 0,
    MODE_EXT_RGMII,
    MODE_EXT_MII_MAC,
    MODE_EXT_MII_PHY, 
    MODE_EXT_TMII_MAC,
    MODE_EXT_TMII_PHY, 
    MODE_EXT_GMII,
    MODE_EXT_RGMII_33V,   
    MODE_EXT_END
} rtk_mode_ext_t;

typedef struct  rtl8370_port_ability_s{
#ifdef _LITTLE_ENDIAN
    uint16 speed:2;
    uint16 duplex:1;
    uint16 reserve1:1;
    uint16 link:1;
    uint16 rxpause:1;
    uint16 txpause:1;
    uint16 nway:1;	
    uint16 mstmode:1;
    uint16 mstfault:1;	
    uint16 lpi100:1;
    uint16 lpi1000:1;
    uint16 forcemode:1;
    uint16 reserve3:3;
#else
    uint16 reserve3:3;
    uint16 forcemode:1;
    uint16 lpi1000:1;
    uint16 lpi100:1;
    uint16 mstfault:1; 
    uint16 mstmode:1;
    uint16 nway:1;	
    uint16 txpause:1;
    uint16 rxpause:1;
    uint16 link:1;
    uint16 reserve1:1;	
    uint16 duplex:1;	
    uint16 speed:2;
	
#endif
}rtl8370_port_ability_t;

#define RTK_EXT_0                                   0
#define RTK_EXT_1                                   1

int rtl8370_setAsicPortExtMode(uint32 id, uint32 mode)
{
    int retVal;
    
    if(id >= RTL8370_EXTNO)
        return RT_ERR_INPUT;	

    if(mode > EXT_RGMII_33V)
        return RT_ERR_INPUT;	

    if( mode == EXT_RGMII_33V || mode == EXT_RGMII )
    {
        if((retVal= rtl8370_setAsicReg(RTL8370_REG_CHIP_DEBUG0,0x0367)) !=  RT_ERR_OK)
            return retVal;
        if((retVal= rtl8370_setAsicReg(RTL8370_REG_CHIP_DEBUG1,0x7777)) !=  RT_ERR_OK)
            return retVal;
    }
    else if((mode == EXT_TMII_MAC)||(mode == EXT_TMII_PHY))
    {
        if((retVal= rtl8370_setAsicRegBit(RTL8370_REG_BYPASS_LINE_RATE,(id+1)%2,1)) !=  RT_ERR_OK)
            return retVal;
    } 
    else if( mode == EXT_GMII )
    {
        if((retVal= rtl8370_setAsicRegBit(RTL8370_REG_CHIP_DEBUG0,RTL8370_CHIP_DEBUG0_DUMMY_0_OFFSET+id,1)) !=  RT_ERR_OK)
            return retVal;
        if((retVal= rtl8370_setAsicRegBit(RTL8370_REG_EXT0_RGMXF+id,6,1)) !=  RT_ERR_OK)
            return retVal;        
    } 
    else 
    {
        if((retVal= rtl8370_setAsicRegBit(RTL8370_REG_BYPASS_LINE_RATE,(id+1)%2,0)) !=  RT_ERR_OK)
            return retVal;
        if((retVal= rtl8370_setAsicRegBit(RTL8370_REG_EXT0_RGMXF+id,6,0)) !=  RT_ERR_OK)
            return retVal;     
    }      

    return rtl8370_setAsicRegBits(RTL8370_REG_DIGITIAL_INTERFACE_SELECT, RTL8370_SELECT_RGMII_0_MASK<<(id*RTL8370_SELECT_RGMII_1_OFFSET), mode);
}



int getReg(int mAddrs)
{
int rData;
RTL8367_getReg(mAddrs, &rData);
return rData;
}

void  macForceLinkExt01_set()
{
    rtl8370_setAsicPortExtMode(0, EXT_RGMII);
    rtl8370_setAsicPortExtMode(1, EXT_RGMII);     
    rtl8370_setAsicReg(0x1310, 0x1076);
    rtl8370_setAsicReg(0x1311, 0x1076);
}


ret_t rtl8370_getAsicPortForceLinkExt(uint32 id, rtl8370_port_ability_t *portability)
{
    ret_t retVal;
    uint32 regData;
    uint16 *accessPtr;
    rtl8370_port_ability_t ability;

    /* Invalid input parameter */
    if(id >= RTL8370_EXTNO)
        return RT_ERR_PORT_ID;
    
    memset(&ability,0x00,sizeof(rtl8370_port_ability_t));


    accessPtr =  (uint16*)&ability;
 
    retVal = rtl8370_getAsicReg(RTL8370_REG_DIGITIAL_INTERFACE0_FORCE + id, &regData);
    if(retVal !=  RT_ERR_OK)
        return retVal;
    
    *accessPtr = regData;

    memcpy(portability, &ability, sizeof(rtl8370_port_ability_t));        
    
    return RT_ERR_OK;  
}

ret_t rtl8370_setAsicPortForceLinkExt(uint32 id, rtl8370_port_ability_t *portability)
{
    uint32 regData;
    uint16 *accessPtr;
    rtl8370_port_ability_t ability;

    /* Invalid input parameter */
    if(id >=RTL8370_EXTNO)
        return RT_ERR_PORT_ID;
    
    memset(&ability, 0x00, sizeof(rtl8370_port_ability_t));
    memcpy(&ability, portability, sizeof(rtl8370_port_ability_t));    

    accessPtr = (uint16*)&ability;
 
    regData = *accessPtr;

    return rtl8370_setAsicReg(RTL8370_REG_DIGITIAL_INTERFACE0_FORCE + id, regData);
}

rtk_api_ret_t rtk_port_macForceLinkExt0_set(rtk_mode_ext_t mode, rtk_port_mac_ability_t *pPortability)
{
    rtk_api_ret_t retVal;
    rtl8370_port_ability_t ability;

    if (mode >=MODE_EXT_END)
        return RT_ERR_INPUT;    

    if (pPortability->forcemode>1||pPortability->speed>2||pPortability->duplex>1||
       pPortability->link>1||pPortability->nway>1||pPortability->txpause>1||pPortability->rxpause>1)
        return RT_ERR_INPUT;

    if ((retVal = rtl8370_setAsicPortExtMode(RTK_EXT_0, mode))!=RT_ERR_OK)
        return retVal;

    if ((retVal = rtl8370_getAsicPortForceLinkExt(RTK_EXT_0,&ability))!=RT_ERR_OK)
        return retVal;
     
    ability.forcemode = pPortability->forcemode;
    ability.speed     = pPortability->speed;
    ability.duplex    = pPortability->duplex;
    ability.link      = pPortability->link;
    ability.nway      = pPortability->nway;
    ability.txpause   = pPortability->txpause;
    ability.rxpause   = pPortability->rxpause;

    if ((retVal = rtl8370_setAsicPortForceLinkExt(RTK_EXT_0,&ability))!=RT_ERR_OK)
        return retVal;

    return RT_ERR_OK;
}

rtk_api_ret_t rtk_port_macForceLinkExt1_set(rtk_mode_ext_t mode, rtk_port_mac_ability_t *pPortability)
{
    rtk_api_ret_t retVal;
    rtl8370_port_ability_t ability;

    if (mode >=MODE_EXT_END)
        return RT_ERR_INPUT;

    if (pPortability->forcemode>1||pPortability->speed>2||pPortability->duplex>1||
       pPortability->link>1||pPortability->nway>1||pPortability->txpause>1||pPortability->rxpause>1)
        return RT_ERR_INPUT;

    if ((retVal = rtl8370_setAsicPortExtMode(RTK_EXT_1, mode))!=RT_ERR_OK)
        return retVal;

    if ((retVal = rtl8370_getAsicPortForceLinkExt(RTK_EXT_1,&ability))!=RT_ERR_OK)
        return retVal;
     
    ability.forcemode = pPortability->forcemode;
    ability.speed     = pPortability->speed;
    ability.duplex    = pPortability->duplex;
    ability.link      = pPortability->link;
    ability.nway      = pPortability->nway;
    ability.txpause   = pPortability->txpause;
    ability.rxpause   = pPortability->rxpause;

    if ((retVal = rtl8370_setAsicPortForceLinkExt(RTK_EXT_1,&ability))!=RT_ERR_OK)
        return retVal;

    return RT_ERR_OK;
}

/* Function Name:
 *      rtk_port_rgmiiDelayExt1_set
 * Description:
 *      Set RGMII interface 1 delay value for TX and RX.
 * Input:
 *      txDelay - TX delay value, 1 for delay 2ns and 0 for no-delay
 *      rxDelay - RX delay value, 0~7 for delay setup.
 * Output:
 *      None 
 * Return:
 *      RT_ERR_OK              - set shared meter successfully
 *      RT_ERR_FAILED          - FAILED to iset shared meter
 *      RT_ERR_SMI             - SMI access error
 *      RT_ERR_INPUT - Invalid input parameters.
 * Note:
 *      This API can set external interface 1 RGMII delay. 
 *      In TX delay, there are 2 selection: no-delay and 2ns delay.
 *      In RX dekay, there are 8 steps for delay tunning. 0 for n0-delay, and 7 for maximum delay.  
 */
rtk_api_ret_t rtk_port_rgmiiDelayExt1_set(rtk_data_t txDelay, rtk_data_t rxDelay)
{
    rtk_api_ret_t retVal;
    uint32 regData;

    if ((txDelay > 1)||(rxDelay > 7))
        return RT_ERR_INPUT;
    
    if ((retVal = rtl8370_getAsicReg(RTL8370_REG_EXT1_RGMXF, &regData))!=RT_ERR_OK)
        return retVal;

    regData = (regData&0xFFF0) | ((txDelay<<3)&0x0008) | (rxDelay&0x007);

    if ((retVal = rtl8370_setAsicReg(RTL8370_REG_EXT1_RGMXF, regData))!=RT_ERR_OK)
        return retVal;

    return RT_ERR_OK;
}

rtk_api_ret_t rtk_port_rgmiiDelayExt0_set(rtk_data_t txDelay, rtk_data_t rxDelay)
{
    rtk_api_ret_t retVal;
    uint32 regData;

    if ((txDelay > 1)||(rxDelay > 7))
        return RT_ERR_INPUT;
    
    if ((retVal = rtl8370_getAsicReg(RTL8370_REG_EXT0_RGMXF, &regData))!=RT_ERR_OK)
        return retVal;

    regData = (regData&0xFFF0) | ((txDelay<<3)&0x0008) | (rxDelay&0x007);

    if ((retVal = rtl8370_setAsicReg(RTL8370_REG_EXT0_RGMXF, regData))!=RT_ERR_OK)
        return retVal;

    return RT_ERR_OK;
}


/*
@func ret_t | rtl8370_setAsicLedOperationMode | Set LED operation mode
@parm uint32 | mode | LED mode. 1:scan mode 1, 2:parallel mode, 3:mdx mode (serial mode) 
@rvalue RT_ERR_OK | Success.
@rvalue RT_ERR_SMI | SMI access error.
@rvalue RT_ERR_INPUT | Invalid input value.
@comm
    The API can turn on/off led serial mode and set signal to active high/low.
 */
ret_t rtl8370_setAsicLedOperationMode(uint32 mode)
{
    ret_t retVal;
    
    /* Invalid input parameter */
    if( mode >= LEDOP_MAX)
        return RT_ERR_INPUT; 

    if( mode == LEDOP_SCAN0)
        return RT_ERR_INPUT;   

    switch(mode)
    {
        case LEDOP_SCAN0:
            break;
        case LEDOP_SCAN1:
            if((retVal = rtl8370_setAsicReg(RTL8370_REG_LED_SYS_CONFIG,0x1471))!=  RT_ERR_OK)
		    return retVal;
            if((retVal = rtl8370_setAsicReg(RTL8370_REG_SCAN1_LED_IO_EN,0xFFBF))!=  RT_ERR_OK)
		        return retVal;       
            break;
        case LEDOP_PARALLEL:
            if((retVal = rtl8370_setAsicReg(RTL8370_REG_LED_SYS_CONFIG,0x1472))!=  RT_ERR_OK)
		        return retVal;
            break;
        case LEDOP_SERIAL:
            if((retVal = rtl8370_setAsicReg(RTL8370_REG_LED_SYS_CONFIG,0x14F7))!=  RT_ERR_OK)
		        return retVal;        
            break;
        default:
            break;
    }
    
    return RT_ERR_OK;
}


/*
@func int32 | rtl8370_setAsicPHYReg | Set PHY registers .
@parm uint32 | phyNo | PHY number (0~7).
@parm uint32 | phyAddr | PHY address (0~31).
@parm uint32 | data | Writing data.
@rvalue RT_ERR_OK | 
@rvalue RT_ERR_FAILED | invalid parameter
@rvalue RT_ERR_PHY_REG_ID | invalid PHY address
@rvalue RT_ERR_PORT_ID | invalid port id.
@rvalue RT_ERR_BUSYWAIT_TIMEOUT | PHY access busy
@comm
    The API can set internal PHY register 0~31. There are 8 internal PHYs in switch and each PHY can be
    accessed by software.
 */
ret_t rtl8370_setAsicPHYReg( uint32 phyNo, uint32 phyAddr, uint32 value)
{
	uint32 regAddr;

    if(phyNo > 7)
        return -1;

    if(phyAddr > 31)
        return -1;

    regAddr = 0x2000 + (phyNo << 5) + phyAddr;

    return rtl8370_setAsicReg(regAddr, value);
}





/*
@func int32 | rtl8370_getAsicPHYReg | Set PHY registers .
@parm uint32 | phyNo | PHY number (0~7).
@parm uint32 | phyAddr | PHY address (0~31).
@parm uint32* | data | Read data.
@rvalue RT_ERR_OK | 
@rvalue RT_ERR_FAILED | invalid parameter
@rvalue RT_ERR_PHY_REG_ID | invalid PHY address
@rvalue RT_ERR_PORT_ID | iinvalid port id
@rvalue RT_ERR_BUSYWAIT_TIMEOUT | PHY access busy
@comm
     The API can get internal PHY register 0~31. There are 8 internal PHYs in switch and each PHY can be
    accessed by software.
 */
ret_t rtl8370_getAsicPHYReg( uint32 phyNo, uint32 phyAddr, uint32 *value)
{
	uint32 regAddr;

    if(phyNo > 7)
        return -1;

    if(phyAddr > 31)
        return -1;

    regAddr = 0x2000 + (phyNo << 5) + phyAddr;
	
    return rtl8370_getAsicReg(regAddr, value);
}

static int test_switch_phy()
{
	static int m,n=9;
	uint32 value;
	for(m=0;m<=7;m++){
		rtl8370_getAsicPHYReg(m,9,&value);
		printf("get phyno =%d	reg_val= 0x%x\n",m,value);
	}

	for(m=0;m<=7;m++){
		printf("set phyno =%d reg_val=0x%x\n",m,(value|0x8000));
		rtl8370_setAsicPHYReg(m,9,(value|0x8000));
	}

	for(m=0;m<=7;m++){
		rtl8370_getAsicPHYReg(m,9,&value);
		printf("get phyno =%d	reg_val= 0x%x\n",m,value);
	}

	return 0;
}

/*
@func ret_t | rtl8370_setAsicLedIndicateInfoConfig | Set Leds indicated information mode
@parm uint32 | ledno | LED group number. There are 1 to 1 led mapping to each port in each led group. 
@parm enum RTL8370_LEDCONF | config | Support 16 types configuration.
@rvalue RT_ERR_OK | Success.
@rvalue RT_ERR_SMI | SMI access error.
@comm
    The API can set LED indicated information configuration for each LED group with 1 to 1 led mapping to each port.
    Definition        LED Statuses            Description
    0000        LED_Off                LED pin Tri-State.
    0001        Dup/Col                Collision, Full duplex Indicator. Blinking every 43ms when collision happens. Low for full duplex, and high for half duplex mode.
    0010        Link/Act               Link, Activity Indicator. Low for link established. Link/Act Blinks every 43ms when the corresponding port is transmitting or receiving.
    0011        Spd1000                1000Mb/s Speed Indicator. Low for 1000Mb/s.
    0100        Spd100                 100Mb/s Speed Indicator. Low for 100Mb/s.
    0101        Spd10                  10Mb/s Speed Indicator. Low for 10Mb/s.
    0110        Spd1000/Act            1000Mb/s Speed/Activity Indicator. Low for 1000Mb/s. Blinks every 43ms when the corresponding port is transmitting or receiving.
    0111        Spd100/Act             100Mb/s Speed/Activity Indicator. Low for 100Mb/s. Blinks every 43ms when the corresponding port is transmitting or receiving.
    1000        Spd10/Act              10Mb/s Speed/Activity Indicator. Low for 10Mb/s. Blinks every 43ms when the corresponding port is transmitting or receiving.
    1001        Spd100 (10)/Act        10/100Mb/s Speed/Activity Indicator. Low for 10/100Mb/s. Blinks every 43ms when the corresponding port is transmitting or receiving.
    1010        Fiber                  Fiber link Indicator. Low for Fiber.
    1011        Fault                  Auto-negotiation     Fault Indicator. Low for Fault.
    1100        Link/Rx                Link, Activity Indicator. Low for link established. Link/Rx Blinks every 43ms when the corresponding port is transmitting.
    1101        Link/Tx                Link, Activity Indicator. Low for link established. Link/Tx Blinks every 43ms when the corresponding port is receiving.
    1110        Master                 Link on Master Indicator. Low for link Master established.
    1111        Act                    Activity Indicator. Low for link established. 
 */
ret_t rtl8370_setAsicLedIndicateInfoConfig(uint32 ledno, enum RTL8370_LEDCONF config)
{
    ret_t retVal;
    uint32 regData;
    CONST_T uint16 bits[RTL8370_LEDGROUPMAX+1]= { RTL8370_LED0_CFG_MASK, RTL8370_LED1_CFG_MASK, RTL8370_LED2_CFG_MASK};
    CONST_T uint16 offsets[RTL8370_LEDGROUPMAX+1]= { RTL8370_LED0_CFG_OFFSET, RTL8370_LED1_CFG_OFFSET, RTL8370_LED2_CFG_OFFSET};

    if(ledno > RTL8370_LEDGROUPMAX)
        return RT_ERR_INPUT;

    if(config > LEDCONF_ACT)    
        return RT_ERR_INPUT;

    retVal = rtl8370_getAsicReg(RTL8370_REG_LED_CONFIGURATION,&regData);  
	if( retVal !=  RT_ERR_OK)
		return retVal;

    regData = regData & (~RTL8370_LED_CONFIG_SEL_MASK);
    regData = regData & (~bits[ledno]);
    regData = regData | ((config & RTL8370_LED0_CFG_MASK)<<offsets[ledno]);

    retVal = rtl8370_setAsicReg(RTL8370_REG_LED_CONFIGURATION,regData);     

    return retVal;
}

static int linkmode[3] = {LEDCONF_LINK_ACT,LEDCONF_SPD1000,LEDCONF_SPD100};

int switch_init()
{
int i;
int val=0;
int txdelay = 1;
int rxdelay = 2;
rtk_port_mac_ability_t mac_cfg;
unsigned long flags;
//local_irq_save(flags);
smi_init(0, 1, 4);
#if 0
for(i=0;i<32;i++)
{
 MDC_MDIO_READ(32 , 1,i, &val);
 printf("%d: %x\n", i, val);
}
#endif
for(i=0;i<128;i++)
{
if((i&0xf) == 0)printf("\n");
RTL8367_getReg(0x2000+i, &val);
printf(" %04x", val);
}
printf("\n");
//macForceLinkExt01_set();

mac_cfg.forcemode = MAC_FORCE; 
mac_cfg.speed =  getenv("physpeed")?strtoul(getenv("physpeed"),0,0):SPD_1000M; 
mac_cfg.duplex = FULL_DUPLEX; 
mac_cfg.link = PORT_LINKUP;
mac_cfg.nway = DISABLED; 
mac_cfg.txpause = ENABLED; 
mac_cfg.rxpause = ENABLED; 
rtk_port_macForceLinkExt0_set(getenv("phytype")?strtoul(getenv("phytype"),0,0):MODE_EXT_RGMII,&mac_cfg);
rtk_port_macForceLinkExt1_set(getenv("phytype")?strtoul(getenv("phytype"),0,0):MODE_EXT_RGMII,&mac_cfg);
if(getenv("phytxdelay")) txdelay = strtoul(getenv("phytxdelay"), 0, 0);
if(getenv("phyrxdelay")) rxdelay = strtoul(getenv("phyrxdelay"), 0, 0);
txdelay %= 2;
rxdelay %= 8;
rtk_port_rgmiiDelayExt0_set(txdelay,rxdelay);
rtk_port_rgmiiDelayExt1_set(txdelay,rxdelay);
rtl8370_setAsicLedOperationMode(LEDOP_PARALLEL);
for(i=0;i<24;i++)
 rtl8370_setAsicLedIndicateInfoConfig(i,linkmode[i%3]);
//local_irq_restore(flags);

// test_switch_phy();
return 0;
}

#define G_OUTPUT		1
#define G_INPUT			0

static void i2c_sleep(int ntime)
{
	int b;
	_rtl865x_getGpioDataBit(smi_SDA, &b);
	delay(10);
}

void sda_dir(int ivalue)
{
    _rtl865x_initGpioPin(smi_SDA, GPIO_PERI_GPIO, ivalue?GPIO_DIR_OUT:GPIO_DIR_IN, GPIO_INT_DISABLE);
}

void scl_dir(int ivalue)
{
    _rtl865x_initGpioPin(smi_SCK, GPIO_PERI_GPIO, ivalue?GPIO_DIR_OUT:GPIO_DIR_IN, GPIO_INT_DISABLE);
}

void sda_bit(int ivalue)
{
    _rtl865x_setGpioDataBit(smi_SDA, ivalue);
}

void scl_bit(int ivalue)
{
    _rtl865x_setGpioDataBit(smi_SCK, ivalue);
}


static void i2c_start(void)
{
	sda_dir(G_OUTPUT);
	scl_dir(G_OUTPUT);
	scl_bit(0);
	i2c_sleep(1);
	sda_bit(1);
	i2c_sleep(1);
	scl_bit(1);
	i2c_sleep(5);
	sda_bit(0);
	i2c_sleep(5);
	scl_bit(0);
	i2c_sleep(2);
	
}
static void i2c_stop(void)
{
	sda_dir(G_OUTPUT);
	scl_dir(G_OUTPUT);
	scl_bit(0);
	i2c_sleep(1);
	sda_bit(0);
	i2c_sleep(1);
	scl_bit(1);
	i2c_sleep(5);
	sda_bit(1);
	i2c_sleep(5);
	scl_bit(0);
	i2c_sleep(2);
	
		
}

static void i2c_send_ack(int ack)
{
	sda_dir(G_OUTPUT);
	sda_bit(ack);
	i2c_sleep(3);
	scl_bit(1);
	i2c_sleep(5);
	scl_bit(0);
	i2c_sleep(2);
}

static char i2c_rec_ack()
{
        char res = 1;
        int num=10;
	int tmp;
        sda_dir(G_INPUT);
        i2c_sleep(3);
        scl_bit(1);
        i2c_sleep(5);
	_rtl865x_getGpioDataBit(smi_SDA, &tmp);

        //wait for a ack signal from slave

        while(tmp)
        {
                i2c_sleep(1);
                num--;
                if(!num)
                {
                        res = 0;
		//printf("no ack\n");
                        break;
                }
	_rtl865x_getGpioDataBit(smi_SDA, &tmp);
        }
        scl_bit(0);
        i2c_sleep(3);
        return res;
}


static unsigned char i2c_rec()
{
	int i;
	int tmp;
	unsigned char or_char;
	unsigned char value = 0x00;
	sda_dir(G_INPUT);
	for(i=7;i>=0;i--)
	{
		i2c_sleep(5);
		scl_bit(1);
		i2c_sleep(3);
	_rtl865x_getGpioDataBit(smi_SDA, &tmp);
		if(tmp)
			or_char=0x1;
		else
			or_char=0x0;
		or_char<<=i;
		value|=or_char;
		i2c_sleep(3);
		scl_bit(0);
	}
	return value;
}

static unsigned char i2c_send(unsigned char value)
{//we assume that now scl is 0
	int i;
	unsigned char and_char;
	sda_dir(G_OUTPUT);
	for(i=7;i>=0;i--)
	{
		and_char = value;
		and_char>>=i;
		and_char&=0x1;
		if(and_char)
			sda_bit(1);
		else
			sda_bit(0);
		i2c_sleep(1);
		scl_bit(1);
		i2c_sleep(5);
		scl_bit(0);
		i2c_sleep(1);
	}
	sda_bit(1);	
	return 1;
}


static char switchrom[]={
/*00000000:*/0xda,0x03,0x24,0x1b,0x00,0x00,0x25,0x1b,0x00,0x00,0x26,0x1b,0x00,0x00,0x27,0x1b,
/*00000010:*/0x00,0x00,0x7f,0x20,0x07,0x00,0x7e,0x20,0x0b,0x00,0x76,0x20,0x00,0x1a,0x7e,0x20,
/*00000020:*/0x0a,0x00,0x78,0x20,0x22,0x1d,0x7f,0x20,0x00,0x00,0x5f,0x20,0x07,0x00,0x5e,0x20,
/*00000030:*/0x0a,0x00,0x59,0x20,0x00,0x00,0x5a,0x20,0x00,0x00,0x5b,0x20,0x00,0x00,0x5c,0x20,
/*00000040:*/0x00,0x00,0x5e,0x20,0x0b,0x00,0x55,0x20,0x00,0x05,0x56,0x20,0x00,0x00,0x57,0x20,
/*00000050:*/0x00,0x00,0x58,0x20,0x00,0x00,0x5f,0x20,0x00,0x00,0x62,0x13,0x15,0x01,0x63,0x13,
/*00000060:*/0x02,0x00,0x63,0x13,0x00,0x00,0x3f,0x13,0x30,0x00,0x3e,0x13,0x0e,0x00,0x1f,0x22,
/*00000070:*/0x07,0x00,0x1e,0x22,0x40,0x00,0x18,0x22,0x00,0x00,0x1f,0x22,0x07,0x00,0x1e,0x22,
/*00000080:*/0x2c,0x00,0x18,0x22,0x8b,0x00,0x1f,0x22,0x05,0x00,0x05,0x22,0xf6,0xff,0x06,0x22,
/*00000090:*/0x80,0x00,0x1f,0x22,0x05,0x00,0x05,0x22,0x00,0x80,0x06,0x22,0x80,0x02,0x06,0x22,
/*000000a0:*/0xf7,0x2b,0x06,0x22,0xe0,0x00,0x06,0x22,0xf7,0xff,0x06,0x22,0x80,0xa0,0x06,0x22,
/*000000b0:*/0xae,0x02,0x06,0x22,0x02,0xf6,0x06,0x22,0x4e,0x80,0x06,0x22,0x01,0x02,0x06,0x22,
/*000000c0:*/0x02,0x50,0x06,0x22,0x63,0x01,0x06,0x22,0x01,0x02,0x06,0x22,0xe0,0x79,0x06,0x22,
/*000000d0:*/0x8c,0x8b,0x06,0x22,0x8b,0xe1,0x06,0x22,0x1e,0x8d,0x06,0x22,0xe1,0x01,0x06,0x22,
/*000000e0:*/0x8e,0x8b,0x06,0x22,0x01,0x1e,0x06,0x22,0x00,0xa0,0x06,0x22,0xae,0xe4,0x06,0x22,
/*000000f0:*/0xbf,0xd8,0x06,0x22,0x88,0x8b,0x06,0x22,0x00,0xec,0x06,0x22,0xa9,0x19,0x06,0x22,
/*00000100:*/0x90,0x8b,0x06,0x22,0xee,0xf9,0x06,0x22,0xf6,0xff,0x06,0x22,0xee,0x00,0x06,0x22,
/*00000110:*/0xf7,0xff,0x06,0x22,0xe0,0xfc,0x06,0x22,0x40,0xe1,0x06,0x22,0xe1,0xe1,0x06,0x22,
/*00000120:*/0xf7,0x41,0x06,0x22,0xf6,0x2f,0x06,0x22,0xe4,0x28,0x06,0x22,0x40,0xe1,0x06,0x22,
/*00000130:*/0xe1,0xe5,0x06,0x22,0x04,0x41,0x06,0x22,0xfa,0xf8,0x06,0x22,0x69,0xef,0x06,0x22,
/*00000140:*/0x8b,0xe0,0x06,0x22,0xac,0x86,0x06,0x22,0x1a,0x20,0x06,0x22,0x80,0xbf,0x06,0x22,
/*00000150:*/0xd0,0x77,0x06,0x22,0x02,0x6c,0x06,0x22,0x78,0x29,0x06,0x22,0xe0,0xe0,0x06,0x22,
/*00000160:*/0xe1,0xe4,0x06,0x22,0xe5,0xe0,0x06,0x22,0x06,0x58,0x06,0x22,0xc0,0x68,0x06,0x22,
/*00000170:*/0xd2,0xd1,0x06,0x22,0xe0,0xe4,0x06,0x22,0xe5,0xe4,0x06,0x22,0xe5,0xe0,0x06,0x22,
/*00000180:*/0x96,0xef,0x06,0x22,0xfc,0xfe,0x06,0x22,0x25,0x04,0x06,0x22,0x07,0x08,0x06,0x22,
/*00000190:*/0x40,0x26,0x06,0x22,0x27,0x72,0x06,0x22,0x7e,0x26,0x06,0x22,0x04,0x28,0x06,0x22,
/*000001a0:*/0x29,0xb7,0x06,0x22,0x76,0x25,0x06,0x22,0x68,0x2a,0x06,0x22,0x2b,0xe5,0x06,0x22,
/*000001b0:*/0x00,0xad,0x06,0x22,0xdb,0x2c,0x06,0x22,0x2d,0xf0,0x06,0x22,0xbb,0x67,0x06,0x22,
/*000001c0:*/0x7b,0x2e,0x06,0x22,0x2f,0x0f,0x06,0x22,0x65,0x73,0x06,0x22,0xac,0x31,0x06,0x22,
/*000001d0:*/0x32,0xcc,0x06,0x22,0x00,0x23,0x06,0x22,0x2d,0x33,0x06,0x22,0x34,0x17,0x06,0x22,
/*000001e0:*/0x52,0x7f,0x06,0x22,0x10,0x35,0x06,0x22,0x36,0x00,0x06,0x22,0x00,0x10,0x06,0x22,
/*000001f0:*/0x10,0x37,0x06,0x22,0x38,0x00,0x06,0x22,0xce,0x7f,0x06,0x22,0xe5,0x3c,0x06,0x22,
/*00000200:*/0x3d,0xf7,0x06,0x22,0xa4,0x3d,0x06,0x22,0x30,0x65,0x06,0x22,0x67,0x3e,0x06,0x22,
/*00000210:*/0x53,0x00,0x06,0x22,0xd2,0x69,0x06,0x22,0x6a,0x0f,0x06,0x22,0x2c,0x01,0x06,0x22,
/*00000220:*/0x2b,0x6c,0x06,0x22,0x6e,0x13,0x06,0x22,0x00,0xe1,0x06,0x22,0x12,0x6f,0x06,0x22,
/*00000230:*/0x71,0xf7,0x06,0x22,0x6b,0x00,0x06,0x22,0x06,0x73,0x06,0x22,0x74,0xeb,0x06,0x22,
/*00000240:*/0xc7,0x94,0x06,0x22,0x98,0x76,0x06,0x22,0x77,0x0a,0x06,0x22,0x00,0x50,0x06,0x22,
/*00000250:*/0x8a,0x78,0x06,0x22,0x79,0x14,0x06,0x22,0x6e,0x7f,0x06,0x22,0x06,0x7a,0x06,0x22,
/*00000260:*/0x00,0xa6,0x01,0x22,0x01,0x06,0x00,0x22,0x05,0x04,0x1f,0x22,0x00,0x00,0x1f,0x22,
/*00000270:*/0x07,0x00,0x1e,0x22,0x2d,0x00,0x18,0x22,0x30,0xf0,0x1e,0x22,0x23,0x00,0x16,0x22,
/*00000280:*/0x05,0x00,0x15,0x22,0x5c,0x00,0x19,0x22,0x68,0x00,0x15,0x22,0x82,0x00,0x19,0x22,
/*00000290:*/0x0a,0x00,0x15,0x22,0xa1,0x00,0x19,0x22,0x81,0x00,0x15,0x22,0xaf,0x00,0x19,0x22,
/*000002a0:*/0x80,0x00,0x15,0x22,0xd4,0x00,0x19,0x22,0x00,0x00,0x15,0x22,0xe4,0x00,0x19,0x22,
/*000002b0:*/0x81,0x00,0x15,0x22,0xe7,0x00,0x19,0x22,0x80,0x00,0x15,0x22,0x0d,0x01,0x19,0x22,
/*000002c0:*/0x83,0x00,0x15,0x22,0x18,0x01,0x19,0x22,0x83,0x00,0x15,0x22,0x20,0x01,0x19,0x22,
/*000002d0:*/0x82,0x00,0x15,0x22,0x9c,0x01,0x19,0x22,0x81,0x00,0x15,0x22,0xa4,0x01,0x19,0x22,
/*000002e0:*/0x80,0x00,0x15,0x22,0xcd,0x01,0x19,0x22,0x00,0x00,0x15,0x22,0xdd,0x01,0x19,0x22,
/*000002f0:*/0x81,0x00,0x15,0x22,0xe0,0x01,0x19,0x22,0x80,0x00,0x15,0x22,0x47,0x01,0x19,0x22,
/*00000300:*/0x96,0x00,0x16,0x22,0x00,0x00,0x1e,0x22,0x2d,0x00,0x18,0x22,0x10,0xf0,0x1f,0x22,
/*00000310:*/0x07,0x00,0x1e,0x22,0x20,0x00,0x15,0x22,0x00,0x01,0x1f,0x22,0x05,0x00,0x05,0x22,
/*00000320:*/0x84,0x8b,0x06,0x22,0x62,0x00,0x1f,0x22,0x00,0x00,0x0d,0x22,0x03,0x00,0x0e,0x22,
/*00000330:*/0x15,0x00,0x0d,0x22,0x03,0x40,0x0e,0x22,0x06,0x00,0x3f,0x13,0x10,0x00,0x3e,0x13,
/*00000340:*/0xfe,0x0f,0xa4,0x12,0x0a,0x38,0x18,0x00,0x00,0x0c,0x38,0x00,0x00,0x0c,0x58,0x00,
/*00000350:*/0x00,0x0c,0x78,0x00,0x00,0x0c,0x98,0x00,0x00,0x0c,0xb8,0x00,0x00,0x0c,0xd8,0x00,
/*00000360:*/0x00,0x0c,0xf8,0x00,0x00,0x0c,0x05,0x13,0x60,0x00,0x11,0x13,0x76,0x10,0x06,0x13,
/*00000370:*/0x0c,0x00,0x07,0x13,0x0c,0x00,0x03,0x13,0x67,0x03,0x04,0x13,0x77,0x77,0x03,0x12,
/*00000380:*/0x00,0xff,0x00,0x12,0xc4,0x7f,0x65,0x08,0x10,0x32,0x7b,0x08,0x00,0x00,0x7c,0x08,
/*00000390:*/0x00,0xff,0x7d,0x08,0x00,0x00,0x7e,0x08,0x00,0x00,0x01,0x08,0x00,0x01,0x02,0x08,
/*000003a0:*/0x00,0x01,0x20,0x0a,0x40,0x20,0x21,0x0a,0x40,0x20,0x22,0x0a,0x40,0x20,0x23,0x0a,
/*000003b0:*/0x40,0x20,0x24,0x0a,0x40,0x20,0x25,0x0a,0x40,0x20,0x26,0x0a,0x40,0x20,0x27,0x0a,
/*000003c0:*/0x40,0x20,0x28,0x0a,0x40,0x20,0x29,0x0a,0x40,0x20,0x0c,0x13,0x50,0x00,0x03,0x1b,
/*000003d0:*/0x4f,0x00,0x00,0x1b,0xf7,0x14,0x26,0x1b,0x03,0x00,0xff,0xff,0xff,0xff,0xff,0xff,
/*000003e0:*/0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
/*000003f0:*/0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};

#define I2C_WRITE 0
#define I2C_READ 1

static char switchrom[0x400];
int program_rom()
{
int addr;
int i;
smi_init(0, 1, 4);

for(addr=0;addr<0x400;)
{
i2c_start();	
i2c_send(0xa0|(((addr>>8)&3)<<1)|I2C_WRITE);
if(!i2c_rec_ack()) { i2c_stop(); continue; }
i2c_send(addr&0xff);
if(!i2c_rec_ack()) { i2c_stop(); continue; }
//for(i=0;i<16;i++,addr++)
{
i2c_send(switchrom[addr]);
if(!i2c_rec_ack()) { i2c_stop(); continue; }
}
i2c_stop();
addr++;
}
}

static unsigned char tmpbuf[0x400];
int read_rom()
{
int addr;
unsigned char c;
smi_init(0, 1, 4);

addr = 0;
i2c_start();	
i2c_send(0xa0|(((addr>>8)&3)<<1)|I2C_WRITE);
i2c_rec_ack();
i2c_send(0);
i2c_rec_ack();
i2c_start();	
i2c_send(0xa0|(((addr>>8)&3)<<1)|I2C_READ);
i2c_rec_ack();
for(addr=0;addr<0x400;addr++)
{
tmpbuf[addr]=i2c_rec();
if(addr<0x400-1)
 i2c_send_ack(0);
else
 i2c_send_ack(1);
}
i2c_stop();

for(addr=0;addr<0x400;addr++)
{
if((addr&0xf)==0) printf("\n");
printf(" %02x", tmpbuf[addr]);
}
printf("\n");
}

static const Cmd Cmds[] = {
	{"MyCmds"},
	{"read_switchrom", "", 0, "", read_rom, 0, 99, CMD_REPEAT},
	{"program_switchrom", "", 0, "", program_rom, 0, 99, CMD_REPEAT},
	{0, 0}
};

static void init_cmd __P((void)) __attribute__ ((constructor));

static void init_cmd()
{
	cmdlist_expand(Cmds, 1);
}

